1 /*
2  * Copyright © 2014 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #include <linux/firmware.h>
26 
27 #include "i915_drv.h"
28 #include "i915_reg.h"
29 #include "intel_de.h"
30 #include "intel_dmc.h"
31 #include "intel_dmc_regs.h"
32 
33 /**
34  * DOC: DMC Firmware Support
35  *
36  * From gen9 onwards we have newly added DMC (Display microcontroller) in display
37  * engine to save and restore the state of display engine when it enter into
38  * low-power state and comes back to normal.
39  */
40 
41 #define DMC_VERSION(major, minor)	((major) << 16 | (minor))
42 #define DMC_VERSION_MAJOR(version)	((version) >> 16)
43 #define DMC_VERSION_MINOR(version)	((version) & 0xffff)
44 
45 #define DMC_PATH(platform, major, minor) \
46 	"i915/"				 \
47 	__stringify(platform) "_dmc_ver" \
48 	__stringify(major) "_"		 \
49 	__stringify(minor) ".bin"
50 
51 #define DISPLAY_VER13_DMC_MAX_FW_SIZE	0x20000
52 
53 #define DISPLAY_VER12_DMC_MAX_FW_SIZE	ICL_DMC_MAX_FW_SIZE
54 
55 #define DG2_DMC_PATH			DMC_PATH(dg2, 2, 07)
56 #define DG2_DMC_VERSION_REQUIRED	DMC_VERSION(2, 07)
57 MODULE_FIRMWARE(DG2_DMC_PATH);
58 
59 #define ADLP_DMC_PATH			DMC_PATH(adlp, 2, 16)
60 #define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 16)
61 MODULE_FIRMWARE(ADLP_DMC_PATH);
62 
63 #define ADLS_DMC_PATH			DMC_PATH(adls, 2, 01)
64 #define ADLS_DMC_VERSION_REQUIRED	DMC_VERSION(2, 1)
65 MODULE_FIRMWARE(ADLS_DMC_PATH);
66 
67 #define DG1_DMC_PATH			DMC_PATH(dg1, 2, 02)
68 #define DG1_DMC_VERSION_REQUIRED	DMC_VERSION(2, 2)
69 MODULE_FIRMWARE(DG1_DMC_PATH);
70 
71 #define RKL_DMC_PATH			DMC_PATH(rkl, 2, 03)
72 #define RKL_DMC_VERSION_REQUIRED	DMC_VERSION(2, 3)
73 MODULE_FIRMWARE(RKL_DMC_PATH);
74 
75 #define TGL_DMC_PATH			DMC_PATH(tgl, 2, 12)
76 #define TGL_DMC_VERSION_REQUIRED	DMC_VERSION(2, 12)
77 MODULE_FIRMWARE(TGL_DMC_PATH);
78 
79 #define ICL_DMC_PATH			DMC_PATH(icl, 1, 09)
80 #define ICL_DMC_VERSION_REQUIRED	DMC_VERSION(1, 9)
81 #define ICL_DMC_MAX_FW_SIZE		0x6000
82 MODULE_FIRMWARE(ICL_DMC_PATH);
83 
84 #define GLK_DMC_PATH			DMC_PATH(glk, 1, 04)
85 #define GLK_DMC_VERSION_REQUIRED	DMC_VERSION(1, 4)
86 #define GLK_DMC_MAX_FW_SIZE		0x4000
87 MODULE_FIRMWARE(GLK_DMC_PATH);
88 
89 #define KBL_DMC_PATH			DMC_PATH(kbl, 1, 04)
90 #define KBL_DMC_VERSION_REQUIRED	DMC_VERSION(1, 4)
91 #define KBL_DMC_MAX_FW_SIZE		BXT_DMC_MAX_FW_SIZE
92 MODULE_FIRMWARE(KBL_DMC_PATH);
93 
94 #define SKL_DMC_PATH			DMC_PATH(skl, 1, 27)
95 #define SKL_DMC_VERSION_REQUIRED	DMC_VERSION(1, 27)
96 #define SKL_DMC_MAX_FW_SIZE		BXT_DMC_MAX_FW_SIZE
97 MODULE_FIRMWARE(SKL_DMC_PATH);
98 
99 #define BXT_DMC_PATH			DMC_PATH(bxt, 1, 07)
100 #define BXT_DMC_VERSION_REQUIRED	DMC_VERSION(1, 7)
101 #define BXT_DMC_MAX_FW_SIZE		0x3000
102 MODULE_FIRMWARE(BXT_DMC_PATH);
103 
104 #define DMC_DEFAULT_FW_OFFSET		0xFFFFFFFF
105 #define PACKAGE_MAX_FW_INFO_ENTRIES	20
106 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES	32
107 #define DMC_V1_MAX_MMIO_COUNT		8
108 #define DMC_V3_MAX_MMIO_COUNT		20
109 #define DMC_V1_MMIO_START_RANGE		0x80000
110 
111 struct intel_css_header {
112 	/* 0x09 for DMC */
113 	u32 module_type;
114 
115 	/* Includes the DMC specific header in dwords */
116 	u32 header_len;
117 
118 	/* always value would be 0x10000 */
119 	u32 header_ver;
120 
121 	/* Not used */
122 	u32 module_id;
123 
124 	/* Not used */
125 	u32 module_vendor;
126 
127 	/* in YYYYMMDD format */
128 	u32 date;
129 
130 	/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
131 	u32 size;
132 
133 	/* Not used */
134 	u32 key_size;
135 
136 	/* Not used */
137 	u32 modulus_size;
138 
139 	/* Not used */
140 	u32 exponent_size;
141 
142 	/* Not used */
143 	u32 reserved1[12];
144 
145 	/* Major Minor */
146 	u32 version;
147 
148 	/* Not used */
149 	u32 reserved2[8];
150 
151 	/* Not used */
152 	u32 kernel_header_info;
153 } __packed;
154 
155 struct intel_fw_info {
156 	u8 reserved1;
157 
158 	/* reserved on package_header version 1, must be 0 on version 2 */
159 	u8 dmc_id;
160 
161 	/* Stepping (A, B, C, ..., *). * is a wildcard */
162 	char stepping;
163 
164 	/* Sub-stepping (0, 1, ..., *). * is a wildcard */
165 	char substepping;
166 
167 	u32 offset;
168 	u32 reserved2;
169 } __packed;
170 
171 struct intel_package_header {
172 	/* DMC container header length in dwords */
173 	u8 header_len;
174 
175 	/* 0x01, 0x02 */
176 	u8 header_ver;
177 
178 	u8 reserved[10];
179 
180 	/* Number of valid entries in the FWInfo array below */
181 	u32 num_entries;
182 } __packed;
183 
184 struct intel_dmc_header_base {
185 	/* always value would be 0x40403E3E */
186 	u32 signature;
187 
188 	/* DMC binary header length */
189 	u8 header_len;
190 
191 	/* 0x01 */
192 	u8 header_ver;
193 
194 	/* Reserved */
195 	u16 dmcc_ver;
196 
197 	/* Major, Minor */
198 	u32 project;
199 
200 	/* Firmware program size (excluding header) in dwords */
201 	u32 fw_size;
202 
203 	/* Major Minor version */
204 	u32 fw_version;
205 } __packed;
206 
207 struct intel_dmc_header_v1 {
208 	struct intel_dmc_header_base base;
209 
210 	/* Number of valid MMIO cycles present. */
211 	u32 mmio_count;
212 
213 	/* MMIO address */
214 	u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT];
215 
216 	/* MMIO data */
217 	u32 mmiodata[DMC_V1_MAX_MMIO_COUNT];
218 
219 	/* FW filename  */
220 	char dfile[32];
221 
222 	u32 reserved1[2];
223 } __packed;
224 
225 struct intel_dmc_header_v3 {
226 	struct intel_dmc_header_base base;
227 
228 	/* DMC RAM start MMIO address */
229 	u32 start_mmioaddr;
230 
231 	u32 reserved[9];
232 
233 	/* FW filename */
234 	char dfile[32];
235 
236 	/* Number of valid MMIO cycles present. */
237 	u32 mmio_count;
238 
239 	/* MMIO address */
240 	u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT];
241 
242 	/* MMIO data */
243 	u32 mmiodata[DMC_V3_MAX_MMIO_COUNT];
244 } __packed;
245 
246 struct stepping_info {
247 	char stepping;
248 	char substepping;
249 };
250 
251 static bool has_dmc_id_fw(struct drm_i915_private *i915, int dmc_id)
252 {
253 	return i915->display.dmc.dmc_info[dmc_id].payload;
254 }
255 
256 bool intel_dmc_has_payload(struct drm_i915_private *i915)
257 {
258 	return has_dmc_id_fw(i915, DMC_FW_MAIN);
259 }
260 
261 static const struct stepping_info *
262 intel_get_stepping_info(struct drm_i915_private *i915,
263 			struct stepping_info *si)
264 {
265 	const char *step_name = intel_step_name(RUNTIME_INFO(i915)->step.display_step);
266 
267 	si->stepping = step_name[0];
268 	si->substepping = step_name[1];
269 	return si;
270 }
271 
272 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
273 {
274 	/* The below bit doesn't need to be cleared ever afterwards */
275 	intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
276 		     DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
277 	intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
278 }
279 
280 static void disable_event_handler(struct drm_i915_private *i915,
281 				  i915_reg_t ctl_reg, i915_reg_t htp_reg)
282 {
283 	intel_de_write(i915, ctl_reg,
284 		       REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
285 				      DMC_EVT_CTL_TYPE_EDGE_0_1) |
286 		       REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
287 				      DMC_EVT_CTL_EVENT_ID_FALSE));
288 	intel_de_write(i915, htp_reg, 0);
289 }
290 
291 static void
292 disable_flip_queue_event(struct drm_i915_private *i915,
293 			 i915_reg_t ctl_reg, i915_reg_t htp_reg)
294 {
295 	u32 event_ctl;
296 	u32 event_htp;
297 
298 	event_ctl = intel_de_read(i915, ctl_reg);
299 	event_htp = intel_de_read(i915, htp_reg);
300 	if (event_ctl != (DMC_EVT_CTL_ENABLE |
301 			  DMC_EVT_CTL_RECURRING |
302 			  REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
303 					 DMC_EVT_CTL_TYPE_EDGE_0_1) |
304 			  REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
305 					 DMC_EVT_CTL_EVENT_ID_CLK_MSEC)) ||
306 	    !event_htp) {
307 		drm_dbg_kms(&i915->drm,
308 			    "Unexpected DMC event configuration (control %08x htp %08x)\n",
309 			    event_ctl, event_htp);
310 		return;
311 	}
312 
313 	disable_event_handler(i915, ctl_reg, htp_reg);
314 }
315 
316 static bool
317 get_flip_queue_event_regs(struct drm_i915_private *i915, int dmc_id,
318 			  i915_reg_t *ctl_reg, i915_reg_t *htp_reg)
319 {
320 	switch (dmc_id) {
321 	case DMC_FW_MAIN:
322 		if (DISPLAY_VER(i915) == 12) {
323 			*ctl_reg = DMC_EVT_CTL(i915, dmc_id, 3);
324 			*htp_reg = DMC_EVT_HTP(i915, dmc_id, 3);
325 
326 			return true;
327 		}
328 		break;
329 	case DMC_FW_PIPEA ... DMC_FW_PIPED:
330 		if (IS_DG2(i915)) {
331 			*ctl_reg = DMC_EVT_CTL(i915, dmc_id, 2);
332 			*htp_reg = DMC_EVT_HTP(i915, dmc_id, 2);
333 
334 			return true;
335 		}
336 		break;
337 	}
338 
339 	return false;
340 }
341 
342 static void
343 disable_all_flip_queue_events(struct drm_i915_private *i915)
344 {
345 	int dmc_id;
346 
347 	/* TODO: check if the following applies to all D13+ platforms. */
348 	if (!IS_DG2(i915) && !IS_TIGERLAKE(i915))
349 		return;
350 
351 	for (dmc_id = 0; dmc_id < DMC_FW_MAX; dmc_id++) {
352 		i915_reg_t ctl_reg;
353 		i915_reg_t htp_reg;
354 
355 		if (!has_dmc_id_fw(i915, dmc_id))
356 			continue;
357 
358 		if (!get_flip_queue_event_regs(i915, dmc_id, &ctl_reg, &htp_reg))
359 			continue;
360 
361 		disable_flip_queue_event(i915, ctl_reg, htp_reg);
362 	}
363 }
364 
365 static void disable_all_event_handlers(struct drm_i915_private *i915)
366 {
367 	int id;
368 
369 	/* TODO: disable the event handlers on pre-GEN12 platforms as well */
370 	if (DISPLAY_VER(i915) < 12)
371 		return;
372 
373 	for (id = DMC_FW_MAIN; id < DMC_FW_MAX; id++) {
374 		int handler;
375 
376 		if (!has_dmc_id_fw(i915, id))
377 			continue;
378 
379 		for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++)
380 			disable_event_handler(i915,
381 					      DMC_EVT_CTL(i915, id, handler),
382 					      DMC_EVT_HTP(i915, id, handler));
383 	}
384 }
385 
386 static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
387 {
388 	enum pipe pipe;
389 
390 	if (DISPLAY_VER(i915) != 13)
391 		return;
392 
393 	/*
394 	 * Wa_16015201720:adl-p,dg2
395 	 * The WA requires clock gating to be disabled all the time
396 	 * for pipe A and B.
397 	 * For pipe C and D clock gating needs to be disabled only
398 	 * during initializing the firmware.
399 	 */
400 	if (enable)
401 		for (pipe = PIPE_A; pipe <= PIPE_D; pipe++)
402 			intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe),
403 				     0, PIPEDMC_GATING_DIS);
404 	else
405 		for (pipe = PIPE_C; pipe <= PIPE_D; pipe++)
406 			intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe),
407 				     PIPEDMC_GATING_DIS, 0);
408 }
409 
410 /**
411  * intel_dmc_load_program() - write the firmware from memory to register.
412  * @dev_priv: i915 drm device.
413  *
414  * DMC firmware is read from a .bin file and kept in internal memory one time.
415  * Everytime display comes back from low power state this function is called to
416  * copy the firmware from internal memory to registers.
417  */
418 void intel_dmc_load_program(struct drm_i915_private *dev_priv)
419 {
420 	struct intel_dmc *dmc = &dev_priv->display.dmc;
421 	u32 id, i;
422 
423 	if (!intel_dmc_has_payload(dev_priv))
424 		return;
425 
426 	pipedmc_clock_gating_wa(dev_priv, true);
427 
428 	disable_all_event_handlers(dev_priv);
429 
430 	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
431 
432 	preempt_disable();
433 
434 	for (id = 0; id < DMC_FW_MAX; id++) {
435 		for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) {
436 			intel_uncore_write_fw(&dev_priv->uncore,
437 					      DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i),
438 					      dmc->dmc_info[id].payload[i]);
439 		}
440 	}
441 
442 	preempt_enable();
443 
444 	for (id = 0; id < DMC_FW_MAX; id++) {
445 		for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) {
446 			intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i],
447 				       dmc->dmc_info[id].mmiodata[i]);
448 		}
449 	}
450 
451 	dev_priv->display.dmc.dc_state = 0;
452 
453 	gen9_set_dc_state_debugmask(dev_priv);
454 
455 	/*
456 	 * Flip queue events need to be disabled before enabling DC5/6.
457 	 * i915 doesn't use the flip queue feature, so disable it already
458 	 * here.
459 	 */
460 	disable_all_flip_queue_events(dev_priv);
461 
462 	pipedmc_clock_gating_wa(dev_priv, false);
463 }
464 
465 /**
466  * intel_dmc_disable_program() - disable the firmware
467  * @i915: i915 drm device
468  *
469  * Disable all event handlers in the firmware, making sure the firmware is
470  * inactive after the display is uninitialized.
471  */
472 void intel_dmc_disable_program(struct drm_i915_private *i915)
473 {
474 	if (!intel_dmc_has_payload(i915))
475 		return;
476 
477 	pipedmc_clock_gating_wa(i915, true);
478 	disable_all_event_handlers(i915);
479 	pipedmc_clock_gating_wa(i915, false);
480 }
481 
482 void assert_dmc_loaded(struct drm_i915_private *i915)
483 {
484 	drm_WARN_ONCE(&i915->drm,
485 		      !intel_de_read(i915, DMC_PROGRAM(i915->display.dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
486 		      "DMC program storage start is NULL\n");
487 	drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE),
488 		      "DMC SSP Base Not fine\n");
489 	drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL),
490 		      "DMC HTP Not fine\n");
491 }
492 
493 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
494 				     const struct stepping_info *si)
495 {
496 	if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) ||
497 	    (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) ||
498 	    /*
499 	     * If we don't find a more specific one from above two checks, we
500 	     * then check for the generic one to be sure to work even with
501 	     * "broken firmware"
502 	     */
503 	    (si->stepping == '*' && si->substepping == fw_info->substepping) ||
504 	    (fw_info->stepping == '*' && fw_info->substepping == '*'))
505 		return true;
506 
507 	return false;
508 }
509 
510 /*
511  * Search fw_info table for dmc_offset to find firmware binary: num_entries is
512  * already sanitized.
513  */
514 static void dmc_set_fw_offset(struct intel_dmc *dmc,
515 			      const struct intel_fw_info *fw_info,
516 			      unsigned int num_entries,
517 			      const struct stepping_info *si,
518 			      u8 package_ver)
519 {
520 	unsigned int i, id;
521 
522 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
523 
524 	for (i = 0; i < num_entries; i++) {
525 		id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
526 
527 		if (id >= DMC_FW_MAX) {
528 			drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", id);
529 			continue;
530 		}
531 
532 		/* More specific versions come first, so we don't even have to
533 		 * check for the stepping since we already found a previous FW
534 		 * for this id.
535 		 */
536 		if (dmc->dmc_info[id].present)
537 			continue;
538 
539 		if (fw_info_matches_stepping(&fw_info[i], si)) {
540 			dmc->dmc_info[id].present = true;
541 			dmc->dmc_info[id].dmc_offset = fw_info[i].offset;
542 		}
543 	}
544 }
545 
546 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
547 				       const u32 *mmioaddr, u32 mmio_count,
548 				       int header_ver, u8 dmc_id)
549 {
550 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
551 	u32 start_range, end_range;
552 	int i;
553 
554 	if (dmc_id >= DMC_FW_MAX) {
555 		drm_warn(&i915->drm, "Unsupported firmware id %u\n", dmc_id);
556 		return false;
557 	}
558 
559 	if (header_ver == 1) {
560 		start_range = DMC_MMIO_START_RANGE;
561 		end_range = DMC_MMIO_END_RANGE;
562 	} else if (dmc_id == DMC_FW_MAIN) {
563 		start_range = TGL_MAIN_MMIO_START;
564 		end_range = TGL_MAIN_MMIO_END;
565 	} else if (DISPLAY_VER(i915) >= 13) {
566 		start_range = ADLP_PIPE_MMIO_START;
567 		end_range = ADLP_PIPE_MMIO_END;
568 	} else if (DISPLAY_VER(i915) >= 12) {
569 		start_range = TGL_PIPE_MMIO_START(dmc_id);
570 		end_range = TGL_PIPE_MMIO_END(dmc_id);
571 	} else {
572 		drm_warn(&i915->drm, "Unknown mmio range for sanity check");
573 		return false;
574 	}
575 
576 	for (i = 0; i < mmio_count; i++) {
577 		if (mmioaddr[i] < start_range || mmioaddr[i] > end_range)
578 			return false;
579 	}
580 
581 	return true;
582 }
583 
584 static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
585 			       const struct intel_dmc_header_base *dmc_header,
586 			       size_t rem_size, u8 dmc_id)
587 {
588 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
589 	struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
590 	unsigned int header_len_bytes, dmc_header_size, payload_size, i;
591 	const u32 *mmioaddr, *mmiodata;
592 	u32 mmio_count, mmio_count_max, start_mmioaddr;
593 	u8 *payload;
594 
595 	BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
596 		     ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
597 
598 	/*
599 	 * Check if we can access common fields, we will checkc again below
600 	 * after we have read the version
601 	 */
602 	if (rem_size < sizeof(struct intel_dmc_header_base))
603 		goto error_truncated;
604 
605 	/* Cope with small differences between v1 and v3 */
606 	if (dmc_header->header_ver == 3) {
607 		const struct intel_dmc_header_v3 *v3 =
608 			(const struct intel_dmc_header_v3 *)dmc_header;
609 
610 		if (rem_size < sizeof(struct intel_dmc_header_v3))
611 			goto error_truncated;
612 
613 		mmioaddr = v3->mmioaddr;
614 		mmiodata = v3->mmiodata;
615 		mmio_count = v3->mmio_count;
616 		mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
617 		/* header_len is in dwords */
618 		header_len_bytes = dmc_header->header_len * 4;
619 		start_mmioaddr = v3->start_mmioaddr;
620 		dmc_header_size = sizeof(*v3);
621 	} else if (dmc_header->header_ver == 1) {
622 		const struct intel_dmc_header_v1 *v1 =
623 			(const struct intel_dmc_header_v1 *)dmc_header;
624 
625 		if (rem_size < sizeof(struct intel_dmc_header_v1))
626 			goto error_truncated;
627 
628 		mmioaddr = v1->mmioaddr;
629 		mmiodata = v1->mmiodata;
630 		mmio_count = v1->mmio_count;
631 		mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
632 		header_len_bytes = dmc_header->header_len;
633 		start_mmioaddr = DMC_V1_MMIO_START_RANGE;
634 		dmc_header_size = sizeof(*v1);
635 	} else {
636 		drm_err(&i915->drm, "Unknown DMC fw header version: %u\n",
637 			dmc_header->header_ver);
638 		return 0;
639 	}
640 
641 	if (header_len_bytes != dmc_header_size) {
642 		drm_err(&i915->drm, "DMC firmware has wrong dmc header length "
643 			"(%u bytes)\n", header_len_bytes);
644 		return 0;
645 	}
646 
647 	/* Cache the dmc header info. */
648 	if (mmio_count > mmio_count_max) {
649 		drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);
650 		return 0;
651 	}
652 
653 	if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count,
654 					dmc_header->header_ver, dmc_id)) {
655 		drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n");
656 		return 0;
657 	}
658 
659 	for (i = 0; i < mmio_count; i++) {
660 		dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
661 		dmc_info->mmiodata[i] = mmiodata[i];
662 	}
663 	dmc_info->mmio_count = mmio_count;
664 	dmc_info->start_mmioaddr = start_mmioaddr;
665 
666 	rem_size -= header_len_bytes;
667 
668 	/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
669 	payload_size = dmc_header->fw_size * 4;
670 	if (rem_size < payload_size)
671 		goto error_truncated;
672 
673 	if (payload_size > dmc->max_fw_size) {
674 		drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size);
675 		return 0;
676 	}
677 	dmc_info->dmc_fw_size = dmc_header->fw_size;
678 
679 	dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
680 	if (!dmc_info->payload)
681 		return 0;
682 
683 	payload = (u8 *)(dmc_header) + header_len_bytes;
684 	memcpy(dmc_info->payload, payload, payload_size);
685 
686 	return header_len_bytes + payload_size;
687 
688 error_truncated:
689 	drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
690 	return 0;
691 }
692 
693 static u32
694 parse_dmc_fw_package(struct intel_dmc *dmc,
695 		     const struct intel_package_header *package_header,
696 		     const struct stepping_info *si,
697 		     size_t rem_size)
698 {
699 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
700 	u32 package_size = sizeof(struct intel_package_header);
701 	u32 num_entries, max_entries;
702 	const struct intel_fw_info *fw_info;
703 
704 	if (rem_size < package_size)
705 		goto error_truncated;
706 
707 	if (package_header->header_ver == 1) {
708 		max_entries = PACKAGE_MAX_FW_INFO_ENTRIES;
709 	} else if (package_header->header_ver == 2) {
710 		max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
711 	} else {
712 		drm_err(&i915->drm, "DMC firmware has unknown header version %u\n",
713 			package_header->header_ver);
714 		return 0;
715 	}
716 
717 	/*
718 	 * We should always have space for max_entries,
719 	 * even if not all are used
720 	 */
721 	package_size += max_entries * sizeof(struct intel_fw_info);
722 	if (rem_size < package_size)
723 		goto error_truncated;
724 
725 	if (package_header->header_len * 4 != package_size) {
726 		drm_err(&i915->drm, "DMC firmware has wrong package header length "
727 			"(%u bytes)\n", package_size);
728 		return 0;
729 	}
730 
731 	num_entries = package_header->num_entries;
732 	if (WARN_ON(package_header->num_entries > max_entries))
733 		num_entries = max_entries;
734 
735 	fw_info = (const struct intel_fw_info *)
736 		((u8 *)package_header + sizeof(*package_header));
737 	dmc_set_fw_offset(dmc, fw_info, num_entries, si,
738 			  package_header->header_ver);
739 
740 	/* dmc_offset is in dwords */
741 	return package_size;
742 
743 error_truncated:
744 	drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
745 	return 0;
746 }
747 
748 /* Return number of bytes parsed or 0 on error */
749 static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
750 			    struct intel_css_header *css_header,
751 			    size_t rem_size)
752 {
753 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
754 
755 	if (rem_size < sizeof(struct intel_css_header)) {
756 		drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
757 		return 0;
758 	}
759 
760 	if (sizeof(struct intel_css_header) !=
761 	    (css_header->header_len * 4)) {
762 		drm_err(&i915->drm, "DMC firmware has wrong CSS header length "
763 			"(%u bytes)\n",
764 			(css_header->header_len * 4));
765 		return 0;
766 	}
767 
768 	if (dmc->required_version &&
769 	    css_header->version != dmc->required_version) {
770 		drm_info(&i915->drm, "Refusing to load DMC firmware v%u.%u,"
771 			 " please use v%u.%u\n",
772 			 DMC_VERSION_MAJOR(css_header->version),
773 			 DMC_VERSION_MINOR(css_header->version),
774 			 DMC_VERSION_MAJOR(dmc->required_version),
775 			 DMC_VERSION_MINOR(dmc->required_version));
776 		return 0;
777 	}
778 
779 	dmc->version = css_header->version;
780 
781 	return sizeof(struct intel_css_header);
782 }
783 
784 static void parse_dmc_fw(struct drm_i915_private *dev_priv,
785 			 const struct firmware *fw)
786 {
787 	struct intel_css_header *css_header;
788 	struct intel_package_header *package_header;
789 	struct intel_dmc_header_base *dmc_header;
790 	struct intel_dmc *dmc = &dev_priv->display.dmc;
791 	struct stepping_info display_info = { '*', '*'};
792 	const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info);
793 	u32 readcount = 0;
794 	u32 r, offset;
795 	int id;
796 
797 	if (!fw)
798 		return;
799 
800 	/* Extract CSS Header information */
801 	css_header = (struct intel_css_header *)fw->data;
802 	r = parse_dmc_fw_css(dmc, css_header, fw->size);
803 	if (!r)
804 		return;
805 
806 	readcount += r;
807 
808 	/* Extract Package Header information */
809 	package_header = (struct intel_package_header *)&fw->data[readcount];
810 	r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount);
811 	if (!r)
812 		return;
813 
814 	readcount += r;
815 
816 	for (id = 0; id < DMC_FW_MAX; id++) {
817 		if (!dev_priv->display.dmc.dmc_info[id].present)
818 			continue;
819 
820 		offset = readcount + dmc->dmc_info[id].dmc_offset * 4;
821 		if (offset > fw->size) {
822 			drm_err(&dev_priv->drm, "Reading beyond the fw_size\n");
823 			continue;
824 		}
825 
826 		dmc_header = (struct intel_dmc_header_base *)&fw->data[offset];
827 		parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id);
828 	}
829 }
830 
831 static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
832 {
833 	drm_WARN_ON(&dev_priv->drm, dev_priv->display.dmc.wakeref);
834 	dev_priv->display.dmc.wakeref =
835 		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
836 }
837 
838 static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv)
839 {
840 	intel_wakeref_t wakeref __maybe_unused =
841 		fetch_and_zero(&dev_priv->display.dmc.wakeref);
842 
843 	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
844 }
845 
846 static void dmc_load_work_fn(struct work_struct *work)
847 {
848 	struct drm_i915_private *dev_priv;
849 	struct intel_dmc *dmc;
850 	const struct firmware *fw = NULL;
851 
852 	dev_priv = container_of(work, typeof(*dev_priv), display.dmc.work);
853 	dmc = &dev_priv->display.dmc;
854 
855 	request_firmware(&fw, dev_priv->display.dmc.fw_path, dev_priv->drm.dev);
856 	parse_dmc_fw(dev_priv, fw);
857 
858 	if (intel_dmc_has_payload(dev_priv)) {
859 		intel_dmc_load_program(dev_priv);
860 		intel_dmc_runtime_pm_put(dev_priv);
861 
862 		drm_info(&dev_priv->drm,
863 			 "Finished loading DMC firmware %s (v%u.%u)\n",
864 			 dev_priv->display.dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
865 			 DMC_VERSION_MINOR(dmc->version));
866 	} else {
867 		drm_notice(&dev_priv->drm,
868 			   "Failed to load DMC firmware %s."
869 			   " Disabling runtime power management.\n",
870 			   dmc->fw_path);
871 		drm_notice(&dev_priv->drm, "DMC firmware homepage: %s",
872 			   INTEL_UC_FIRMWARE_URL);
873 	}
874 
875 	release_firmware(fw);
876 }
877 
878 /**
879  * intel_dmc_ucode_init() - initialize the firmware loading.
880  * @dev_priv: i915 drm device.
881  *
882  * This function is called at the time of loading the display driver to read
883  * firmware from a .bin file and copied into a internal memory.
884  */
885 void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
886 {
887 	struct intel_dmc *dmc = &dev_priv->display.dmc;
888 
889 	INIT_WORK(&dev_priv->display.dmc.work, dmc_load_work_fn);
890 
891 	if (!HAS_DMC(dev_priv))
892 		return;
893 
894 	/*
895 	 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering
896 	 * runtime-suspend.
897 	 *
898 	 * On error, we return with the rpm wakeref held to prevent runtime
899 	 * suspend as runtime suspend *requires* a working DMC for whatever
900 	 * reason.
901 	 */
902 	intel_dmc_runtime_pm_get(dev_priv);
903 
904 	if (IS_DG2(dev_priv)) {
905 		dmc->fw_path = DG2_DMC_PATH;
906 		dmc->required_version = DG2_DMC_VERSION_REQUIRED;
907 		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
908 	} else if (IS_ALDERLAKE_P(dev_priv)) {
909 		dmc->fw_path = ADLP_DMC_PATH;
910 		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
911 		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
912 	} else if (IS_ALDERLAKE_S(dev_priv)) {
913 		dmc->fw_path = ADLS_DMC_PATH;
914 		dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
915 		dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
916 	} else if (IS_DG1(dev_priv)) {
917 		dmc->fw_path = DG1_DMC_PATH;
918 		dmc->required_version = DG1_DMC_VERSION_REQUIRED;
919 		dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
920 	} else if (IS_ROCKETLAKE(dev_priv)) {
921 		dmc->fw_path = RKL_DMC_PATH;
922 		dmc->required_version = RKL_DMC_VERSION_REQUIRED;
923 		dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
924 	} else if (IS_TIGERLAKE(dev_priv)) {
925 		dmc->fw_path = TGL_DMC_PATH;
926 		dmc->required_version = TGL_DMC_VERSION_REQUIRED;
927 		dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
928 	} else if (DISPLAY_VER(dev_priv) == 11) {
929 		dmc->fw_path = ICL_DMC_PATH;
930 		dmc->required_version = ICL_DMC_VERSION_REQUIRED;
931 		dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;
932 	} else if (IS_GEMINILAKE(dev_priv)) {
933 		dmc->fw_path = GLK_DMC_PATH;
934 		dmc->required_version = GLK_DMC_VERSION_REQUIRED;
935 		dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE;
936 	} else if (IS_KABYLAKE(dev_priv) ||
937 		   IS_COFFEELAKE(dev_priv) ||
938 		   IS_COMETLAKE(dev_priv)) {
939 		dmc->fw_path = KBL_DMC_PATH;
940 		dmc->required_version = KBL_DMC_VERSION_REQUIRED;
941 		dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE;
942 	} else if (IS_SKYLAKE(dev_priv)) {
943 		dmc->fw_path = SKL_DMC_PATH;
944 		dmc->required_version = SKL_DMC_VERSION_REQUIRED;
945 		dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE;
946 	} else if (IS_BROXTON(dev_priv)) {
947 		dmc->fw_path = BXT_DMC_PATH;
948 		dmc->required_version = BXT_DMC_VERSION_REQUIRED;
949 		dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE;
950 	}
951 
952 	if (dev_priv->params.dmc_firmware_path) {
953 		if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
954 			dmc->fw_path = NULL;
955 			drm_info(&dev_priv->drm,
956 				 "Disabling DMC firmware and runtime PM\n");
957 			return;
958 		}
959 
960 		dmc->fw_path = dev_priv->params.dmc_firmware_path;
961 		/* Bypass version check for firmware override. */
962 		dmc->required_version = 0;
963 	}
964 
965 	if (!dmc->fw_path) {
966 		drm_dbg_kms(&dev_priv->drm,
967 			    "No known DMC firmware for platform, disabling runtime PM\n");
968 		return;
969 	}
970 
971 	drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
972 	schedule_work(&dev_priv->display.dmc.work);
973 }
974 
975 /**
976  * intel_dmc_ucode_suspend() - prepare DMC firmware before system suspend
977  * @dev_priv: i915 drm device
978  *
979  * Prepare the DMC firmware before entering system suspend. This includes
980  * flushing pending work items and releasing any resources acquired during
981  * init.
982  */
983 void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv)
984 {
985 	if (!HAS_DMC(dev_priv))
986 		return;
987 
988 	flush_work(&dev_priv->display.dmc.work);
989 
990 	/* Drop the reference held in case DMC isn't loaded. */
991 	if (!intel_dmc_has_payload(dev_priv))
992 		intel_dmc_runtime_pm_put(dev_priv);
993 }
994 
995 /**
996  * intel_dmc_ucode_resume() - init DMC firmware during system resume
997  * @dev_priv: i915 drm device
998  *
999  * Reinitialize the DMC firmware during system resume, reacquiring any
1000  * resources released in intel_dmc_ucode_suspend().
1001  */
1002 void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv)
1003 {
1004 	if (!HAS_DMC(dev_priv))
1005 		return;
1006 
1007 	/*
1008 	 * Reacquire the reference to keep RPM disabled in case DMC isn't
1009 	 * loaded.
1010 	 */
1011 	if (!intel_dmc_has_payload(dev_priv))
1012 		intel_dmc_runtime_pm_get(dev_priv);
1013 }
1014 
1015 /**
1016  * intel_dmc_ucode_fini() - unload the DMC firmware.
1017  * @dev_priv: i915 drm device.
1018  *
1019  * Firmmware unloading includes freeing the internal memory and reset the
1020  * firmware loading status.
1021  */
1022 void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
1023 {
1024 	int id;
1025 
1026 	if (!HAS_DMC(dev_priv))
1027 		return;
1028 
1029 	intel_dmc_ucode_suspend(dev_priv);
1030 	drm_WARN_ON(&dev_priv->drm, dev_priv->display.dmc.wakeref);
1031 
1032 	for (id = 0; id < DMC_FW_MAX; id++)
1033 		kfree(dev_priv->display.dmc.dmc_info[id].payload);
1034 }
1035 
1036 void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m,
1037 				 struct drm_i915_private *i915)
1038 {
1039 	struct intel_dmc *dmc = &i915->display.dmc;
1040 
1041 	if (!HAS_DMC(i915))
1042 		return;
1043 
1044 	i915_error_printf(m, "DMC loaded: %s\n",
1045 			  str_yes_no(intel_dmc_has_payload(i915)));
1046 	i915_error_printf(m, "DMC fw version: %d.%d\n",
1047 			  DMC_VERSION_MAJOR(dmc->version),
1048 			  DMC_VERSION_MINOR(dmc->version));
1049 }
1050 
1051 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
1052 {
1053 	struct drm_i915_private *i915 = m->private;
1054 	intel_wakeref_t wakeref;
1055 	struct intel_dmc *dmc;
1056 	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
1057 
1058 	if (!HAS_DMC(i915))
1059 		return -ENODEV;
1060 
1061 	dmc = &i915->display.dmc;
1062 
1063 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1064 
1065 	seq_printf(m, "fw loaded: %s\n",
1066 		   str_yes_no(intel_dmc_has_payload(i915)));
1067 	seq_printf(m, "path: %s\n", dmc->fw_path);
1068 	seq_printf(m, "Pipe A fw support: %s\n",
1069 		   str_yes_no(GRAPHICS_VER(i915) >= 12));
1070 	seq_printf(m, "Pipe A fw loaded: %s\n",
1071 		   str_yes_no(dmc->dmc_info[DMC_FW_PIPEA].payload));
1072 	seq_printf(m, "Pipe B fw support: %s\n",
1073 		   str_yes_no(IS_ALDERLAKE_P(i915)));
1074 	seq_printf(m, "Pipe B fw loaded: %s\n",
1075 		   str_yes_no(dmc->dmc_info[DMC_FW_PIPEB].payload));
1076 
1077 	if (!intel_dmc_has_payload(i915))
1078 		goto out;
1079 
1080 	seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
1081 		   DMC_VERSION_MINOR(dmc->version));
1082 
1083 	if (DISPLAY_VER(i915) >= 12) {
1084 		if (IS_DGFX(i915)) {
1085 			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
1086 		} else {
1087 			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
1088 			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
1089 		}
1090 
1091 		/*
1092 		 * NOTE: DMC_DEBUG3 is a general purpose reg.
1093 		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
1094 		 * reg for DC3CO debugging and validation,
1095 		 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
1096 		 */
1097 		seq_printf(m, "DC3CO count: %d\n",
1098 			   intel_de_read(i915, IS_DGFX(i915) ?
1099 					 DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3));
1100 	} else {
1101 		dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT :
1102 			SKL_DMC_DC3_DC5_COUNT;
1103 		if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915))
1104 			dc6_reg = SKL_DMC_DC5_DC6_COUNT;
1105 	}
1106 
1107 	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg));
1108 	if (i915_mmio_reg_valid(dc6_reg))
1109 		seq_printf(m, "DC5 -> DC6 count: %d\n",
1110 			   intel_de_read(i915, dc6_reg));
1111 
1112 out:
1113 	seq_printf(m, "program base: 0x%08x\n",
1114 		   intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
1115 	seq_printf(m, "ssp base: 0x%08x\n",
1116 		   intel_de_read(i915, DMC_SSP_BASE));
1117 	seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL));
1118 
1119 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1120 
1121 	return 0;
1122 }
1123 
1124 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status);
1125 
1126 void intel_dmc_debugfs_register(struct drm_i915_private *i915)
1127 {
1128 	struct drm_minor *minor = i915->drm.primary;
1129 
1130 	debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
1131 			    i915, &intel_dmc_debugfs_status_fops);
1132 }
1133