1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/firmware.h> 26 27 #include "i915_drv.h" 28 #include "i915_reg.h" 29 #include "intel_de.h" 30 #include "intel_dmc.h" 31 #include "intel_dmc_regs.h" 32 33 /** 34 * DOC: DMC Firmware Support 35 * 36 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 37 * engine to save and restore the state of display engine when it enter into 38 * low-power state and comes back to normal. 39 */ 40 41 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 42 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 43 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 44 45 #define DMC_PATH(platform) \ 46 "i915/" __stringify(platform) "_dmc.bin" 47 48 /* 49 * New DMC additions should not use this. This is used solely to remain 50 * compatible with systems that have not yet updated DMC blobs to use 51 * unversioned file names. 52 */ 53 #define DMC_LEGACY_PATH(platform, major, minor) \ 54 "i915/" \ 55 __stringify(platform) "_dmc_ver" \ 56 __stringify(major) "_" \ 57 __stringify(minor) ".bin" 58 59 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 60 61 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 62 63 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 64 MODULE_FIRMWARE(DG2_DMC_PATH); 65 66 #define ADLP_DMC_PATH DMC_PATH(adlp) 67 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 68 MODULE_FIRMWARE(ADLP_DMC_PATH); 69 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 70 71 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 72 MODULE_FIRMWARE(ADLS_DMC_PATH); 73 74 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 75 MODULE_FIRMWARE(DG1_DMC_PATH); 76 77 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 78 MODULE_FIRMWARE(RKL_DMC_PATH); 79 80 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 81 MODULE_FIRMWARE(TGL_DMC_PATH); 82 83 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 84 #define ICL_DMC_MAX_FW_SIZE 0x6000 85 MODULE_FIRMWARE(ICL_DMC_PATH); 86 87 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 88 #define GLK_DMC_MAX_FW_SIZE 0x4000 89 MODULE_FIRMWARE(GLK_DMC_PATH); 90 91 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 92 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 93 MODULE_FIRMWARE(KBL_DMC_PATH); 94 95 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 96 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 97 MODULE_FIRMWARE(SKL_DMC_PATH); 98 99 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 100 #define BXT_DMC_MAX_FW_SIZE 0x3000 101 MODULE_FIRMWARE(BXT_DMC_PATH); 102 103 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 104 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 105 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 106 #define DMC_V1_MAX_MMIO_COUNT 8 107 #define DMC_V3_MAX_MMIO_COUNT 20 108 #define DMC_V1_MMIO_START_RANGE 0x80000 109 110 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 111 112 struct intel_css_header { 113 /* 0x09 for DMC */ 114 u32 module_type; 115 116 /* Includes the DMC specific header in dwords */ 117 u32 header_len; 118 119 /* always value would be 0x10000 */ 120 u32 header_ver; 121 122 /* Not used */ 123 u32 module_id; 124 125 /* Not used */ 126 u32 module_vendor; 127 128 /* in YYYYMMDD format */ 129 u32 date; 130 131 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 132 u32 size; 133 134 /* Not used */ 135 u32 key_size; 136 137 /* Not used */ 138 u32 modulus_size; 139 140 /* Not used */ 141 u32 exponent_size; 142 143 /* Not used */ 144 u32 reserved1[12]; 145 146 /* Major Minor */ 147 u32 version; 148 149 /* Not used */ 150 u32 reserved2[8]; 151 152 /* Not used */ 153 u32 kernel_header_info; 154 } __packed; 155 156 struct intel_fw_info { 157 u8 reserved1; 158 159 /* reserved on package_header version 1, must be 0 on version 2 */ 160 u8 dmc_id; 161 162 /* Stepping (A, B, C, ..., *). * is a wildcard */ 163 char stepping; 164 165 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 166 char substepping; 167 168 u32 offset; 169 u32 reserved2; 170 } __packed; 171 172 struct intel_package_header { 173 /* DMC container header length in dwords */ 174 u8 header_len; 175 176 /* 0x01, 0x02 */ 177 u8 header_ver; 178 179 u8 reserved[10]; 180 181 /* Number of valid entries in the FWInfo array below */ 182 u32 num_entries; 183 } __packed; 184 185 struct intel_dmc_header_base { 186 /* always value would be 0x40403E3E */ 187 u32 signature; 188 189 /* DMC binary header length */ 190 u8 header_len; 191 192 /* 0x01 */ 193 u8 header_ver; 194 195 /* Reserved */ 196 u16 dmcc_ver; 197 198 /* Major, Minor */ 199 u32 project; 200 201 /* Firmware program size (excluding header) in dwords */ 202 u32 fw_size; 203 204 /* Major Minor version */ 205 u32 fw_version; 206 } __packed; 207 208 struct intel_dmc_header_v1 { 209 struct intel_dmc_header_base base; 210 211 /* Number of valid MMIO cycles present. */ 212 u32 mmio_count; 213 214 /* MMIO address */ 215 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 216 217 /* MMIO data */ 218 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 219 220 /* FW filename */ 221 char dfile[32]; 222 223 u32 reserved1[2]; 224 } __packed; 225 226 struct intel_dmc_header_v3 { 227 struct intel_dmc_header_base base; 228 229 /* DMC RAM start MMIO address */ 230 u32 start_mmioaddr; 231 232 u32 reserved[9]; 233 234 /* FW filename */ 235 char dfile[32]; 236 237 /* Number of valid MMIO cycles present. */ 238 u32 mmio_count; 239 240 /* MMIO address */ 241 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 242 243 /* MMIO data */ 244 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 245 } __packed; 246 247 struct stepping_info { 248 char stepping; 249 char substepping; 250 }; 251 252 static bool has_dmc_id_fw(struct drm_i915_private *i915, int dmc_id) 253 { 254 return i915->display.dmc.dmc_info[dmc_id].payload; 255 } 256 257 bool intel_dmc_has_payload(struct drm_i915_private *i915) 258 { 259 return has_dmc_id_fw(i915, DMC_FW_MAIN); 260 } 261 262 static const struct stepping_info * 263 intel_get_stepping_info(struct drm_i915_private *i915, 264 struct stepping_info *si) 265 { 266 const char *step_name = intel_step_name(RUNTIME_INFO(i915)->step.display_step); 267 268 si->stepping = step_name[0]; 269 si->substepping = step_name[1]; 270 return si; 271 } 272 273 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) 274 { 275 /* The below bit doesn't need to be cleared ever afterwards */ 276 intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0, 277 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 278 intel_de_posting_read(dev_priv, DC_STATE_DEBUG); 279 } 280 281 static void disable_event_handler(struct drm_i915_private *i915, 282 i915_reg_t ctl_reg, i915_reg_t htp_reg) 283 { 284 intel_de_write(i915, ctl_reg, 285 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 286 DMC_EVT_CTL_TYPE_EDGE_0_1) | 287 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 288 DMC_EVT_CTL_EVENT_ID_FALSE)); 289 intel_de_write(i915, htp_reg, 0); 290 } 291 292 static void 293 disable_flip_queue_event(struct drm_i915_private *i915, 294 i915_reg_t ctl_reg, i915_reg_t htp_reg) 295 { 296 u32 event_ctl; 297 u32 event_htp; 298 299 event_ctl = intel_de_read(i915, ctl_reg); 300 event_htp = intel_de_read(i915, htp_reg); 301 if (event_ctl != (DMC_EVT_CTL_ENABLE | 302 DMC_EVT_CTL_RECURRING | 303 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 304 DMC_EVT_CTL_TYPE_EDGE_0_1) | 305 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 306 DMC_EVT_CTL_EVENT_ID_CLK_MSEC)) || 307 !event_htp) { 308 drm_dbg_kms(&i915->drm, 309 "Unexpected DMC event configuration (control %08x htp %08x)\n", 310 event_ctl, event_htp); 311 return; 312 } 313 314 disable_event_handler(i915, ctl_reg, htp_reg); 315 } 316 317 static bool 318 get_flip_queue_event_regs(struct drm_i915_private *i915, int dmc_id, 319 i915_reg_t *ctl_reg, i915_reg_t *htp_reg) 320 { 321 switch (dmc_id) { 322 case DMC_FW_MAIN: 323 if (DISPLAY_VER(i915) == 12) { 324 *ctl_reg = DMC_EVT_CTL(i915, dmc_id, 3); 325 *htp_reg = DMC_EVT_HTP(i915, dmc_id, 3); 326 327 return true; 328 } 329 break; 330 case DMC_FW_PIPEA ... DMC_FW_PIPED: 331 if (IS_DG2(i915)) { 332 *ctl_reg = DMC_EVT_CTL(i915, dmc_id, 2); 333 *htp_reg = DMC_EVT_HTP(i915, dmc_id, 2); 334 335 return true; 336 } 337 break; 338 } 339 340 return false; 341 } 342 343 static void 344 disable_all_flip_queue_events(struct drm_i915_private *i915) 345 { 346 int dmc_id; 347 348 /* TODO: check if the following applies to all D13+ platforms. */ 349 if (!IS_DG2(i915) && !IS_TIGERLAKE(i915)) 350 return; 351 352 for (dmc_id = 0; dmc_id < DMC_FW_MAX; dmc_id++) { 353 i915_reg_t ctl_reg; 354 i915_reg_t htp_reg; 355 356 if (!has_dmc_id_fw(i915, dmc_id)) 357 continue; 358 359 if (!get_flip_queue_event_regs(i915, dmc_id, &ctl_reg, &htp_reg)) 360 continue; 361 362 disable_flip_queue_event(i915, ctl_reg, htp_reg); 363 } 364 } 365 366 static void disable_all_event_handlers(struct drm_i915_private *i915) 367 { 368 int id; 369 370 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 371 if (DISPLAY_VER(i915) < 12) 372 return; 373 374 for (id = DMC_FW_MAIN; id < DMC_FW_MAX; id++) { 375 int handler; 376 377 if (!has_dmc_id_fw(i915, id)) 378 continue; 379 380 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 381 disable_event_handler(i915, 382 DMC_EVT_CTL(i915, id, handler), 383 DMC_EVT_HTP(i915, id, handler)); 384 } 385 } 386 387 static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) 388 { 389 enum pipe pipe; 390 391 /* 392 * Wa_16015201720:adl-p,dg2 393 * The WA requires clock gating to be disabled all the time 394 * for pipe A and B. 395 * For pipe C and D clock gating needs to be disabled only 396 * during initializing the firmware. 397 */ 398 if (enable) 399 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 400 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), 401 0, PIPEDMC_GATING_DIS); 402 else 403 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 404 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), 405 PIPEDMC_GATING_DIS, 0); 406 } 407 408 static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915) 409 { 410 /* 411 * Wa_16015201720 412 * The WA requires clock gating to be disabled all the time 413 * for pipe A and B. 414 */ 415 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, 416 MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B); 417 } 418 419 static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) 420 { 421 if (DISPLAY_VER(i915) >= 14 && enable) 422 mtl_pipedmc_clock_gating_wa(i915); 423 else if (DISPLAY_VER(i915) == 13) 424 adlp_pipedmc_clock_gating_wa(i915, enable); 425 } 426 427 void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe) 428 { 429 if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe))) 430 return; 431 432 if (DISPLAY_VER(i915) >= 14) 433 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 434 else 435 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 436 } 437 438 void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe) 439 { 440 if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe))) 441 return; 442 443 if (DISPLAY_VER(i915) >= 14) 444 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 445 else 446 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 447 } 448 449 /** 450 * intel_dmc_load_program() - write the firmware from memory to register. 451 * @dev_priv: i915 drm device. 452 * 453 * DMC firmware is read from a .bin file and kept in internal memory one time. 454 * Everytime display comes back from low power state this function is called to 455 * copy the firmware from internal memory to registers. 456 */ 457 void intel_dmc_load_program(struct drm_i915_private *dev_priv) 458 { 459 struct intel_dmc *dmc = &dev_priv->display.dmc; 460 u32 id, i; 461 462 if (!intel_dmc_has_payload(dev_priv)) 463 return; 464 465 pipedmc_clock_gating_wa(dev_priv, true); 466 467 disable_all_event_handlers(dev_priv); 468 469 assert_rpm_wakelock_held(&dev_priv->runtime_pm); 470 471 preempt_disable(); 472 473 for (id = 0; id < DMC_FW_MAX; id++) { 474 for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) { 475 intel_de_write_fw(dev_priv, 476 DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i), 477 dmc->dmc_info[id].payload[i]); 478 } 479 } 480 481 preempt_enable(); 482 483 for (id = 0; id < DMC_FW_MAX; id++) { 484 for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) { 485 intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i], 486 dmc->dmc_info[id].mmiodata[i]); 487 } 488 } 489 490 dev_priv->display.dmc.dc_state = 0; 491 492 gen9_set_dc_state_debugmask(dev_priv); 493 494 /* 495 * Flip queue events need to be disabled before enabling DC5/6. 496 * i915 doesn't use the flip queue feature, so disable it already 497 * here. 498 */ 499 disable_all_flip_queue_events(dev_priv); 500 501 pipedmc_clock_gating_wa(dev_priv, false); 502 } 503 504 /** 505 * intel_dmc_disable_program() - disable the firmware 506 * @i915: i915 drm device 507 * 508 * Disable all event handlers in the firmware, making sure the firmware is 509 * inactive after the display is uninitialized. 510 */ 511 void intel_dmc_disable_program(struct drm_i915_private *i915) 512 { 513 if (!intel_dmc_has_payload(i915)) 514 return; 515 516 pipedmc_clock_gating_wa(i915, true); 517 disable_all_event_handlers(i915); 518 pipedmc_clock_gating_wa(i915, false); 519 } 520 521 void assert_dmc_loaded(struct drm_i915_private *i915) 522 { 523 drm_WARN_ONCE(&i915->drm, 524 !intel_de_read(i915, DMC_PROGRAM(i915->display.dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), 525 "DMC program storage start is NULL\n"); 526 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE), 527 "DMC SSP Base Not fine\n"); 528 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL), 529 "DMC HTP Not fine\n"); 530 } 531 532 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 533 const struct stepping_info *si) 534 { 535 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 536 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 537 /* 538 * If we don't find a more specific one from above two checks, we 539 * then check for the generic one to be sure to work even with 540 * "broken firmware" 541 */ 542 (si->stepping == '*' && si->substepping == fw_info->substepping) || 543 (fw_info->stepping == '*' && fw_info->substepping == '*')) 544 return true; 545 546 return false; 547 } 548 549 /* 550 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 551 * already sanitized. 552 */ 553 static void dmc_set_fw_offset(struct intel_dmc *dmc, 554 const struct intel_fw_info *fw_info, 555 unsigned int num_entries, 556 const struct stepping_info *si, 557 u8 package_ver) 558 { 559 unsigned int i, id; 560 561 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc); 562 563 for (i = 0; i < num_entries; i++) { 564 id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 565 566 if (id >= DMC_FW_MAX) { 567 drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", id); 568 continue; 569 } 570 571 /* More specific versions come first, so we don't even have to 572 * check for the stepping since we already found a previous FW 573 * for this id. 574 */ 575 if (dmc->dmc_info[id].present) 576 continue; 577 578 if (fw_info_matches_stepping(&fw_info[i], si)) { 579 dmc->dmc_info[id].present = true; 580 dmc->dmc_info[id].dmc_offset = fw_info[i].offset; 581 } 582 } 583 } 584 585 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 586 const u32 *mmioaddr, u32 mmio_count, 587 int header_ver, u8 dmc_id) 588 { 589 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc); 590 u32 start_range, end_range; 591 int i; 592 593 if (dmc_id >= DMC_FW_MAX) { 594 drm_warn(&i915->drm, "Unsupported firmware id %u\n", dmc_id); 595 return false; 596 } 597 598 if (header_ver == 1) { 599 start_range = DMC_MMIO_START_RANGE; 600 end_range = DMC_MMIO_END_RANGE; 601 } else if (dmc_id == DMC_FW_MAIN) { 602 start_range = TGL_MAIN_MMIO_START; 603 end_range = TGL_MAIN_MMIO_END; 604 } else if (DISPLAY_VER(i915) >= 13) { 605 start_range = ADLP_PIPE_MMIO_START; 606 end_range = ADLP_PIPE_MMIO_END; 607 } else if (DISPLAY_VER(i915) >= 12) { 608 start_range = TGL_PIPE_MMIO_START(dmc_id); 609 end_range = TGL_PIPE_MMIO_END(dmc_id); 610 } else { 611 drm_warn(&i915->drm, "Unknown mmio range for sanity check"); 612 return false; 613 } 614 615 for (i = 0; i < mmio_count; i++) { 616 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 617 return false; 618 } 619 620 return true; 621 } 622 623 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 624 const struct intel_dmc_header_base *dmc_header, 625 size_t rem_size, u8 dmc_id) 626 { 627 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc); 628 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 629 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 630 const u32 *mmioaddr, *mmiodata; 631 u32 mmio_count, mmio_count_max, start_mmioaddr; 632 u8 *payload; 633 634 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 635 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 636 637 /* 638 * Check if we can access common fields, we will checkc again below 639 * after we have read the version 640 */ 641 if (rem_size < sizeof(struct intel_dmc_header_base)) 642 goto error_truncated; 643 644 /* Cope with small differences between v1 and v3 */ 645 if (dmc_header->header_ver == 3) { 646 const struct intel_dmc_header_v3 *v3 = 647 (const struct intel_dmc_header_v3 *)dmc_header; 648 649 if (rem_size < sizeof(struct intel_dmc_header_v3)) 650 goto error_truncated; 651 652 mmioaddr = v3->mmioaddr; 653 mmiodata = v3->mmiodata; 654 mmio_count = v3->mmio_count; 655 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 656 /* header_len is in dwords */ 657 header_len_bytes = dmc_header->header_len * 4; 658 start_mmioaddr = v3->start_mmioaddr; 659 dmc_header_size = sizeof(*v3); 660 } else if (dmc_header->header_ver == 1) { 661 const struct intel_dmc_header_v1 *v1 = 662 (const struct intel_dmc_header_v1 *)dmc_header; 663 664 if (rem_size < sizeof(struct intel_dmc_header_v1)) 665 goto error_truncated; 666 667 mmioaddr = v1->mmioaddr; 668 mmiodata = v1->mmiodata; 669 mmio_count = v1->mmio_count; 670 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 671 header_len_bytes = dmc_header->header_len; 672 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 673 dmc_header_size = sizeof(*v1); 674 } else { 675 drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", 676 dmc_header->header_ver); 677 return 0; 678 } 679 680 if (header_len_bytes != dmc_header_size) { 681 drm_err(&i915->drm, "DMC firmware has wrong dmc header length " 682 "(%u bytes)\n", header_len_bytes); 683 return 0; 684 } 685 686 /* Cache the dmc header info. */ 687 if (mmio_count > mmio_count_max) { 688 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 689 return 0; 690 } 691 692 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 693 dmc_header->header_ver, dmc_id)) { 694 drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n"); 695 return 0; 696 } 697 698 for (i = 0; i < mmio_count; i++) { 699 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 700 dmc_info->mmiodata[i] = mmiodata[i]; 701 } 702 dmc_info->mmio_count = mmio_count; 703 dmc_info->start_mmioaddr = start_mmioaddr; 704 705 rem_size -= header_len_bytes; 706 707 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 708 payload_size = dmc_header->fw_size * 4; 709 if (rem_size < payload_size) 710 goto error_truncated; 711 712 if (payload_size > dmc->max_fw_size) { 713 drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); 714 return 0; 715 } 716 dmc_info->dmc_fw_size = dmc_header->fw_size; 717 718 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 719 if (!dmc_info->payload) 720 return 0; 721 722 payload = (u8 *)(dmc_header) + header_len_bytes; 723 memcpy(dmc_info->payload, payload, payload_size); 724 725 return header_len_bytes + payload_size; 726 727 error_truncated: 728 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 729 return 0; 730 } 731 732 static u32 733 parse_dmc_fw_package(struct intel_dmc *dmc, 734 const struct intel_package_header *package_header, 735 const struct stepping_info *si, 736 size_t rem_size) 737 { 738 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc); 739 u32 package_size = sizeof(struct intel_package_header); 740 u32 num_entries, max_entries; 741 const struct intel_fw_info *fw_info; 742 743 if (rem_size < package_size) 744 goto error_truncated; 745 746 if (package_header->header_ver == 1) { 747 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 748 } else if (package_header->header_ver == 2) { 749 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 750 } else { 751 drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", 752 package_header->header_ver); 753 return 0; 754 } 755 756 /* 757 * We should always have space for max_entries, 758 * even if not all are used 759 */ 760 package_size += max_entries * sizeof(struct intel_fw_info); 761 if (rem_size < package_size) 762 goto error_truncated; 763 764 if (package_header->header_len * 4 != package_size) { 765 drm_err(&i915->drm, "DMC firmware has wrong package header length " 766 "(%u bytes)\n", package_size); 767 return 0; 768 } 769 770 num_entries = package_header->num_entries; 771 if (WARN_ON(package_header->num_entries > max_entries)) 772 num_entries = max_entries; 773 774 fw_info = (const struct intel_fw_info *) 775 ((u8 *)package_header + sizeof(*package_header)); 776 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 777 package_header->header_ver); 778 779 /* dmc_offset is in dwords */ 780 return package_size; 781 782 error_truncated: 783 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 784 return 0; 785 } 786 787 /* Return number of bytes parsed or 0 on error */ 788 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 789 struct intel_css_header *css_header, 790 size_t rem_size) 791 { 792 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc); 793 794 if (rem_size < sizeof(struct intel_css_header)) { 795 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 796 return 0; 797 } 798 799 if (sizeof(struct intel_css_header) != 800 (css_header->header_len * 4)) { 801 drm_err(&i915->drm, "DMC firmware has wrong CSS header length " 802 "(%u bytes)\n", 803 (css_header->header_len * 4)); 804 return 0; 805 } 806 807 dmc->version = css_header->version; 808 809 return sizeof(struct intel_css_header); 810 } 811 812 static void parse_dmc_fw(struct drm_i915_private *dev_priv, 813 const struct firmware *fw) 814 { 815 struct intel_css_header *css_header; 816 struct intel_package_header *package_header; 817 struct intel_dmc_header_base *dmc_header; 818 struct intel_dmc *dmc = &dev_priv->display.dmc; 819 struct stepping_info display_info = { '*', '*'}; 820 const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info); 821 u32 readcount = 0; 822 u32 r, offset; 823 int id; 824 825 if (!fw) 826 return; 827 828 /* Extract CSS Header information */ 829 css_header = (struct intel_css_header *)fw->data; 830 r = parse_dmc_fw_css(dmc, css_header, fw->size); 831 if (!r) 832 return; 833 834 readcount += r; 835 836 /* Extract Package Header information */ 837 package_header = (struct intel_package_header *)&fw->data[readcount]; 838 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 839 if (!r) 840 return; 841 842 readcount += r; 843 844 for (id = 0; id < DMC_FW_MAX; id++) { 845 if (!dev_priv->display.dmc.dmc_info[id].present) 846 continue; 847 848 offset = readcount + dmc->dmc_info[id].dmc_offset * 4; 849 if (offset > fw->size) { 850 drm_err(&dev_priv->drm, "Reading beyond the fw_size\n"); 851 continue; 852 } 853 854 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 855 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id); 856 } 857 } 858 859 static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv) 860 { 861 drm_WARN_ON(&dev_priv->drm, dev_priv->display.dmc.wakeref); 862 dev_priv->display.dmc.wakeref = 863 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 864 } 865 866 static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv) 867 { 868 intel_wakeref_t wakeref __maybe_unused = 869 fetch_and_zero(&dev_priv->display.dmc.wakeref); 870 871 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 872 } 873 874 static const char *dmc_fallback_path(struct drm_i915_private *i915) 875 { 876 if (IS_ALDERLAKE_P(i915)) 877 return ADLP_DMC_FALLBACK_PATH; 878 879 return NULL; 880 } 881 882 static void dmc_load_work_fn(struct work_struct *work) 883 { 884 struct drm_i915_private *dev_priv; 885 struct intel_dmc *dmc; 886 const struct firmware *fw = NULL; 887 const char *fallback_path; 888 int err; 889 890 dev_priv = container_of(work, typeof(*dev_priv), display.dmc.work); 891 dmc = &dev_priv->display.dmc; 892 893 err = request_firmware(&fw, dev_priv->display.dmc.fw_path, dev_priv->drm.dev); 894 895 if (err == -ENOENT && !dev_priv->params.dmc_firmware_path) { 896 fallback_path = dmc_fallback_path(dev_priv); 897 if (fallback_path) { 898 drm_dbg_kms(&dev_priv->drm, 899 "%s not found, falling back to %s\n", 900 dmc->fw_path, 901 fallback_path); 902 err = request_firmware(&fw, fallback_path, dev_priv->drm.dev); 903 if (err == 0) 904 dev_priv->display.dmc.fw_path = fallback_path; 905 } 906 } 907 908 parse_dmc_fw(dev_priv, fw); 909 910 if (intel_dmc_has_payload(dev_priv)) { 911 intel_dmc_load_program(dev_priv); 912 intel_dmc_runtime_pm_put(dev_priv); 913 914 drm_info(&dev_priv->drm, 915 "Finished loading DMC firmware %s (v%u.%u)\n", 916 dev_priv->display.dmc.fw_path, DMC_VERSION_MAJOR(dmc->version), 917 DMC_VERSION_MINOR(dmc->version)); 918 } else { 919 drm_notice(&dev_priv->drm, 920 "Failed to load DMC firmware %s." 921 " Disabling runtime power management.\n", 922 dmc->fw_path); 923 drm_notice(&dev_priv->drm, "DMC firmware homepage: %s", 924 INTEL_UC_FIRMWARE_URL); 925 } 926 927 release_firmware(fw); 928 } 929 930 /** 931 * intel_dmc_ucode_init() - initialize the firmware loading. 932 * @dev_priv: i915 drm device. 933 * 934 * This function is called at the time of loading the display driver to read 935 * firmware from a .bin file and copied into a internal memory. 936 */ 937 void intel_dmc_ucode_init(struct drm_i915_private *dev_priv) 938 { 939 struct intel_dmc *dmc = &dev_priv->display.dmc; 940 941 INIT_WORK(&dev_priv->display.dmc.work, dmc_load_work_fn); 942 943 if (!HAS_DMC(dev_priv)) 944 return; 945 946 /* 947 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 948 * runtime-suspend. 949 * 950 * On error, we return with the rpm wakeref held to prevent runtime 951 * suspend as runtime suspend *requires* a working DMC for whatever 952 * reason. 953 */ 954 intel_dmc_runtime_pm_get(dev_priv); 955 956 if (IS_DG2(dev_priv)) { 957 dmc->fw_path = DG2_DMC_PATH; 958 dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 959 } else if (IS_ALDERLAKE_P(dev_priv)) { 960 dmc->fw_path = ADLP_DMC_PATH; 961 dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 962 } else if (IS_ALDERLAKE_S(dev_priv)) { 963 dmc->fw_path = ADLS_DMC_PATH; 964 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 965 } else if (IS_DG1(dev_priv)) { 966 dmc->fw_path = DG1_DMC_PATH; 967 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 968 } else if (IS_ROCKETLAKE(dev_priv)) { 969 dmc->fw_path = RKL_DMC_PATH; 970 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 971 } else if (IS_TIGERLAKE(dev_priv)) { 972 dmc->fw_path = TGL_DMC_PATH; 973 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 974 } else if (DISPLAY_VER(dev_priv) == 11) { 975 dmc->fw_path = ICL_DMC_PATH; 976 dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE; 977 } else if (IS_GEMINILAKE(dev_priv)) { 978 dmc->fw_path = GLK_DMC_PATH; 979 dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE; 980 } else if (IS_KABYLAKE(dev_priv) || 981 IS_COFFEELAKE(dev_priv) || 982 IS_COMETLAKE(dev_priv)) { 983 dmc->fw_path = KBL_DMC_PATH; 984 dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE; 985 } else if (IS_SKYLAKE(dev_priv)) { 986 dmc->fw_path = SKL_DMC_PATH; 987 dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE; 988 } else if (IS_BROXTON(dev_priv)) { 989 dmc->fw_path = BXT_DMC_PATH; 990 dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE; 991 } 992 993 if (dev_priv->params.dmc_firmware_path) { 994 if (strlen(dev_priv->params.dmc_firmware_path) == 0) { 995 dmc->fw_path = NULL; 996 drm_info(&dev_priv->drm, 997 "Disabling DMC firmware and runtime PM\n"); 998 return; 999 } 1000 1001 dmc->fw_path = dev_priv->params.dmc_firmware_path; 1002 } 1003 1004 if (!dmc->fw_path) { 1005 drm_dbg_kms(&dev_priv->drm, 1006 "No known DMC firmware for platform, disabling runtime PM\n"); 1007 return; 1008 } 1009 1010 drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path); 1011 schedule_work(&dev_priv->display.dmc.work); 1012 } 1013 1014 /** 1015 * intel_dmc_ucode_suspend() - prepare DMC firmware before system suspend 1016 * @dev_priv: i915 drm device 1017 * 1018 * Prepare the DMC firmware before entering system suspend. This includes 1019 * flushing pending work items and releasing any resources acquired during 1020 * init. 1021 */ 1022 void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv) 1023 { 1024 if (!HAS_DMC(dev_priv)) 1025 return; 1026 1027 flush_work(&dev_priv->display.dmc.work); 1028 1029 /* Drop the reference held in case DMC isn't loaded. */ 1030 if (!intel_dmc_has_payload(dev_priv)) 1031 intel_dmc_runtime_pm_put(dev_priv); 1032 } 1033 1034 /** 1035 * intel_dmc_ucode_resume() - init DMC firmware during system resume 1036 * @dev_priv: i915 drm device 1037 * 1038 * Reinitialize the DMC firmware during system resume, reacquiring any 1039 * resources released in intel_dmc_ucode_suspend(). 1040 */ 1041 void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv) 1042 { 1043 if (!HAS_DMC(dev_priv)) 1044 return; 1045 1046 /* 1047 * Reacquire the reference to keep RPM disabled in case DMC isn't 1048 * loaded. 1049 */ 1050 if (!intel_dmc_has_payload(dev_priv)) 1051 intel_dmc_runtime_pm_get(dev_priv); 1052 } 1053 1054 /** 1055 * intel_dmc_ucode_fini() - unload the DMC firmware. 1056 * @dev_priv: i915 drm device. 1057 * 1058 * Firmmware unloading includes freeing the internal memory and reset the 1059 * firmware loading status. 1060 */ 1061 void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv) 1062 { 1063 int id; 1064 1065 if (!HAS_DMC(dev_priv)) 1066 return; 1067 1068 intel_dmc_ucode_suspend(dev_priv); 1069 drm_WARN_ON(&dev_priv->drm, dev_priv->display.dmc.wakeref); 1070 1071 for (id = 0; id < DMC_FW_MAX; id++) 1072 kfree(dev_priv->display.dmc.dmc_info[id].payload); 1073 } 1074 1075 void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m, 1076 struct drm_i915_private *i915) 1077 { 1078 struct intel_dmc *dmc = &i915->display.dmc; 1079 1080 if (!HAS_DMC(i915)) 1081 return; 1082 1083 i915_error_printf(m, "DMC loaded: %s\n", 1084 str_yes_no(intel_dmc_has_payload(i915))); 1085 i915_error_printf(m, "DMC fw version: %d.%d\n", 1086 DMC_VERSION_MAJOR(dmc->version), 1087 DMC_VERSION_MINOR(dmc->version)); 1088 } 1089 1090 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1091 { 1092 struct drm_i915_private *i915 = m->private; 1093 intel_wakeref_t wakeref; 1094 struct intel_dmc *dmc; 1095 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1096 1097 if (!HAS_DMC(i915)) 1098 return -ENODEV; 1099 1100 dmc = &i915->display.dmc; 1101 1102 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 1103 1104 seq_printf(m, "fw loaded: %s\n", 1105 str_yes_no(intel_dmc_has_payload(i915))); 1106 seq_printf(m, "path: %s\n", dmc->fw_path); 1107 seq_printf(m, "Pipe A fw needed: %s\n", 1108 str_yes_no(GRAPHICS_VER(i915) >= 12)); 1109 seq_printf(m, "Pipe A fw loaded: %s\n", 1110 str_yes_no(dmc->dmc_info[DMC_FW_PIPEA].payload)); 1111 seq_printf(m, "Pipe B fw needed: %s\n", 1112 str_yes_no(IS_ALDERLAKE_P(i915) || 1113 DISPLAY_VER(i915) >= 14)); 1114 seq_printf(m, "Pipe B fw loaded: %s\n", 1115 str_yes_no(dmc->dmc_info[DMC_FW_PIPEB].payload)); 1116 1117 if (!intel_dmc_has_payload(i915)) 1118 goto out; 1119 1120 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1121 DMC_VERSION_MINOR(dmc->version)); 1122 1123 if (DISPLAY_VER(i915) >= 12) { 1124 i915_reg_t dc3co_reg; 1125 1126 if (IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) { 1127 dc3co_reg = DG1_DMC_DEBUG3; 1128 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1129 } else { 1130 dc3co_reg = TGL_DMC_DEBUG3; 1131 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1132 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1133 } 1134 1135 seq_printf(m, "DC3CO count: %d\n", 1136 intel_de_read(i915, dc3co_reg)); 1137 } else { 1138 dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : 1139 SKL_DMC_DC3_DC5_COUNT; 1140 if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915)) 1141 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1142 } 1143 1144 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg)); 1145 if (i915_mmio_reg_valid(dc6_reg)) 1146 seq_printf(m, "DC5 -> DC6 count: %d\n", 1147 intel_de_read(i915, dc6_reg)); 1148 1149 out: 1150 seq_printf(m, "program base: 0x%08x\n", 1151 intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1152 seq_printf(m, "ssp base: 0x%08x\n", 1153 intel_de_read(i915, DMC_SSP_BASE)); 1154 seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL)); 1155 1156 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1157 1158 return 0; 1159 } 1160 1161 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1162 1163 void intel_dmc_debugfs_register(struct drm_i915_private *i915) 1164 { 1165 struct drm_minor *minor = i915->drm.primary; 1166 1167 debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, 1168 i915, &intel_dmc_debugfs_status_fops); 1169 } 1170