1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/firmware.h> 26 27 #include "i915_drv.h" 28 #include "i915_reg.h" 29 #include "intel_de.h" 30 #include "intel_dmc.h" 31 #include "intel_dmc_regs.h" 32 33 /** 34 * DOC: DMC Firmware Support 35 * 36 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 37 * engine to save and restore the state of display engine when it enter into 38 * low-power state and comes back to normal. 39 */ 40 41 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 42 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 43 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 44 45 #define DMC_PATH(platform, major, minor) \ 46 "i915/" \ 47 __stringify(platform) "_dmc_ver" \ 48 __stringify(major) "_" \ 49 __stringify(minor) ".bin" 50 51 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 52 53 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 54 55 #define DG2_DMC_PATH DMC_PATH(dg2, 2, 06) 56 #define DG2_DMC_VERSION_REQUIRED DMC_VERSION(2, 06) 57 MODULE_FIRMWARE(DG2_DMC_PATH); 58 59 #define ADLP_DMC_PATH DMC_PATH(adlp, 2, 16) 60 #define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 16) 61 MODULE_FIRMWARE(ADLP_DMC_PATH); 62 63 #define ADLS_DMC_PATH DMC_PATH(adls, 2, 01) 64 #define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1) 65 MODULE_FIRMWARE(ADLS_DMC_PATH); 66 67 #define DG1_DMC_PATH DMC_PATH(dg1, 2, 02) 68 #define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) 69 MODULE_FIRMWARE(DG1_DMC_PATH); 70 71 #define RKL_DMC_PATH DMC_PATH(rkl, 2, 03) 72 #define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 3) 73 MODULE_FIRMWARE(RKL_DMC_PATH); 74 75 #define TGL_DMC_PATH DMC_PATH(tgl, 2, 12) 76 #define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 12) 77 MODULE_FIRMWARE(TGL_DMC_PATH); 78 79 #define ICL_DMC_PATH DMC_PATH(icl, 1, 09) 80 #define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9) 81 #define ICL_DMC_MAX_FW_SIZE 0x6000 82 MODULE_FIRMWARE(ICL_DMC_PATH); 83 84 #define GLK_DMC_PATH DMC_PATH(glk, 1, 04) 85 #define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) 86 #define GLK_DMC_MAX_FW_SIZE 0x4000 87 MODULE_FIRMWARE(GLK_DMC_PATH); 88 89 #define KBL_DMC_PATH DMC_PATH(kbl, 1, 04) 90 #define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) 91 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 92 MODULE_FIRMWARE(KBL_DMC_PATH); 93 94 #define SKL_DMC_PATH DMC_PATH(skl, 1, 27) 95 #define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27) 96 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 97 MODULE_FIRMWARE(SKL_DMC_PATH); 98 99 #define BXT_DMC_PATH DMC_PATH(bxt, 1, 07) 100 #define BXT_DMC_VERSION_REQUIRED DMC_VERSION(1, 7) 101 #define BXT_DMC_MAX_FW_SIZE 0x3000 102 MODULE_FIRMWARE(BXT_DMC_PATH); 103 104 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 105 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 106 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 107 #define DMC_V1_MAX_MMIO_COUNT 8 108 #define DMC_V3_MAX_MMIO_COUNT 20 109 #define DMC_V1_MMIO_START_RANGE 0x80000 110 111 struct intel_css_header { 112 /* 0x09 for DMC */ 113 u32 module_type; 114 115 /* Includes the DMC specific header in dwords */ 116 u32 header_len; 117 118 /* always value would be 0x10000 */ 119 u32 header_ver; 120 121 /* Not used */ 122 u32 module_id; 123 124 /* Not used */ 125 u32 module_vendor; 126 127 /* in YYYYMMDD format */ 128 u32 date; 129 130 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 131 u32 size; 132 133 /* Not used */ 134 u32 key_size; 135 136 /* Not used */ 137 u32 modulus_size; 138 139 /* Not used */ 140 u32 exponent_size; 141 142 /* Not used */ 143 u32 reserved1[12]; 144 145 /* Major Minor */ 146 u32 version; 147 148 /* Not used */ 149 u32 reserved2[8]; 150 151 /* Not used */ 152 u32 kernel_header_info; 153 } __packed; 154 155 struct intel_fw_info { 156 u8 reserved1; 157 158 /* reserved on package_header version 1, must be 0 on version 2 */ 159 u8 dmc_id; 160 161 /* Stepping (A, B, C, ..., *). * is a wildcard */ 162 char stepping; 163 164 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 165 char substepping; 166 167 u32 offset; 168 u32 reserved2; 169 } __packed; 170 171 struct intel_package_header { 172 /* DMC container header length in dwords */ 173 u8 header_len; 174 175 /* 0x01, 0x02 */ 176 u8 header_ver; 177 178 u8 reserved[10]; 179 180 /* Number of valid entries in the FWInfo array below */ 181 u32 num_entries; 182 } __packed; 183 184 struct intel_dmc_header_base { 185 /* always value would be 0x40403E3E */ 186 u32 signature; 187 188 /* DMC binary header length */ 189 u8 header_len; 190 191 /* 0x01 */ 192 u8 header_ver; 193 194 /* Reserved */ 195 u16 dmcc_ver; 196 197 /* Major, Minor */ 198 u32 project; 199 200 /* Firmware program size (excluding header) in dwords */ 201 u32 fw_size; 202 203 /* Major Minor version */ 204 u32 fw_version; 205 } __packed; 206 207 struct intel_dmc_header_v1 { 208 struct intel_dmc_header_base base; 209 210 /* Number of valid MMIO cycles present. */ 211 u32 mmio_count; 212 213 /* MMIO address */ 214 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 215 216 /* MMIO data */ 217 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 218 219 /* FW filename */ 220 char dfile[32]; 221 222 u32 reserved1[2]; 223 } __packed; 224 225 struct intel_dmc_header_v3 { 226 struct intel_dmc_header_base base; 227 228 /* DMC RAM start MMIO address */ 229 u32 start_mmioaddr; 230 231 u32 reserved[9]; 232 233 /* FW filename */ 234 char dfile[32]; 235 236 /* Number of valid MMIO cycles present. */ 237 u32 mmio_count; 238 239 /* MMIO address */ 240 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 241 242 /* MMIO data */ 243 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 244 } __packed; 245 246 struct stepping_info { 247 char stepping; 248 char substepping; 249 }; 250 251 static bool has_dmc_id_fw(struct drm_i915_private *i915, int dmc_id) 252 { 253 return i915->dmc.dmc_info[dmc_id].payload; 254 } 255 256 bool intel_dmc_has_payload(struct drm_i915_private *i915) 257 { 258 return has_dmc_id_fw(i915, DMC_FW_MAIN); 259 } 260 261 static const struct stepping_info * 262 intel_get_stepping_info(struct drm_i915_private *i915, 263 struct stepping_info *si) 264 { 265 const char *step_name = intel_step_name(RUNTIME_INFO(i915)->step.display_step); 266 267 si->stepping = step_name[0]; 268 si->substepping = step_name[1]; 269 return si; 270 } 271 272 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) 273 { 274 /* The below bit doesn't need to be cleared ever afterwards */ 275 intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0, 276 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 277 intel_de_posting_read(dev_priv, DC_STATE_DEBUG); 278 } 279 280 static void 281 disable_flip_queue_event(struct drm_i915_private *i915, 282 i915_reg_t ctl_reg, i915_reg_t htp_reg) 283 { 284 u32 event_ctl; 285 u32 event_htp; 286 287 event_ctl = intel_de_read(i915, ctl_reg); 288 event_htp = intel_de_read(i915, htp_reg); 289 if (event_ctl != (DMC_EVT_CTL_ENABLE | 290 DMC_EVT_CTL_RECURRING | 291 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 292 DMC_EVT_CTL_TYPE_EDGE_0_1) | 293 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 294 DMC_EVT_CTL_EVENT_ID_CLK_MSEC)) || 295 !event_htp) { 296 drm_dbg_kms(&i915->drm, 297 "Unexpected DMC event configuration (control %08x htp %08x)\n", 298 event_ctl, event_htp); 299 return; 300 } 301 302 intel_de_write(i915, ctl_reg, 303 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 304 DMC_EVT_CTL_TYPE_EDGE_0_1) | 305 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 306 DMC_EVT_CTL_EVENT_ID_FALSE)); 307 intel_de_write(i915, htp_reg, 0); 308 } 309 310 static bool 311 get_flip_queue_event_regs(struct drm_i915_private *i915, int dmc_id, 312 i915_reg_t *ctl_reg, i915_reg_t *htp_reg) 313 { 314 switch (dmc_id) { 315 case DMC_FW_MAIN: 316 if (DISPLAY_VER(i915) == 12) { 317 *ctl_reg = DMC_EVT_CTL(i915, dmc_id, 3); 318 *htp_reg = DMC_EVT_HTP(i915, dmc_id, 3); 319 320 return true; 321 } 322 break; 323 case DMC_FW_PIPEA ... DMC_FW_PIPED: 324 if (IS_DG2(i915)) { 325 *ctl_reg = DMC_EVT_CTL(i915, dmc_id, 2); 326 *htp_reg = DMC_EVT_HTP(i915, dmc_id, 2); 327 328 return true; 329 } 330 break; 331 } 332 333 return false; 334 } 335 336 static void 337 disable_all_flip_queue_events(struct drm_i915_private *i915) 338 { 339 int dmc_id; 340 341 /* TODO: check if the following applies to all D13+ platforms. */ 342 if (!IS_DG2(i915) && !IS_TIGERLAKE(i915)) 343 return; 344 345 for (dmc_id = 0; dmc_id < DMC_FW_MAX; dmc_id++) { 346 i915_reg_t ctl_reg; 347 i915_reg_t htp_reg; 348 349 if (!has_dmc_id_fw(i915, dmc_id)) 350 continue; 351 352 if (!get_flip_queue_event_regs(i915, dmc_id, &ctl_reg, &htp_reg)) 353 continue; 354 355 disable_flip_queue_event(i915, ctl_reg, htp_reg); 356 } 357 } 358 359 /** 360 * intel_dmc_load_program() - write the firmware from memory to register. 361 * @dev_priv: i915 drm device. 362 * 363 * DMC firmware is read from a .bin file and kept in internal memory one time. 364 * Everytime display comes back from low power state this function is called to 365 * copy the firmware from internal memory to registers. 366 */ 367 void intel_dmc_load_program(struct drm_i915_private *dev_priv) 368 { 369 struct intel_dmc *dmc = &dev_priv->dmc; 370 u32 id, i; 371 372 if (!intel_dmc_has_payload(dev_priv)) 373 return; 374 375 assert_rpm_wakelock_held(&dev_priv->runtime_pm); 376 377 preempt_disable(); 378 379 for (id = 0; id < DMC_FW_MAX; id++) { 380 for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) { 381 intel_uncore_write_fw(&dev_priv->uncore, 382 DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i), 383 dmc->dmc_info[id].payload[i]); 384 } 385 } 386 387 preempt_enable(); 388 389 for (id = 0; id < DMC_FW_MAX; id++) { 390 for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) { 391 intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i], 392 dmc->dmc_info[id].mmiodata[i]); 393 } 394 } 395 396 dev_priv->dmc.dc_state = 0; 397 398 gen9_set_dc_state_debugmask(dev_priv); 399 400 /* 401 * Flip queue events need to be disabled before enabling DC5/6. 402 * i915 doesn't use the flip queue feature, so disable it already 403 * here. 404 */ 405 disable_all_flip_queue_events(dev_priv); 406 } 407 408 void assert_dmc_loaded(struct drm_i915_private *i915) 409 { 410 drm_WARN_ONCE(&i915->drm, 411 !intel_de_read(i915, DMC_PROGRAM(i915->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), 412 "DMC program storage start is NULL\n"); 413 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE), 414 "DMC SSP Base Not fine\n"); 415 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL), 416 "DMC HTP Not fine\n"); 417 } 418 419 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 420 const struct stepping_info *si) 421 { 422 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 423 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 424 /* 425 * If we don't find a more specific one from above two checks, we 426 * then check for the generic one to be sure to work even with 427 * "broken firmware" 428 */ 429 (si->stepping == '*' && si->substepping == fw_info->substepping) || 430 (fw_info->stepping == '*' && fw_info->substepping == '*')) 431 return true; 432 433 return false; 434 } 435 436 /* 437 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 438 * already sanitized. 439 */ 440 static void dmc_set_fw_offset(struct intel_dmc *dmc, 441 const struct intel_fw_info *fw_info, 442 unsigned int num_entries, 443 const struct stepping_info *si, 444 u8 package_ver) 445 { 446 unsigned int i, id; 447 448 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 449 450 for (i = 0; i < num_entries; i++) { 451 id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 452 453 if (id >= DMC_FW_MAX) { 454 drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", id); 455 continue; 456 } 457 458 /* More specific versions come first, so we don't even have to 459 * check for the stepping since we already found a previous FW 460 * for this id. 461 */ 462 if (dmc->dmc_info[id].present) 463 continue; 464 465 if (fw_info_matches_stepping(&fw_info[i], si)) { 466 dmc->dmc_info[id].present = true; 467 dmc->dmc_info[id].dmc_offset = fw_info[i].offset; 468 } 469 } 470 } 471 472 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 473 const u32 *mmioaddr, u32 mmio_count, 474 int header_ver, u8 dmc_id) 475 { 476 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 477 u32 start_range, end_range; 478 int i; 479 480 if (dmc_id >= DMC_FW_MAX) { 481 drm_warn(&i915->drm, "Unsupported firmware id %u\n", dmc_id); 482 return false; 483 } 484 485 if (header_ver == 1) { 486 start_range = DMC_MMIO_START_RANGE; 487 end_range = DMC_MMIO_END_RANGE; 488 } else if (dmc_id == DMC_FW_MAIN) { 489 start_range = TGL_MAIN_MMIO_START; 490 end_range = TGL_MAIN_MMIO_END; 491 } else if (DISPLAY_VER(i915) >= 13) { 492 start_range = ADLP_PIPE_MMIO_START; 493 end_range = ADLP_PIPE_MMIO_END; 494 } else if (DISPLAY_VER(i915) >= 12) { 495 start_range = TGL_PIPE_MMIO_START(dmc_id); 496 end_range = TGL_PIPE_MMIO_END(dmc_id); 497 } else { 498 drm_warn(&i915->drm, "Unknown mmio range for sanity check"); 499 return false; 500 } 501 502 for (i = 0; i < mmio_count; i++) { 503 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 504 return false; 505 } 506 507 return true; 508 } 509 510 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 511 const struct intel_dmc_header_base *dmc_header, 512 size_t rem_size, u8 dmc_id) 513 { 514 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 515 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 516 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 517 const u32 *mmioaddr, *mmiodata; 518 u32 mmio_count, mmio_count_max, start_mmioaddr; 519 u8 *payload; 520 521 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 522 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 523 524 /* 525 * Check if we can access common fields, we will checkc again below 526 * after we have read the version 527 */ 528 if (rem_size < sizeof(struct intel_dmc_header_base)) 529 goto error_truncated; 530 531 /* Cope with small differences between v1 and v3 */ 532 if (dmc_header->header_ver == 3) { 533 const struct intel_dmc_header_v3 *v3 = 534 (const struct intel_dmc_header_v3 *)dmc_header; 535 536 if (rem_size < sizeof(struct intel_dmc_header_v3)) 537 goto error_truncated; 538 539 mmioaddr = v3->mmioaddr; 540 mmiodata = v3->mmiodata; 541 mmio_count = v3->mmio_count; 542 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 543 /* header_len is in dwords */ 544 header_len_bytes = dmc_header->header_len * 4; 545 start_mmioaddr = v3->start_mmioaddr; 546 dmc_header_size = sizeof(*v3); 547 } else if (dmc_header->header_ver == 1) { 548 const struct intel_dmc_header_v1 *v1 = 549 (const struct intel_dmc_header_v1 *)dmc_header; 550 551 if (rem_size < sizeof(struct intel_dmc_header_v1)) 552 goto error_truncated; 553 554 mmioaddr = v1->mmioaddr; 555 mmiodata = v1->mmiodata; 556 mmio_count = v1->mmio_count; 557 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 558 header_len_bytes = dmc_header->header_len; 559 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 560 dmc_header_size = sizeof(*v1); 561 } else { 562 drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", 563 dmc_header->header_ver); 564 return 0; 565 } 566 567 if (header_len_bytes != dmc_header_size) { 568 drm_err(&i915->drm, "DMC firmware has wrong dmc header length " 569 "(%u bytes)\n", header_len_bytes); 570 return 0; 571 } 572 573 /* Cache the dmc header info. */ 574 if (mmio_count > mmio_count_max) { 575 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 576 return 0; 577 } 578 579 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 580 dmc_header->header_ver, dmc_id)) { 581 drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n"); 582 return 0; 583 } 584 585 for (i = 0; i < mmio_count; i++) { 586 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 587 dmc_info->mmiodata[i] = mmiodata[i]; 588 } 589 dmc_info->mmio_count = mmio_count; 590 dmc_info->start_mmioaddr = start_mmioaddr; 591 592 rem_size -= header_len_bytes; 593 594 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 595 payload_size = dmc_header->fw_size * 4; 596 if (rem_size < payload_size) 597 goto error_truncated; 598 599 if (payload_size > dmc->max_fw_size) { 600 drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); 601 return 0; 602 } 603 dmc_info->dmc_fw_size = dmc_header->fw_size; 604 605 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 606 if (!dmc_info->payload) 607 return 0; 608 609 payload = (u8 *)(dmc_header) + header_len_bytes; 610 memcpy(dmc_info->payload, payload, payload_size); 611 612 return header_len_bytes + payload_size; 613 614 error_truncated: 615 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 616 return 0; 617 } 618 619 static u32 620 parse_dmc_fw_package(struct intel_dmc *dmc, 621 const struct intel_package_header *package_header, 622 const struct stepping_info *si, 623 size_t rem_size) 624 { 625 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 626 u32 package_size = sizeof(struct intel_package_header); 627 u32 num_entries, max_entries; 628 const struct intel_fw_info *fw_info; 629 630 if (rem_size < package_size) 631 goto error_truncated; 632 633 if (package_header->header_ver == 1) { 634 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 635 } else if (package_header->header_ver == 2) { 636 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 637 } else { 638 drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", 639 package_header->header_ver); 640 return 0; 641 } 642 643 /* 644 * We should always have space for max_entries, 645 * even if not all are used 646 */ 647 package_size += max_entries * sizeof(struct intel_fw_info); 648 if (rem_size < package_size) 649 goto error_truncated; 650 651 if (package_header->header_len * 4 != package_size) { 652 drm_err(&i915->drm, "DMC firmware has wrong package header length " 653 "(%u bytes)\n", package_size); 654 return 0; 655 } 656 657 num_entries = package_header->num_entries; 658 if (WARN_ON(package_header->num_entries > max_entries)) 659 num_entries = max_entries; 660 661 fw_info = (const struct intel_fw_info *) 662 ((u8 *)package_header + sizeof(*package_header)); 663 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 664 package_header->header_ver); 665 666 /* dmc_offset is in dwords */ 667 return package_size; 668 669 error_truncated: 670 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 671 return 0; 672 } 673 674 /* Return number of bytes parsed or 0 on error */ 675 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 676 struct intel_css_header *css_header, 677 size_t rem_size) 678 { 679 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 680 681 if (rem_size < sizeof(struct intel_css_header)) { 682 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 683 return 0; 684 } 685 686 if (sizeof(struct intel_css_header) != 687 (css_header->header_len * 4)) { 688 drm_err(&i915->drm, "DMC firmware has wrong CSS header length " 689 "(%u bytes)\n", 690 (css_header->header_len * 4)); 691 return 0; 692 } 693 694 if (dmc->required_version && 695 css_header->version != dmc->required_version) { 696 drm_info(&i915->drm, "Refusing to load DMC firmware v%u.%u," 697 " please use v%u.%u\n", 698 DMC_VERSION_MAJOR(css_header->version), 699 DMC_VERSION_MINOR(css_header->version), 700 DMC_VERSION_MAJOR(dmc->required_version), 701 DMC_VERSION_MINOR(dmc->required_version)); 702 return 0; 703 } 704 705 dmc->version = css_header->version; 706 707 return sizeof(struct intel_css_header); 708 } 709 710 static void parse_dmc_fw(struct drm_i915_private *dev_priv, 711 const struct firmware *fw) 712 { 713 struct intel_css_header *css_header; 714 struct intel_package_header *package_header; 715 struct intel_dmc_header_base *dmc_header; 716 struct intel_dmc *dmc = &dev_priv->dmc; 717 struct stepping_info display_info = { '*', '*'}; 718 const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info); 719 u32 readcount = 0; 720 u32 r, offset; 721 int id; 722 723 if (!fw) 724 return; 725 726 /* Extract CSS Header information */ 727 css_header = (struct intel_css_header *)fw->data; 728 r = parse_dmc_fw_css(dmc, css_header, fw->size); 729 if (!r) 730 return; 731 732 readcount += r; 733 734 /* Extract Package Header information */ 735 package_header = (struct intel_package_header *)&fw->data[readcount]; 736 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 737 if (!r) 738 return; 739 740 readcount += r; 741 742 for (id = 0; id < DMC_FW_MAX; id++) { 743 if (!dev_priv->dmc.dmc_info[id].present) 744 continue; 745 746 offset = readcount + dmc->dmc_info[id].dmc_offset * 4; 747 if (offset > fw->size) { 748 drm_err(&dev_priv->drm, "Reading beyond the fw_size\n"); 749 continue; 750 } 751 752 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 753 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id); 754 } 755 } 756 757 static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv) 758 { 759 drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); 760 dev_priv->dmc.wakeref = 761 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 762 } 763 764 static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv) 765 { 766 intel_wakeref_t wakeref __maybe_unused = 767 fetch_and_zero(&dev_priv->dmc.wakeref); 768 769 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 770 } 771 772 static void dmc_load_work_fn(struct work_struct *work) 773 { 774 struct drm_i915_private *dev_priv; 775 struct intel_dmc *dmc; 776 const struct firmware *fw = NULL; 777 778 dev_priv = container_of(work, typeof(*dev_priv), dmc.work); 779 dmc = &dev_priv->dmc; 780 781 request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev); 782 parse_dmc_fw(dev_priv, fw); 783 784 if (intel_dmc_has_payload(dev_priv)) { 785 intel_dmc_load_program(dev_priv); 786 intel_dmc_runtime_pm_put(dev_priv); 787 788 drm_info(&dev_priv->drm, 789 "Finished loading DMC firmware %s (v%u.%u)\n", 790 dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version), 791 DMC_VERSION_MINOR(dmc->version)); 792 } else { 793 drm_notice(&dev_priv->drm, 794 "Failed to load DMC firmware %s." 795 " Disabling runtime power management.\n", 796 dmc->fw_path); 797 drm_notice(&dev_priv->drm, "DMC firmware homepage: %s", 798 INTEL_UC_FIRMWARE_URL); 799 } 800 801 release_firmware(fw); 802 } 803 804 /** 805 * intel_dmc_ucode_init() - initialize the firmware loading. 806 * @dev_priv: i915 drm device. 807 * 808 * This function is called at the time of loading the display driver to read 809 * firmware from a .bin file and copied into a internal memory. 810 */ 811 void intel_dmc_ucode_init(struct drm_i915_private *dev_priv) 812 { 813 struct intel_dmc *dmc = &dev_priv->dmc; 814 815 INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn); 816 817 if (!HAS_DMC(dev_priv)) 818 return; 819 820 /* 821 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 822 * runtime-suspend. 823 * 824 * On error, we return with the rpm wakeref held to prevent runtime 825 * suspend as runtime suspend *requires* a working DMC for whatever 826 * reason. 827 */ 828 intel_dmc_runtime_pm_get(dev_priv); 829 830 if (IS_DG2(dev_priv)) { 831 dmc->fw_path = DG2_DMC_PATH; 832 dmc->required_version = DG2_DMC_VERSION_REQUIRED; 833 dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 834 } else if (IS_ALDERLAKE_P(dev_priv)) { 835 dmc->fw_path = ADLP_DMC_PATH; 836 dmc->required_version = ADLP_DMC_VERSION_REQUIRED; 837 dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 838 } else if (IS_ALDERLAKE_S(dev_priv)) { 839 dmc->fw_path = ADLS_DMC_PATH; 840 dmc->required_version = ADLS_DMC_VERSION_REQUIRED; 841 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 842 } else if (IS_DG1(dev_priv)) { 843 dmc->fw_path = DG1_DMC_PATH; 844 dmc->required_version = DG1_DMC_VERSION_REQUIRED; 845 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 846 } else if (IS_ROCKETLAKE(dev_priv)) { 847 dmc->fw_path = RKL_DMC_PATH; 848 dmc->required_version = RKL_DMC_VERSION_REQUIRED; 849 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 850 } else if (IS_TIGERLAKE(dev_priv)) { 851 dmc->fw_path = TGL_DMC_PATH; 852 dmc->required_version = TGL_DMC_VERSION_REQUIRED; 853 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 854 } else if (DISPLAY_VER(dev_priv) == 11) { 855 dmc->fw_path = ICL_DMC_PATH; 856 dmc->required_version = ICL_DMC_VERSION_REQUIRED; 857 dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE; 858 } else if (IS_GEMINILAKE(dev_priv)) { 859 dmc->fw_path = GLK_DMC_PATH; 860 dmc->required_version = GLK_DMC_VERSION_REQUIRED; 861 dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE; 862 } else if (IS_KABYLAKE(dev_priv) || 863 IS_COFFEELAKE(dev_priv) || 864 IS_COMETLAKE(dev_priv)) { 865 dmc->fw_path = KBL_DMC_PATH; 866 dmc->required_version = KBL_DMC_VERSION_REQUIRED; 867 dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE; 868 } else if (IS_SKYLAKE(dev_priv)) { 869 dmc->fw_path = SKL_DMC_PATH; 870 dmc->required_version = SKL_DMC_VERSION_REQUIRED; 871 dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE; 872 } else if (IS_BROXTON(dev_priv)) { 873 dmc->fw_path = BXT_DMC_PATH; 874 dmc->required_version = BXT_DMC_VERSION_REQUIRED; 875 dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE; 876 } 877 878 if (dev_priv->params.dmc_firmware_path) { 879 if (strlen(dev_priv->params.dmc_firmware_path) == 0) { 880 dmc->fw_path = NULL; 881 drm_info(&dev_priv->drm, 882 "Disabling DMC firmware and runtime PM\n"); 883 return; 884 } 885 886 dmc->fw_path = dev_priv->params.dmc_firmware_path; 887 /* Bypass version check for firmware override. */ 888 dmc->required_version = 0; 889 } 890 891 if (!dmc->fw_path) { 892 drm_dbg_kms(&dev_priv->drm, 893 "No known DMC firmware for platform, disabling runtime PM\n"); 894 return; 895 } 896 897 drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path); 898 schedule_work(&dev_priv->dmc.work); 899 } 900 901 /** 902 * intel_dmc_ucode_suspend() - prepare DMC firmware before system suspend 903 * @dev_priv: i915 drm device 904 * 905 * Prepare the DMC firmware before entering system suspend. This includes 906 * flushing pending work items and releasing any resources acquired during 907 * init. 908 */ 909 void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv) 910 { 911 if (!HAS_DMC(dev_priv)) 912 return; 913 914 flush_work(&dev_priv->dmc.work); 915 916 /* Drop the reference held in case DMC isn't loaded. */ 917 if (!intel_dmc_has_payload(dev_priv)) 918 intel_dmc_runtime_pm_put(dev_priv); 919 } 920 921 /** 922 * intel_dmc_ucode_resume() - init DMC firmware during system resume 923 * @dev_priv: i915 drm device 924 * 925 * Reinitialize the DMC firmware during system resume, reacquiring any 926 * resources released in intel_dmc_ucode_suspend(). 927 */ 928 void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv) 929 { 930 if (!HAS_DMC(dev_priv)) 931 return; 932 933 /* 934 * Reacquire the reference to keep RPM disabled in case DMC isn't 935 * loaded. 936 */ 937 if (!intel_dmc_has_payload(dev_priv)) 938 intel_dmc_runtime_pm_get(dev_priv); 939 } 940 941 /** 942 * intel_dmc_ucode_fini() - unload the DMC firmware. 943 * @dev_priv: i915 drm device. 944 * 945 * Firmmware unloading includes freeing the internal memory and reset the 946 * firmware loading status. 947 */ 948 void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv) 949 { 950 int id; 951 952 if (!HAS_DMC(dev_priv)) 953 return; 954 955 intel_dmc_ucode_suspend(dev_priv); 956 drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); 957 958 for (id = 0; id < DMC_FW_MAX; id++) 959 kfree(dev_priv->dmc.dmc_info[id].payload); 960 } 961 962 void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m, 963 struct drm_i915_private *i915) 964 { 965 struct intel_dmc *dmc = &i915->dmc; 966 967 if (!HAS_DMC(i915)) 968 return; 969 970 i915_error_printf(m, "DMC loaded: %s\n", 971 str_yes_no(intel_dmc_has_payload(i915))); 972 i915_error_printf(m, "DMC fw version: %d.%d\n", 973 DMC_VERSION_MAJOR(dmc->version), 974 DMC_VERSION_MINOR(dmc->version)); 975 } 976 977 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 978 { 979 struct drm_i915_private *i915 = m->private; 980 intel_wakeref_t wakeref; 981 struct intel_dmc *dmc; 982 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 983 984 if (!HAS_DMC(i915)) 985 return -ENODEV; 986 987 dmc = &i915->dmc; 988 989 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 990 991 seq_printf(m, "fw loaded: %s\n", 992 str_yes_no(intel_dmc_has_payload(i915))); 993 seq_printf(m, "path: %s\n", dmc->fw_path); 994 seq_printf(m, "Pipe A fw support: %s\n", 995 str_yes_no(GRAPHICS_VER(i915) >= 12)); 996 seq_printf(m, "Pipe A fw loaded: %s\n", 997 str_yes_no(dmc->dmc_info[DMC_FW_PIPEA].payload)); 998 seq_printf(m, "Pipe B fw support: %s\n", 999 str_yes_no(IS_ALDERLAKE_P(i915))); 1000 seq_printf(m, "Pipe B fw loaded: %s\n", 1001 str_yes_no(dmc->dmc_info[DMC_FW_PIPEB].payload)); 1002 1003 if (!intel_dmc_has_payload(i915)) 1004 goto out; 1005 1006 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1007 DMC_VERSION_MINOR(dmc->version)); 1008 1009 if (DISPLAY_VER(i915) >= 12) { 1010 if (IS_DGFX(i915)) { 1011 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1012 } else { 1013 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1014 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1015 } 1016 1017 /* 1018 * NOTE: DMC_DEBUG3 is a general purpose reg. 1019 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter 1020 * reg for DC3CO debugging and validation, 1021 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter. 1022 */ 1023 seq_printf(m, "DC3CO count: %d\n", 1024 intel_de_read(i915, IS_DGFX(i915) ? 1025 DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3)); 1026 } else { 1027 dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : 1028 SKL_DMC_DC3_DC5_COUNT; 1029 if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915)) 1030 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1031 } 1032 1033 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg)); 1034 if (i915_mmio_reg_valid(dc6_reg)) 1035 seq_printf(m, "DC5 -> DC6 count: %d\n", 1036 intel_de_read(i915, dc6_reg)); 1037 1038 out: 1039 seq_printf(m, "program base: 0x%08x\n", 1040 intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1041 seq_printf(m, "ssp base: 0x%08x\n", 1042 intel_de_read(i915, DMC_SSP_BASE)); 1043 seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL)); 1044 1045 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1046 1047 return 0; 1048 } 1049 1050 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1051 1052 void intel_dmc_debugfs_register(struct drm_i915_private *i915) 1053 { 1054 struct drm_minor *minor = i915->drm.primary; 1055 1056 debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, 1057 i915, &intel_dmc_debugfs_status_fops); 1058 } 1059