1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/firmware.h> 26 27 #include "i915_drv.h" 28 #include "i915_reg.h" 29 #include "intel_de.h" 30 #include "intel_dmc.h" 31 32 /** 33 * DOC: DMC Firmware Support 34 * 35 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 36 * engine to save and restore the state of display engine when it enter into 37 * low-power state and comes back to normal. 38 */ 39 40 #define DMC_PATH(platform, major, minor) \ 41 "i915/" \ 42 __stringify(platform) "_dmc_ver" \ 43 __stringify(major) "_" \ 44 __stringify(minor) ".bin" 45 46 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 47 48 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 49 50 #define ADLP_DMC_PATH DMC_PATH(adlp, 2, 14) 51 #define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 14) 52 MODULE_FIRMWARE(ADLP_DMC_PATH); 53 54 #define ADLS_DMC_PATH DMC_PATH(adls, 2, 01) 55 #define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1) 56 MODULE_FIRMWARE(ADLS_DMC_PATH); 57 58 #define DG1_DMC_PATH DMC_PATH(dg1, 2, 02) 59 #define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) 60 MODULE_FIRMWARE(DG1_DMC_PATH); 61 62 #define RKL_DMC_PATH DMC_PATH(rkl, 2, 03) 63 #define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 3) 64 MODULE_FIRMWARE(RKL_DMC_PATH); 65 66 #define TGL_DMC_PATH DMC_PATH(tgl, 2, 12) 67 #define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 12) 68 MODULE_FIRMWARE(TGL_DMC_PATH); 69 70 #define ICL_DMC_PATH DMC_PATH(icl, 1, 09) 71 #define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9) 72 #define ICL_DMC_MAX_FW_SIZE 0x6000 73 MODULE_FIRMWARE(ICL_DMC_PATH); 74 75 #define GLK_DMC_PATH DMC_PATH(glk, 1, 04) 76 #define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) 77 #define GLK_DMC_MAX_FW_SIZE 0x4000 78 MODULE_FIRMWARE(GLK_DMC_PATH); 79 80 #define KBL_DMC_PATH DMC_PATH(kbl, 1, 04) 81 #define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) 82 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 83 MODULE_FIRMWARE(KBL_DMC_PATH); 84 85 #define SKL_DMC_PATH DMC_PATH(skl, 1, 27) 86 #define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27) 87 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 88 MODULE_FIRMWARE(SKL_DMC_PATH); 89 90 #define BXT_DMC_PATH DMC_PATH(bxt, 1, 07) 91 #define BXT_DMC_VERSION_REQUIRED DMC_VERSION(1, 7) 92 #define BXT_DMC_MAX_FW_SIZE 0x3000 93 MODULE_FIRMWARE(BXT_DMC_PATH); 94 95 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 96 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 97 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 98 #define DMC_V1_MAX_MMIO_COUNT 8 99 #define DMC_V3_MAX_MMIO_COUNT 20 100 #define DMC_V1_MMIO_START_RANGE 0x80000 101 102 struct intel_css_header { 103 /* 0x09 for DMC */ 104 u32 module_type; 105 106 /* Includes the DMC specific header in dwords */ 107 u32 header_len; 108 109 /* always value would be 0x10000 */ 110 u32 header_ver; 111 112 /* Not used */ 113 u32 module_id; 114 115 /* Not used */ 116 u32 module_vendor; 117 118 /* in YYYYMMDD format */ 119 u32 date; 120 121 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 122 u32 size; 123 124 /* Not used */ 125 u32 key_size; 126 127 /* Not used */ 128 u32 modulus_size; 129 130 /* Not used */ 131 u32 exponent_size; 132 133 /* Not used */ 134 u32 reserved1[12]; 135 136 /* Major Minor */ 137 u32 version; 138 139 /* Not used */ 140 u32 reserved2[8]; 141 142 /* Not used */ 143 u32 kernel_header_info; 144 } __packed; 145 146 struct intel_fw_info { 147 u8 reserved1; 148 149 /* reserved on package_header version 1, must be 0 on version 2 */ 150 u8 dmc_id; 151 152 /* Stepping (A, B, C, ..., *). * is a wildcard */ 153 char stepping; 154 155 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 156 char substepping; 157 158 u32 offset; 159 u32 reserved2; 160 } __packed; 161 162 struct intel_package_header { 163 /* DMC container header length in dwords */ 164 u8 header_len; 165 166 /* 0x01, 0x02 */ 167 u8 header_ver; 168 169 u8 reserved[10]; 170 171 /* Number of valid entries in the FWInfo array below */ 172 u32 num_entries; 173 } __packed; 174 175 struct intel_dmc_header_base { 176 /* always value would be 0x40403E3E */ 177 u32 signature; 178 179 /* DMC binary header length */ 180 u8 header_len; 181 182 /* 0x01 */ 183 u8 header_ver; 184 185 /* Reserved */ 186 u16 dmcc_ver; 187 188 /* Major, Minor */ 189 u32 project; 190 191 /* Firmware program size (excluding header) in dwords */ 192 u32 fw_size; 193 194 /* Major Minor version */ 195 u32 fw_version; 196 } __packed; 197 198 struct intel_dmc_header_v1 { 199 struct intel_dmc_header_base base; 200 201 /* Number of valid MMIO cycles present. */ 202 u32 mmio_count; 203 204 /* MMIO address */ 205 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 206 207 /* MMIO data */ 208 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 209 210 /* FW filename */ 211 char dfile[32]; 212 213 u32 reserved1[2]; 214 } __packed; 215 216 struct intel_dmc_header_v3 { 217 struct intel_dmc_header_base base; 218 219 /* DMC RAM start MMIO address */ 220 u32 start_mmioaddr; 221 222 u32 reserved[9]; 223 224 /* FW filename */ 225 char dfile[32]; 226 227 /* Number of valid MMIO cycles present. */ 228 u32 mmio_count; 229 230 /* MMIO address */ 231 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 232 233 /* MMIO data */ 234 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 235 } __packed; 236 237 struct stepping_info { 238 char stepping; 239 char substepping; 240 }; 241 242 bool intel_dmc_has_payload(struct drm_i915_private *i915) 243 { 244 return i915->dmc.dmc_info[DMC_FW_MAIN].payload; 245 } 246 247 static const struct stepping_info * 248 intel_get_stepping_info(struct drm_i915_private *i915, 249 struct stepping_info *si) 250 { 251 const char *step_name = intel_step_name(RUNTIME_INFO(i915)->step.display_step); 252 253 si->stepping = step_name[0]; 254 si->substepping = step_name[1]; 255 return si; 256 } 257 258 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) 259 { 260 /* The below bit doesn't need to be cleared ever afterwards */ 261 intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0, 262 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 263 intel_de_posting_read(dev_priv, DC_STATE_DEBUG); 264 } 265 266 /** 267 * intel_dmc_load_program() - write the firmware from memory to register. 268 * @dev_priv: i915 drm device. 269 * 270 * DMC firmware is read from a .bin file and kept in internal memory one time. 271 * Everytime display comes back from low power state this function is called to 272 * copy the firmware from internal memory to registers. 273 */ 274 void intel_dmc_load_program(struct drm_i915_private *dev_priv) 275 { 276 struct intel_dmc *dmc = &dev_priv->dmc; 277 u32 id, i; 278 279 if (!HAS_DMC(dev_priv)) { 280 drm_err(&dev_priv->drm, 281 "No DMC support available for this platform\n"); 282 return; 283 } 284 285 if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) { 286 drm_err(&dev_priv->drm, 287 "Tried to program CSR with empty payload\n"); 288 return; 289 } 290 291 assert_rpm_wakelock_held(&dev_priv->runtime_pm); 292 293 preempt_disable(); 294 295 for (id = 0; id < DMC_FW_MAX; id++) { 296 for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) { 297 intel_uncore_write_fw(&dev_priv->uncore, 298 DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i), 299 dmc->dmc_info[id].payload[i]); 300 } 301 } 302 303 preempt_enable(); 304 305 for (id = 0; id < DMC_FW_MAX; id++) { 306 for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) { 307 intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i], 308 dmc->dmc_info[id].mmiodata[i]); 309 } 310 } 311 312 dev_priv->dmc.dc_state = 0; 313 314 gen9_set_dc_state_debugmask(dev_priv); 315 } 316 317 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 318 const struct stepping_info *si) 319 { 320 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 321 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 322 /* 323 * If we don't find a more specific one from above two checks, we 324 * then check for the generic one to be sure to work even with 325 * "broken firmware" 326 */ 327 (si->stepping == '*' && si->substepping == fw_info->substepping) || 328 (fw_info->stepping == '*' && fw_info->substepping == '*')) 329 return true; 330 331 return false; 332 } 333 334 /* 335 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 336 * already sanitized. 337 */ 338 static void dmc_set_fw_offset(struct intel_dmc *dmc, 339 const struct intel_fw_info *fw_info, 340 unsigned int num_entries, 341 const struct stepping_info *si, 342 u8 package_ver) 343 { 344 unsigned int i, id; 345 346 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 347 348 for (i = 0; i < num_entries; i++) { 349 id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 350 351 if (id >= DMC_FW_MAX) { 352 drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", id); 353 continue; 354 } 355 356 /* More specific versions come first, so we don't even have to 357 * check for the stepping since we already found a previous FW 358 * for this id. 359 */ 360 if (dmc->dmc_info[id].present) 361 continue; 362 363 if (fw_info_matches_stepping(&fw_info[i], si)) { 364 dmc->dmc_info[id].present = true; 365 dmc->dmc_info[id].dmc_offset = fw_info[i].offset; 366 } 367 } 368 } 369 370 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 371 const u32 *mmioaddr, u32 mmio_count, 372 int header_ver, u8 dmc_id) 373 { 374 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 375 u32 start_range, end_range; 376 int i; 377 378 if (dmc_id >= DMC_FW_MAX) { 379 drm_warn(&i915->drm, "Unsupported firmware id %u\n", dmc_id); 380 return false; 381 } 382 383 if (header_ver == 1) { 384 start_range = DMC_MMIO_START_RANGE; 385 end_range = DMC_MMIO_END_RANGE; 386 } else if (dmc_id == DMC_FW_MAIN) { 387 start_range = TGL_MAIN_MMIO_START; 388 end_range = TGL_MAIN_MMIO_END; 389 } else if (DISPLAY_VER(i915) >= 13) { 390 start_range = ADLP_PIPE_MMIO_START; 391 end_range = ADLP_PIPE_MMIO_END; 392 } else if (DISPLAY_VER(i915) >= 12) { 393 start_range = TGL_PIPE_MMIO_START(dmc_id); 394 end_range = TGL_PIPE_MMIO_END(dmc_id); 395 } else { 396 drm_warn(&i915->drm, "Unknown mmio range for sanity check"); 397 return false; 398 } 399 400 for (i = 0; i < mmio_count; i++) { 401 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 402 return false; 403 } 404 405 return true; 406 } 407 408 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 409 const struct intel_dmc_header_base *dmc_header, 410 size_t rem_size, u8 dmc_id) 411 { 412 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 413 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 414 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 415 const u32 *mmioaddr, *mmiodata; 416 u32 mmio_count, mmio_count_max, start_mmioaddr; 417 u8 *payload; 418 419 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 420 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 421 422 /* 423 * Check if we can access common fields, we will checkc again below 424 * after we have read the version 425 */ 426 if (rem_size < sizeof(struct intel_dmc_header_base)) 427 goto error_truncated; 428 429 /* Cope with small differences between v1 and v3 */ 430 if (dmc_header->header_ver == 3) { 431 const struct intel_dmc_header_v3 *v3 = 432 (const struct intel_dmc_header_v3 *)dmc_header; 433 434 if (rem_size < sizeof(struct intel_dmc_header_v3)) 435 goto error_truncated; 436 437 mmioaddr = v3->mmioaddr; 438 mmiodata = v3->mmiodata; 439 mmio_count = v3->mmio_count; 440 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 441 /* header_len is in dwords */ 442 header_len_bytes = dmc_header->header_len * 4; 443 start_mmioaddr = v3->start_mmioaddr; 444 dmc_header_size = sizeof(*v3); 445 } else if (dmc_header->header_ver == 1) { 446 const struct intel_dmc_header_v1 *v1 = 447 (const struct intel_dmc_header_v1 *)dmc_header; 448 449 if (rem_size < sizeof(struct intel_dmc_header_v1)) 450 goto error_truncated; 451 452 mmioaddr = v1->mmioaddr; 453 mmiodata = v1->mmiodata; 454 mmio_count = v1->mmio_count; 455 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 456 header_len_bytes = dmc_header->header_len; 457 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 458 dmc_header_size = sizeof(*v1); 459 } else { 460 drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", 461 dmc_header->header_ver); 462 return 0; 463 } 464 465 if (header_len_bytes != dmc_header_size) { 466 drm_err(&i915->drm, "DMC firmware has wrong dmc header length " 467 "(%u bytes)\n", header_len_bytes); 468 return 0; 469 } 470 471 /* Cache the dmc header info. */ 472 if (mmio_count > mmio_count_max) { 473 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 474 return 0; 475 } 476 477 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 478 dmc_header->header_ver, dmc_id)) { 479 drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n"); 480 return 0; 481 } 482 483 for (i = 0; i < mmio_count; i++) { 484 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 485 dmc_info->mmiodata[i] = mmiodata[i]; 486 } 487 dmc_info->mmio_count = mmio_count; 488 dmc_info->start_mmioaddr = start_mmioaddr; 489 490 rem_size -= header_len_bytes; 491 492 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 493 payload_size = dmc_header->fw_size * 4; 494 if (rem_size < payload_size) 495 goto error_truncated; 496 497 if (payload_size > dmc->max_fw_size) { 498 drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); 499 return 0; 500 } 501 dmc_info->dmc_fw_size = dmc_header->fw_size; 502 503 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 504 if (!dmc_info->payload) 505 return 0; 506 507 payload = (u8 *)(dmc_header) + header_len_bytes; 508 memcpy(dmc_info->payload, payload, payload_size); 509 510 return header_len_bytes + payload_size; 511 512 error_truncated: 513 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 514 return 0; 515 } 516 517 static u32 518 parse_dmc_fw_package(struct intel_dmc *dmc, 519 const struct intel_package_header *package_header, 520 const struct stepping_info *si, 521 size_t rem_size) 522 { 523 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 524 u32 package_size = sizeof(struct intel_package_header); 525 u32 num_entries, max_entries; 526 const struct intel_fw_info *fw_info; 527 528 if (rem_size < package_size) 529 goto error_truncated; 530 531 if (package_header->header_ver == 1) { 532 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 533 } else if (package_header->header_ver == 2) { 534 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 535 } else { 536 drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", 537 package_header->header_ver); 538 return 0; 539 } 540 541 /* 542 * We should always have space for max_entries, 543 * even if not all are used 544 */ 545 package_size += max_entries * sizeof(struct intel_fw_info); 546 if (rem_size < package_size) 547 goto error_truncated; 548 549 if (package_header->header_len * 4 != package_size) { 550 drm_err(&i915->drm, "DMC firmware has wrong package header length " 551 "(%u bytes)\n", package_size); 552 return 0; 553 } 554 555 num_entries = package_header->num_entries; 556 if (WARN_ON(package_header->num_entries > max_entries)) 557 num_entries = max_entries; 558 559 fw_info = (const struct intel_fw_info *) 560 ((u8 *)package_header + sizeof(*package_header)); 561 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 562 package_header->header_ver); 563 564 /* dmc_offset is in dwords */ 565 return package_size; 566 567 error_truncated: 568 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 569 return 0; 570 } 571 572 /* Return number of bytes parsed or 0 on error */ 573 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 574 struct intel_css_header *css_header, 575 size_t rem_size) 576 { 577 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 578 579 if (rem_size < sizeof(struct intel_css_header)) { 580 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 581 return 0; 582 } 583 584 if (sizeof(struct intel_css_header) != 585 (css_header->header_len * 4)) { 586 drm_err(&i915->drm, "DMC firmware has wrong CSS header length " 587 "(%u bytes)\n", 588 (css_header->header_len * 4)); 589 return 0; 590 } 591 592 if (dmc->required_version && 593 css_header->version != dmc->required_version) { 594 drm_info(&i915->drm, "Refusing to load DMC firmware v%u.%u," 595 " please use v%u.%u\n", 596 DMC_VERSION_MAJOR(css_header->version), 597 DMC_VERSION_MINOR(css_header->version), 598 DMC_VERSION_MAJOR(dmc->required_version), 599 DMC_VERSION_MINOR(dmc->required_version)); 600 return 0; 601 } 602 603 dmc->version = css_header->version; 604 605 return sizeof(struct intel_css_header); 606 } 607 608 static void parse_dmc_fw(struct drm_i915_private *dev_priv, 609 const struct firmware *fw) 610 { 611 struct intel_css_header *css_header; 612 struct intel_package_header *package_header; 613 struct intel_dmc_header_base *dmc_header; 614 struct intel_dmc *dmc = &dev_priv->dmc; 615 struct stepping_info display_info = { '*', '*'}; 616 const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info); 617 u32 readcount = 0; 618 u32 r, offset; 619 int id; 620 621 if (!fw) 622 return; 623 624 /* Extract CSS Header information */ 625 css_header = (struct intel_css_header *)fw->data; 626 r = parse_dmc_fw_css(dmc, css_header, fw->size); 627 if (!r) 628 return; 629 630 readcount += r; 631 632 /* Extract Package Header information */ 633 package_header = (struct intel_package_header *)&fw->data[readcount]; 634 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 635 if (!r) 636 return; 637 638 readcount += r; 639 640 for (id = 0; id < DMC_FW_MAX; id++) { 641 if (!dev_priv->dmc.dmc_info[id].present) 642 continue; 643 644 offset = readcount + dmc->dmc_info[id].dmc_offset * 4; 645 if (offset > fw->size) { 646 drm_err(&dev_priv->drm, "Reading beyond the fw_size\n"); 647 continue; 648 } 649 650 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 651 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id); 652 } 653 } 654 655 static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv) 656 { 657 drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); 658 dev_priv->dmc.wakeref = 659 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 660 } 661 662 static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv) 663 { 664 intel_wakeref_t wakeref __maybe_unused = 665 fetch_and_zero(&dev_priv->dmc.wakeref); 666 667 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 668 } 669 670 static void dmc_load_work_fn(struct work_struct *work) 671 { 672 struct drm_i915_private *dev_priv; 673 struct intel_dmc *dmc; 674 const struct firmware *fw = NULL; 675 676 dev_priv = container_of(work, typeof(*dev_priv), dmc.work); 677 dmc = &dev_priv->dmc; 678 679 request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev); 680 parse_dmc_fw(dev_priv, fw); 681 682 if (intel_dmc_has_payload(dev_priv)) { 683 intel_dmc_load_program(dev_priv); 684 intel_dmc_runtime_pm_put(dev_priv); 685 686 drm_info(&dev_priv->drm, 687 "Finished loading DMC firmware %s (v%u.%u)\n", 688 dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version), 689 DMC_VERSION_MINOR(dmc->version)); 690 } else { 691 drm_notice(&dev_priv->drm, 692 "Failed to load DMC firmware %s." 693 " Disabling runtime power management.\n", 694 dmc->fw_path); 695 drm_notice(&dev_priv->drm, "DMC firmware homepage: %s", 696 INTEL_UC_FIRMWARE_URL); 697 } 698 699 release_firmware(fw); 700 } 701 702 /** 703 * intel_dmc_ucode_init() - initialize the firmware loading. 704 * @dev_priv: i915 drm device. 705 * 706 * This function is called at the time of loading the display driver to read 707 * firmware from a .bin file and copied into a internal memory. 708 */ 709 void intel_dmc_ucode_init(struct drm_i915_private *dev_priv) 710 { 711 struct intel_dmc *dmc = &dev_priv->dmc; 712 713 INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn); 714 715 if (!HAS_DMC(dev_priv)) 716 return; 717 718 /* 719 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 720 * runtime-suspend. 721 * 722 * On error, we return with the rpm wakeref held to prevent runtime 723 * suspend as runtime suspend *requires* a working DMC for whatever 724 * reason. 725 */ 726 intel_dmc_runtime_pm_get(dev_priv); 727 728 if (IS_ALDERLAKE_P(dev_priv)) { 729 dmc->fw_path = ADLP_DMC_PATH; 730 dmc->required_version = ADLP_DMC_VERSION_REQUIRED; 731 dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 732 } else if (IS_ALDERLAKE_S(dev_priv)) { 733 dmc->fw_path = ADLS_DMC_PATH; 734 dmc->required_version = ADLS_DMC_VERSION_REQUIRED; 735 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 736 } else if (IS_DG1(dev_priv)) { 737 dmc->fw_path = DG1_DMC_PATH; 738 dmc->required_version = DG1_DMC_VERSION_REQUIRED; 739 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 740 } else if (IS_ROCKETLAKE(dev_priv)) { 741 dmc->fw_path = RKL_DMC_PATH; 742 dmc->required_version = RKL_DMC_VERSION_REQUIRED; 743 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 744 } else if (DISPLAY_VER(dev_priv) >= 12) { 745 dmc->fw_path = TGL_DMC_PATH; 746 dmc->required_version = TGL_DMC_VERSION_REQUIRED; 747 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 748 } else if (DISPLAY_VER(dev_priv) == 11) { 749 dmc->fw_path = ICL_DMC_PATH; 750 dmc->required_version = ICL_DMC_VERSION_REQUIRED; 751 dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE; 752 } else if (IS_GEMINILAKE(dev_priv)) { 753 dmc->fw_path = GLK_DMC_PATH; 754 dmc->required_version = GLK_DMC_VERSION_REQUIRED; 755 dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE; 756 } else if (IS_KABYLAKE(dev_priv) || 757 IS_COFFEELAKE(dev_priv) || 758 IS_COMETLAKE(dev_priv)) { 759 dmc->fw_path = KBL_DMC_PATH; 760 dmc->required_version = KBL_DMC_VERSION_REQUIRED; 761 dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE; 762 } else if (IS_SKYLAKE(dev_priv)) { 763 dmc->fw_path = SKL_DMC_PATH; 764 dmc->required_version = SKL_DMC_VERSION_REQUIRED; 765 dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE; 766 } else if (IS_BROXTON(dev_priv)) { 767 dmc->fw_path = BXT_DMC_PATH; 768 dmc->required_version = BXT_DMC_VERSION_REQUIRED; 769 dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE; 770 } 771 772 if (dev_priv->params.dmc_firmware_path) { 773 if (strlen(dev_priv->params.dmc_firmware_path) == 0) { 774 dmc->fw_path = NULL; 775 drm_info(&dev_priv->drm, 776 "Disabling DMC firmware and runtime PM\n"); 777 return; 778 } 779 780 dmc->fw_path = dev_priv->params.dmc_firmware_path; 781 /* Bypass version check for firmware override. */ 782 dmc->required_version = 0; 783 } 784 785 if (!dmc->fw_path) { 786 drm_dbg_kms(&dev_priv->drm, 787 "No known DMC firmware for platform, disabling runtime PM\n"); 788 return; 789 } 790 791 drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path); 792 schedule_work(&dev_priv->dmc.work); 793 } 794 795 /** 796 * intel_dmc_ucode_suspend() - prepare DMC firmware before system suspend 797 * @dev_priv: i915 drm device 798 * 799 * Prepare the DMC firmware before entering system suspend. This includes 800 * flushing pending work items and releasing any resources acquired during 801 * init. 802 */ 803 void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv) 804 { 805 if (!HAS_DMC(dev_priv)) 806 return; 807 808 flush_work(&dev_priv->dmc.work); 809 810 /* Drop the reference held in case DMC isn't loaded. */ 811 if (!intel_dmc_has_payload(dev_priv)) 812 intel_dmc_runtime_pm_put(dev_priv); 813 } 814 815 /** 816 * intel_dmc_ucode_resume() - init DMC firmware during system resume 817 * @dev_priv: i915 drm device 818 * 819 * Reinitialize the DMC firmware during system resume, reacquiring any 820 * resources released in intel_dmc_ucode_suspend(). 821 */ 822 void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv) 823 { 824 if (!HAS_DMC(dev_priv)) 825 return; 826 827 /* 828 * Reacquire the reference to keep RPM disabled in case DMC isn't 829 * loaded. 830 */ 831 if (!intel_dmc_has_payload(dev_priv)) 832 intel_dmc_runtime_pm_get(dev_priv); 833 } 834 835 /** 836 * intel_dmc_ucode_fini() - unload the DMC firmware. 837 * @dev_priv: i915 drm device. 838 * 839 * Firmmware unloading includes freeing the internal memory and reset the 840 * firmware loading status. 841 */ 842 void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv) 843 { 844 int id; 845 846 if (!HAS_DMC(dev_priv)) 847 return; 848 849 intel_dmc_ucode_suspend(dev_priv); 850 drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); 851 852 for (id = 0; id < DMC_FW_MAX; id++) 853 kfree(dev_priv->dmc.dmc_info[id].payload); 854 } 855