1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25 26 #ifndef __INTEL_DISPLAY_TYPES_H__ 27 #define __INTEL_DISPLAY_TYPES_H__ 28 29 #include <linux/async.h> 30 #include <linux/i2c.h> 31 #include <linux/pwm.h> 32 #include <linux/sched/clock.h> 33 34 #include <drm/drm_atomic.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_dp_dual_mode_helper.h> 37 #include <drm/drm_dp_mst_helper.h> 38 #include <drm/drm_encoder.h> 39 #include <drm/drm_fb_helper.h> 40 #include <drm/drm_fourcc.h> 41 #include <drm/drm_probe_helper.h> 42 #include <drm/drm_rect.h> 43 #include <drm/drm_vblank.h> 44 #include <drm/i915_mei_hdcp_interface.h> 45 #include <media/cec-notifier.h> 46 47 #include "i915_drv.h" 48 49 struct drm_printer; 50 struct __intel_global_objs_state; 51 struct intel_ddi_buf_trans; 52 53 /* 54 * Display related stuff 55 */ 56 57 /* these are outputs from the chip - integrated only 58 external chips are via DVO or SDVO output */ 59 enum intel_output_type { 60 INTEL_OUTPUT_UNUSED = 0, 61 INTEL_OUTPUT_ANALOG = 1, 62 INTEL_OUTPUT_DVO = 2, 63 INTEL_OUTPUT_SDVO = 3, 64 INTEL_OUTPUT_LVDS = 4, 65 INTEL_OUTPUT_TVOUT = 5, 66 INTEL_OUTPUT_HDMI = 6, 67 INTEL_OUTPUT_DP = 7, 68 INTEL_OUTPUT_EDP = 8, 69 INTEL_OUTPUT_DSI = 9, 70 INTEL_OUTPUT_DDI = 10, 71 INTEL_OUTPUT_DP_MST = 11, 72 }; 73 74 enum hdmi_force_audio { 75 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 76 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 77 HDMI_AUDIO_AUTO, /* trust EDID */ 78 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 79 }; 80 81 /* "Broadcast RGB" property */ 82 enum intel_broadcast_rgb { 83 INTEL_BROADCAST_RGB_AUTO, 84 INTEL_BROADCAST_RGB_FULL, 85 INTEL_BROADCAST_RGB_LIMITED, 86 }; 87 88 struct intel_fb_view { 89 /* 90 * The remap information used in the remapped and rotated views to 91 * create the DMA scatter-gather list for each FB color plane. This sg 92 * list is created along with the view type (gtt.type) specific 93 * i915_vma object and contains the list of FB object pages (reordered 94 * in the rotated view) that are visible in the view. 95 * In the normal view the FB object's backing store sg list is used 96 * directly and hence the remap information here is not used. 97 */ 98 struct i915_ggtt_view gtt; 99 100 /* 101 * The GTT view (gtt.type) specific information for each FB color 102 * plane. In the normal GTT view all formats (up to 4 color planes), 103 * in the rotated and remapped GTT view all no-CCS formats (up to 2 104 * color planes) are supported. 105 * 106 * The view information shared by all FB color planes in the FB, 107 * like dst x/y and src/dst width, is stored separately in 108 * intel_plane_state. 109 */ 110 struct i915_color_plane_view { 111 u32 offset; 112 unsigned int x, y; 113 /* 114 * Plane stride in: 115 * bytes for 0/180 degree rotation 116 * pixels for 90/270 degree rotation 117 */ 118 unsigned int stride; 119 } color_plane[4]; 120 }; 121 122 struct intel_framebuffer { 123 struct drm_framebuffer base; 124 struct intel_frontbuffer *frontbuffer; 125 126 /* Params to remap the FB pages and program the plane registers in each view. */ 127 struct intel_fb_view normal_view; 128 union { 129 struct intel_fb_view rotated_view; 130 struct intel_fb_view remapped_view; 131 }; 132 133 struct i915_address_space *dpt_vm; 134 }; 135 136 struct intel_fbdev { 137 struct drm_fb_helper helper; 138 struct intel_framebuffer *fb; 139 struct i915_vma *vma; 140 unsigned long vma_flags; 141 async_cookie_t cookie; 142 int preferred_bpp; 143 144 /* Whether or not fbdev hpd processing is temporarily suspended */ 145 bool hpd_suspended : 1; 146 /* Set when a hotplug was received while HPD processing was 147 * suspended 148 */ 149 bool hpd_waiting : 1; 150 151 /* Protects hpd_suspended */ 152 struct mutex hpd_lock; 153 }; 154 155 enum intel_hotplug_state { 156 INTEL_HOTPLUG_UNCHANGED, 157 INTEL_HOTPLUG_CHANGED, 158 INTEL_HOTPLUG_RETRY, 159 }; 160 161 struct intel_encoder { 162 struct drm_encoder base; 163 164 enum intel_output_type type; 165 enum port port; 166 u16 cloneable; 167 u8 pipe_mask; 168 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder, 169 struct intel_connector *connector); 170 enum intel_output_type (*compute_output_type)(struct intel_encoder *, 171 struct intel_crtc_state *, 172 struct drm_connector_state *); 173 int (*compute_config)(struct intel_encoder *, 174 struct intel_crtc_state *, 175 struct drm_connector_state *); 176 int (*compute_config_late)(struct intel_encoder *, 177 struct intel_crtc_state *, 178 struct drm_connector_state *); 179 void (*update_prepare)(struct intel_atomic_state *, 180 struct intel_encoder *, 181 struct intel_crtc *); 182 void (*pre_pll_enable)(struct intel_atomic_state *, 183 struct intel_encoder *, 184 const struct intel_crtc_state *, 185 const struct drm_connector_state *); 186 void (*pre_enable)(struct intel_atomic_state *, 187 struct intel_encoder *, 188 const struct intel_crtc_state *, 189 const struct drm_connector_state *); 190 void (*enable)(struct intel_atomic_state *, 191 struct intel_encoder *, 192 const struct intel_crtc_state *, 193 const struct drm_connector_state *); 194 void (*update_complete)(struct intel_atomic_state *, 195 struct intel_encoder *, 196 struct intel_crtc *); 197 void (*pre_disable)(struct intel_atomic_state *, 198 struct intel_encoder *, 199 const struct intel_crtc_state *, 200 const struct drm_connector_state *); 201 void (*disable)(struct intel_atomic_state *, 202 struct intel_encoder *, 203 const struct intel_crtc_state *, 204 const struct drm_connector_state *); 205 void (*post_disable)(struct intel_atomic_state *, 206 struct intel_encoder *, 207 const struct intel_crtc_state *, 208 const struct drm_connector_state *); 209 void (*post_pll_disable)(struct intel_atomic_state *, 210 struct intel_encoder *, 211 const struct intel_crtc_state *, 212 const struct drm_connector_state *); 213 void (*update_pipe)(struct intel_atomic_state *, 214 struct intel_encoder *, 215 const struct intel_crtc_state *, 216 const struct drm_connector_state *); 217 /* Read out the current hw state of this connector, returning true if 218 * the encoder is active. If the encoder is enabled it also set the pipe 219 * it is connected to in the pipe parameter. */ 220 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); 221 /* Reconstructs the equivalent mode flags for the current hardware 222 * state. This must be called _after_ display->get_pipe_config has 223 * pre-filled the pipe config. Note that intel_encoder->base.crtc must 224 * be set correctly before calling this function. */ 225 void (*get_config)(struct intel_encoder *, 226 struct intel_crtc_state *pipe_config); 227 228 /* 229 * Optional hook called during init/resume to sync any state 230 * stored in the encoder (eg. DP link parameters) wrt. the HW state. 231 */ 232 void (*sync_state)(struct intel_encoder *encoder, 233 const struct intel_crtc_state *crtc_state); 234 235 /* 236 * Optional hook, returning true if this encoder allows a fastset 237 * during the initial commit, false otherwise. 238 */ 239 bool (*initial_fastset_check)(struct intel_encoder *encoder, 240 struct intel_crtc_state *crtc_state); 241 242 /* 243 * Acquires the power domains needed for an active encoder during 244 * hardware state readout. 245 */ 246 void (*get_power_domains)(struct intel_encoder *encoder, 247 struct intel_crtc_state *crtc_state); 248 /* 249 * Called during system suspend after all pending requests for the 250 * encoder are flushed (for example for DP AUX transactions) and 251 * device interrupts are disabled. 252 */ 253 void (*suspend)(struct intel_encoder *); 254 /* 255 * Called during system reboot/shutdown after all the 256 * encoders have been disabled and suspended. 257 */ 258 void (*shutdown)(struct intel_encoder *encoder); 259 /* 260 * Enable/disable the clock to the port. 261 */ 262 void (*enable_clock)(struct intel_encoder *encoder, 263 const struct intel_crtc_state *crtc_state); 264 void (*disable_clock)(struct intel_encoder *encoder); 265 /* 266 * Returns whether the port clock is enabled or not. 267 */ 268 bool (*is_clock_enabled)(struct intel_encoder *encoder); 269 const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder, 270 const struct intel_crtc_state *crtc_state, 271 int *n_entries); 272 void (*set_signal_levels)(struct intel_encoder *encoder, 273 const struct intel_crtc_state *crtc_state); 274 275 enum hpd_pin hpd_pin; 276 enum intel_display_power_domain power_domain; 277 /* for communication with audio component; protected by av_mutex */ 278 const struct drm_connector *audio_connector; 279 280 /* VBT information for this encoder (may be NULL for older platforms) */ 281 const struct intel_bios_encoder_data *devdata; 282 }; 283 284 struct intel_panel_bl_funcs { 285 /* Connector and platform specific backlight functions */ 286 int (*setup)(struct intel_connector *connector, enum pipe pipe); 287 u32 (*get)(struct intel_connector *connector, enum pipe pipe); 288 void (*set)(const struct drm_connector_state *conn_state, u32 level); 289 void (*disable)(const struct drm_connector_state *conn_state, u32 level); 290 void (*enable)(const struct intel_crtc_state *crtc_state, 291 const struct drm_connector_state *conn_state, u32 level); 292 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz); 293 }; 294 295 struct intel_panel { 296 struct drm_display_mode *fixed_mode; 297 struct drm_display_mode *downclock_mode; 298 299 /* backlight */ 300 struct { 301 bool present; 302 u32 level; 303 u32 min; 304 u32 max; 305 bool enabled; 306 bool combination_mode; /* gen 2/4 only */ 307 bool active_low_pwm; 308 bool alternate_pwm_increment; /* lpt+ */ 309 310 /* PWM chip */ 311 u32 pwm_level_min; 312 u32 pwm_level_max; 313 bool pwm_enabled; 314 bool util_pin_active_low; /* bxt+ */ 315 u8 controller; /* bxt+ only */ 316 struct pwm_device *pwm; 317 struct pwm_state pwm_state; 318 319 /* DPCD backlight */ 320 union { 321 struct { 322 struct drm_edp_backlight_info info; 323 } vesa; 324 struct { 325 bool sdr_uses_aux; 326 } intel; 327 } edp; 328 329 struct backlight_device *device; 330 331 const struct intel_panel_bl_funcs *funcs; 332 const struct intel_panel_bl_funcs *pwm_funcs; 333 void (*power)(struct intel_connector *, bool enable); 334 } backlight; 335 }; 336 337 struct intel_digital_port; 338 339 enum check_link_response { 340 HDCP_LINK_PROTECTED = 0, 341 HDCP_TOPOLOGY_CHANGE, 342 HDCP_LINK_INTEGRITY_FAILURE, 343 HDCP_REAUTH_REQUEST 344 }; 345 346 /* 347 * This structure serves as a translation layer between the generic HDCP code 348 * and the bus-specific code. What that means is that HDCP over HDMI differs 349 * from HDCP over DP, so to account for these differences, we need to 350 * communicate with the receiver through this shim. 351 * 352 * For completeness, the 2 buses differ in the following ways: 353 * - DP AUX vs. DDC 354 * HDCP registers on the receiver are set via DP AUX for DP, and 355 * they are set via DDC for HDMI. 356 * - Receiver register offsets 357 * The offsets of the registers are different for DP vs. HDMI 358 * - Receiver register masks/offsets 359 * For instance, the ready bit for the KSV fifo is in a different 360 * place on DP vs HDMI 361 * - Receiver register names 362 * Seriously. In the DP spec, the 16-bit register containing 363 * downstream information is called BINFO, on HDMI it's called 364 * BSTATUS. To confuse matters further, DP has a BSTATUS register 365 * with a completely different definition. 366 * - KSV FIFO 367 * On HDMI, the ksv fifo is read all at once, whereas on DP it must 368 * be read 3 keys at a time 369 * - Aksv output 370 * Since Aksv is hidden in hardware, there's different procedures 371 * to send it over DP AUX vs DDC 372 */ 373 struct intel_hdcp_shim { 374 /* Outputs the transmitter's An and Aksv values to the receiver. */ 375 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an); 376 377 /* Reads the receiver's key selection vector */ 378 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv); 379 380 /* 381 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The 382 * definitions are the same in the respective specs, but the names are 383 * different. Call it BSTATUS since that's the name the HDMI spec 384 * uses and it was there first. 385 */ 386 int (*read_bstatus)(struct intel_digital_port *dig_port, 387 u8 *bstatus); 388 389 /* Determines whether a repeater is present downstream */ 390 int (*repeater_present)(struct intel_digital_port *dig_port, 391 bool *repeater_present); 392 393 /* Reads the receiver's Ri' value */ 394 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri); 395 396 /* Determines if the receiver's KSV FIFO is ready for consumption */ 397 int (*read_ksv_ready)(struct intel_digital_port *dig_port, 398 bool *ksv_ready); 399 400 /* Reads the ksv fifo for num_downstream devices */ 401 int (*read_ksv_fifo)(struct intel_digital_port *dig_port, 402 int num_downstream, u8 *ksv_fifo); 403 404 /* Reads a 32-bit part of V' from the receiver */ 405 int (*read_v_prime_part)(struct intel_digital_port *dig_port, 406 int i, u32 *part); 407 408 /* Enables HDCP signalling on the port */ 409 int (*toggle_signalling)(struct intel_digital_port *dig_port, 410 enum transcoder cpu_transcoder, 411 bool enable); 412 413 /* Enable/Disable stream encryption on DP MST Transport Link */ 414 int (*stream_encryption)(struct intel_connector *connector, 415 bool enable); 416 417 /* Ensures the link is still protected */ 418 bool (*check_link)(struct intel_digital_port *dig_port, 419 struct intel_connector *connector); 420 421 /* Detects panel's hdcp capability. This is optional for HDMI. */ 422 int (*hdcp_capable)(struct intel_digital_port *dig_port, 423 bool *hdcp_capable); 424 425 /* HDCP adaptation(DP/HDMI) required on the port */ 426 enum hdcp_wired_protocol protocol; 427 428 /* Detects whether sink is HDCP2.2 capable */ 429 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port, 430 bool *capable); 431 432 /* Write HDCP2.2 messages */ 433 int (*write_2_2_msg)(struct intel_digital_port *dig_port, 434 void *buf, size_t size); 435 436 /* Read HDCP2.2 messages */ 437 int (*read_2_2_msg)(struct intel_digital_port *dig_port, 438 u8 msg_id, void *buf, size_t size); 439 440 /* 441 * Implementation of DP HDCP2.2 Errata for the communication of stream 442 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to 443 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI. 444 */ 445 int (*config_stream_type)(struct intel_digital_port *dig_port, 446 bool is_repeater, u8 type); 447 448 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */ 449 int (*stream_2_2_encryption)(struct intel_connector *connector, 450 bool enable); 451 452 /* HDCP2.2 Link Integrity Check */ 453 int (*check_2_2_link)(struct intel_digital_port *dig_port, 454 struct intel_connector *connector); 455 }; 456 457 struct intel_hdcp { 458 const struct intel_hdcp_shim *shim; 459 /* Mutex for hdcp state of the connector */ 460 struct mutex mutex; 461 u64 value; 462 struct delayed_work check_work; 463 struct work_struct prop_work; 464 465 /* HDCP1.4 Encryption status */ 466 bool hdcp_encrypted; 467 468 /* HDCP2.2 related definitions */ 469 /* Flag indicates whether this connector supports HDCP2.2 or not. */ 470 bool hdcp2_supported; 471 472 /* HDCP2.2 Encryption status */ 473 bool hdcp2_encrypted; 474 475 /* 476 * Content Stream Type defined by content owner. TYPE0(0x0) content can 477 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1) 478 * content can flow only through a link protected by HDCP2.2. 479 */ 480 u8 content_type; 481 482 bool is_paired; 483 bool is_repeater; 484 485 /* 486 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT. 487 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List. 488 * When it rolls over re-auth has to be triggered. 489 */ 490 u32 seq_num_v; 491 492 /* 493 * Count of RepeaterAuth_Stream_Manage msg propagated. 494 * Initialized to 0 on AKE_INIT. Incremented after every successful 495 * transmission of RepeaterAuth_Stream_Manage message. When it rolls 496 * over re-Auth has to be triggered. 497 */ 498 u32 seq_num_m; 499 500 /* 501 * Work queue to signal the CP_IRQ. Used for the waiters to read the 502 * available information from HDCP DP sink. 503 */ 504 wait_queue_head_t cp_irq_queue; 505 atomic_t cp_irq_count; 506 int cp_irq_count_cached; 507 508 /* 509 * HDCP register access for gen12+ need the transcoder associated. 510 * Transcoder attached to the connector could be changed at modeset. 511 * Hence caching the transcoder here. 512 */ 513 enum transcoder cpu_transcoder; 514 /* Only used for DP MST stream encryption */ 515 enum transcoder stream_transcoder; 516 }; 517 518 struct intel_connector { 519 struct drm_connector base; 520 /* 521 * The fixed encoder this connector is connected to. 522 */ 523 struct intel_encoder *encoder; 524 525 /* ACPI device id for ACPI and driver cooperation */ 526 u32 acpi_device_id; 527 528 /* Reads out the current hw, returning true if the connector is enabled 529 * and active (i.e. dpms ON state). */ 530 bool (*get_hw_state)(struct intel_connector *); 531 532 /* Panel info for eDP and LVDS */ 533 struct intel_panel panel; 534 535 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 536 struct edid *edid; 537 struct edid *detect_edid; 538 539 /* Number of times hotplug detection was tried after an HPD interrupt */ 540 int hotplug_retries; 541 542 /* since POLL and HPD connectors may use the same HPD line keep the native 543 state of connector->polled in case hotplug storm detection changes it */ 544 u8 polled; 545 546 struct drm_dp_mst_port *port; 547 548 struct intel_dp *mst_port; 549 550 /* Work struct to schedule a uevent on link train failure */ 551 struct work_struct modeset_retry_work; 552 553 struct intel_hdcp hdcp; 554 }; 555 556 struct intel_digital_connector_state { 557 struct drm_connector_state base; 558 559 enum hdmi_force_audio force_audio; 560 int broadcast_rgb; 561 }; 562 563 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base) 564 565 struct dpll { 566 /* given values */ 567 int n; 568 int m1, m2; 569 int p1, p2; 570 /* derived values */ 571 int dot; 572 int vco; 573 int m; 574 int p; 575 }; 576 577 struct intel_atomic_state { 578 struct drm_atomic_state base; 579 580 intel_wakeref_t wakeref; 581 582 struct __intel_global_objs_state *global_objs; 583 int num_global_objs; 584 585 bool dpll_set, modeset; 586 587 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; 588 589 /* 590 * Current watermarks can't be trusted during hardware readout, so 591 * don't bother calculating intermediate watermarks. 592 */ 593 bool skip_intermediate_wm; 594 595 bool rps_interactive; 596 597 struct i915_sw_fence commit_ready; 598 599 struct llist_node freed; 600 }; 601 602 struct intel_plane_state { 603 struct drm_plane_state uapi; 604 605 /* 606 * actual hardware state, the state we program to the hardware. 607 * The following members are used to verify the hardware state: 608 * During initial hw readout, they need to be copied from uapi. 609 */ 610 struct { 611 struct drm_crtc *crtc; 612 struct drm_framebuffer *fb; 613 614 u16 alpha; 615 u16 pixel_blend_mode; 616 unsigned int rotation; 617 enum drm_color_encoding color_encoding; 618 enum drm_color_range color_range; 619 enum drm_scaling_filter scaling_filter; 620 } hw; 621 622 struct i915_vma *ggtt_vma; 623 struct i915_vma *dpt_vma; 624 unsigned long flags; 625 #define PLANE_HAS_FENCE BIT(0) 626 627 struct intel_fb_view view; 628 629 /* Plane pxp decryption state */ 630 bool decrypt; 631 632 /* Plane state to display black pixels when pxp is borked */ 633 bool force_black; 634 635 /* plane control register */ 636 u32 ctl; 637 638 /* plane color control register */ 639 u32 color_ctl; 640 641 /* chroma upsampler control register */ 642 u32 cus_ctl; 643 644 /* 645 * scaler_id 646 * = -1 : not using a scaler 647 * >= 0 : using a scalers 648 * 649 * plane requiring a scaler: 650 * - During check_plane, its bit is set in 651 * crtc_state->scaler_state.scaler_users by calling helper function 652 * update_scaler_plane. 653 * - scaler_id indicates the scaler it got assigned. 654 * 655 * plane doesn't require a scaler: 656 * - this can happen when scaling is no more required or plane simply 657 * got disabled. 658 * - During check_plane, corresponding bit is reset in 659 * crtc_state->scaler_state.scaler_users by calling helper function 660 * update_scaler_plane. 661 */ 662 int scaler_id; 663 664 /* 665 * planar_linked_plane: 666 * 667 * ICL planar formats require 2 planes that are updated as pairs. 668 * This member is used to make sure the other plane is also updated 669 * when required, and for update_slave() to find the correct 670 * plane_state to pass as argument. 671 */ 672 struct intel_plane *planar_linked_plane; 673 674 /* 675 * planar_slave: 676 * If set don't update use the linked plane's state for updating 677 * this plane during atomic commit with the update_slave() callback. 678 * 679 * It's also used by the watermark code to ignore wm calculations on 680 * this plane. They're calculated by the linked plane's wm code. 681 */ 682 u32 planar_slave; 683 684 struct drm_intel_sprite_colorkey ckey; 685 686 struct drm_rect psr2_sel_fetch_area; 687 688 /* Clear Color Value */ 689 u64 ccval; 690 }; 691 692 struct intel_initial_plane_config { 693 struct intel_framebuffer *fb; 694 struct i915_vma *vma; 695 unsigned int tiling; 696 int size; 697 u32 base; 698 u8 rotation; 699 }; 700 701 struct intel_scaler { 702 int in_use; 703 u32 mode; 704 }; 705 706 struct intel_crtc_scaler_state { 707 #define SKL_NUM_SCALERS 2 708 struct intel_scaler scalers[SKL_NUM_SCALERS]; 709 710 /* 711 * scaler_users: keeps track of users requesting scalers on this crtc. 712 * 713 * If a bit is set, a user is using a scaler. 714 * Here user can be a plane or crtc as defined below: 715 * bits 0-30 - plane (bit position is index from drm_plane_index) 716 * bit 31 - crtc 717 * 718 * Instead of creating a new index to cover planes and crtc, using 719 * existing drm_plane_index for planes which is well less than 31 720 * planes and bit 31 for crtc. This should be fine to cover all 721 * our platforms. 722 * 723 * intel_atomic_setup_scalers will setup available scalers to users 724 * requesting scalers. It will gracefully fail if request exceeds 725 * avilability. 726 */ 727 #define SKL_CRTC_INDEX 31 728 unsigned scaler_users; 729 730 /* scaler used by crtc for panel fitting purpose */ 731 int scaler_id; 732 }; 733 734 /* {crtc,crtc_state}->mode_flags */ 735 /* Flag to get scanline using frame time stamps */ 736 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1) 737 /* Flag to use the scanline counter instead of the pixel counter */ 738 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2) 739 /* 740 * TE0 or TE1 flag is set if the crtc has a DSI encoder which 741 * is operating in command mode. 742 * Flag to use TE from DSI0 instead of VBI in command mode 743 */ 744 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3) 745 /* Flag to use TE from DSI1 instead of VBI in command mode */ 746 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4) 747 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */ 748 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5) 749 /* Do tricks to make vblank timestamps sane with VRR? */ 750 #define I915_MODE_FLAG_VRR (1<<6) 751 752 struct intel_wm_level { 753 bool enable; 754 u32 pri_val; 755 u32 spr_val; 756 u32 cur_val; 757 u32 fbc_val; 758 }; 759 760 struct intel_pipe_wm { 761 struct intel_wm_level wm[5]; 762 bool fbc_wm_enabled; 763 bool pipe_enabled; 764 bool sprites_enabled; 765 bool sprites_scaled; 766 }; 767 768 struct skl_wm_level { 769 u16 min_ddb_alloc; 770 u16 blocks; 771 u8 lines; 772 bool enable; 773 bool ignore_lines; 774 bool can_sagv; 775 }; 776 777 struct skl_plane_wm { 778 struct skl_wm_level wm[8]; 779 struct skl_wm_level uv_wm[8]; 780 struct skl_wm_level trans_wm; 781 struct { 782 struct skl_wm_level wm0; 783 struct skl_wm_level trans_wm; 784 } sagv; 785 bool is_planar; 786 }; 787 788 struct skl_pipe_wm { 789 struct skl_plane_wm planes[I915_MAX_PLANES]; 790 bool use_sagv_wm; 791 }; 792 793 enum vlv_wm_level { 794 VLV_WM_LEVEL_PM2, 795 VLV_WM_LEVEL_PM5, 796 VLV_WM_LEVEL_DDR_DVFS, 797 NUM_VLV_WM_LEVELS, 798 }; 799 800 struct vlv_wm_state { 801 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS]; 802 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS]; 803 u8 num_levels; 804 bool cxsr; 805 }; 806 807 struct vlv_fifo_state { 808 u16 plane[I915_MAX_PLANES]; 809 }; 810 811 enum g4x_wm_level { 812 G4X_WM_LEVEL_NORMAL, 813 G4X_WM_LEVEL_SR, 814 G4X_WM_LEVEL_HPLL, 815 NUM_G4X_WM_LEVELS, 816 }; 817 818 struct g4x_wm_state { 819 struct g4x_pipe_wm wm; 820 struct g4x_sr_wm sr; 821 struct g4x_sr_wm hpll; 822 bool cxsr; 823 bool hpll_en; 824 bool fbc_en; 825 }; 826 827 struct intel_crtc_wm_state { 828 union { 829 /* 830 * raw: 831 * The "raw" watermark values produced by the formula 832 * given the plane's current state. They do not consider 833 * how much FIFO is actually allocated for each plane. 834 * 835 * optimal: 836 * The "optimal" watermark values given the current 837 * state of the planes and the amount of FIFO 838 * allocated to each, ignoring any previous state 839 * of the planes. 840 * 841 * intermediate: 842 * The "intermediate" watermark values when transitioning 843 * between the old and new "optimal" values. Used when 844 * the watermark registers are single buffered and hence 845 * their state changes asynchronously with regards to the 846 * actual plane registers. These are essentially the 847 * worst case combination of the old and new "optimal" 848 * watermarks, which are therefore safe to use when the 849 * plane is in either its old or new state. 850 */ 851 struct { 852 struct intel_pipe_wm intermediate; 853 struct intel_pipe_wm optimal; 854 } ilk; 855 856 struct { 857 struct skl_pipe_wm raw; 858 /* gen9+ only needs 1-step wm programming */ 859 struct skl_pipe_wm optimal; 860 struct skl_ddb_entry ddb; 861 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES]; 862 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES]; 863 } skl; 864 865 struct { 866 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */ 867 struct vlv_wm_state intermediate; /* inverted */ 868 struct vlv_wm_state optimal; /* inverted */ 869 struct vlv_fifo_state fifo_state; 870 } vlv; 871 872 struct { 873 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS]; 874 struct g4x_wm_state intermediate; 875 struct g4x_wm_state optimal; 876 } g4x; 877 }; 878 879 /* 880 * Platforms with two-step watermark programming will need to 881 * update watermark programming post-vblank to switch from the 882 * safe intermediate watermarks to the optimal final 883 * watermarks. 884 */ 885 bool need_postvbl_update; 886 }; 887 888 enum intel_output_format { 889 INTEL_OUTPUT_FORMAT_RGB, 890 INTEL_OUTPUT_FORMAT_YCBCR420, 891 INTEL_OUTPUT_FORMAT_YCBCR444, 892 }; 893 894 struct intel_mpllb_state { 895 u32 clock; /* in KHz */ 896 u32 ref_control; 897 u32 mpllb_cp; 898 u32 mpllb_div; 899 u32 mpllb_div2; 900 u32 mpllb_fracn1; 901 u32 mpllb_fracn2; 902 u32 mpllb_sscen; 903 u32 mpllb_sscstep; 904 }; 905 906 struct intel_crtc_state { 907 /* 908 * uapi (drm) state. This is the software state shown to userspace. 909 * In particular, the following members are used for bookkeeping: 910 * - crtc 911 * - state 912 * - *_changed 913 * - event 914 * - commit 915 * - mode_blob 916 */ 917 struct drm_crtc_state uapi; 918 919 /* 920 * actual hardware state, the state we program to the hardware. 921 * The following members are used to verify the hardware state: 922 * - enable 923 * - active 924 * - mode / pipe_mode / adjusted_mode 925 * - color property blobs. 926 * 927 * During initial hw readout, they need to be copied to uapi. 928 * 929 * Bigjoiner will allow a transcoder mode that spans 2 pipes; 930 * Use the pipe_mode for calculations like watermarks, pipe 931 * scaler, and bandwidth. 932 * 933 * Use adjusted_mode for things that need to know the full 934 * mode on the transcoder, which spans all pipes. 935 */ 936 struct { 937 bool active, enable; 938 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; 939 struct drm_display_mode mode, pipe_mode, adjusted_mode; 940 enum drm_scaling_filter scaling_filter; 941 } hw; 942 943 /** 944 * quirks - bitfield with hw state readout quirks 945 * 946 * For various reasons the hw state readout code might not be able to 947 * completely faithfully read out the current state. These cases are 948 * tracked with quirk flags so that fastboot and state checker can act 949 * accordingly. 950 */ 951 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ 952 #define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */ 953 unsigned long quirks; 954 955 unsigned fb_bits; /* framebuffers to flip */ 956 bool update_pipe; /* can a fast modeset be performed? */ 957 bool disable_cxsr; 958 bool update_wm_pre, update_wm_post; /* watermarks are updated */ 959 bool fifo_changed; /* FIFO split is changed */ 960 bool preload_luts; 961 bool inherited; /* state inherited from BIOS? */ 962 963 /* Pipe source size (ie. panel fitter input size) 964 * All planes will be positioned inside this space, 965 * and get clipped at the edges. */ 966 int pipe_src_w, pipe_src_h; 967 968 /* 969 * Pipe pixel rate, adjusted for 970 * panel fitter/pipe scaler downscaling. 971 */ 972 unsigned int pixel_rate; 973 974 /* Whether to set up the PCH/FDI. Note that we never allow sharing 975 * between pch encoders and cpu encoders. */ 976 bool has_pch_encoder; 977 978 /* Are we sending infoframes on the attached port */ 979 bool has_infoframe; 980 981 /* CPU Transcoder for the pipe. Currently this can only differ from the 982 * pipe on Haswell and later (where we have a special eDP transcoder) 983 * and Broxton (where we have special DSI transcoders). */ 984 enum transcoder cpu_transcoder; 985 986 /* 987 * Use reduced/limited/broadcast rbg range, compressing from the full 988 * range fed into the crtcs. 989 */ 990 bool limited_color_range; 991 992 /* Bitmask of encoder types (enum intel_output_type) 993 * driven by the pipe. 994 */ 995 unsigned int output_types; 996 997 /* Whether we should send NULL infoframes. Required for audio. */ 998 bool has_hdmi_sink; 999 1000 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or 1001 * has_dp_encoder is set. */ 1002 bool has_audio; 1003 1004 /* 1005 * Enable dithering, used when the selected pipe bpp doesn't match the 1006 * plane bpp. 1007 */ 1008 bool dither; 1009 1010 /* 1011 * Dither gets enabled for 18bpp which causes CRC mismatch errors for 1012 * compliance video pattern tests. 1013 * Disable dither only if it is a compliance test request for 1014 * 18bpp. 1015 */ 1016 bool dither_force_disable; 1017 1018 /* Controls for the clock computation, to override various stages. */ 1019 bool clock_set; 1020 1021 /* SDVO TV has a bunch of special case. To make multifunction encoders 1022 * work correctly, we need to track this at runtime.*/ 1023 bool sdvo_tv_clock; 1024 1025 /* 1026 * crtc bandwidth limit, don't increase pipe bpp or clock if not really 1027 * required. This is set in the 2nd loop of calling encoder's 1028 * ->compute_config if the first pick doesn't work out. 1029 */ 1030 bool bw_constrained; 1031 1032 /* Settings for the intel dpll used on pretty much everything but 1033 * haswell. */ 1034 struct dpll dpll; 1035 1036 /* Selected dpll when shared or NULL. */ 1037 struct intel_shared_dpll *shared_dpll; 1038 1039 /* Actual register state of the dpll, for shared dpll cross-checking. */ 1040 union { 1041 struct intel_dpll_hw_state dpll_hw_state; 1042 struct intel_mpllb_state mpllb_state; 1043 }; 1044 1045 /* 1046 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by 1047 * setting shared_dpll and dpll_hw_state to one of these reserved ones. 1048 */ 1049 struct icl_port_dpll { 1050 struct intel_shared_dpll *pll; 1051 struct intel_dpll_hw_state hw_state; 1052 } icl_port_dplls[ICL_PORT_DPLL_COUNT]; 1053 1054 /* DSI PLL registers */ 1055 struct { 1056 u32 ctrl, div; 1057 } dsi_pll; 1058 1059 int pipe_bpp; 1060 struct intel_link_m_n dp_m_n; 1061 1062 /* m2_n2 for eDP downclock */ 1063 struct intel_link_m_n dp_m2_n2; 1064 bool has_drrs; 1065 1066 /* PSR is supported but might not be enabled due the lack of enabled planes */ 1067 bool has_psr; 1068 bool has_psr2; 1069 bool enable_psr2_sel_fetch; 1070 bool req_psr2_sdp_prior_scanline; 1071 u32 dc3co_exitline; 1072 u16 su_y_granularity; 1073 struct drm_dp_vsc_sdp psr_vsc; 1074 1075 /* 1076 * Frequence the dpll for the port should run at. Differs from the 1077 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also 1078 * already multiplied by pixel_multiplier. 1079 */ 1080 int port_clock; 1081 1082 /* Used by SDVO (and if we ever fix it, HDMI). */ 1083 unsigned pixel_multiplier; 1084 1085 /* I915_MODE_FLAG_* */ 1086 u8 mode_flags; 1087 1088 u8 lane_count; 1089 1090 /* 1091 * Used by platforms having DP/HDMI PHY with programmable lane 1092 * latency optimization. 1093 */ 1094 u8 lane_lat_optim_mask; 1095 1096 /* minimum acceptable voltage level */ 1097 u8 min_voltage_level; 1098 1099 /* Panel fitter controls for gen2-gen4 + VLV */ 1100 struct { 1101 u32 control; 1102 u32 pgm_ratios; 1103 u32 lvds_border_bits; 1104 } gmch_pfit; 1105 1106 /* Panel fitter placement and size for Ironlake+ */ 1107 struct { 1108 struct drm_rect dst; 1109 bool enabled; 1110 bool force_thru; 1111 } pch_pfit; 1112 1113 /* FDI configuration, only valid if has_pch_encoder is set. */ 1114 int fdi_lanes; 1115 struct intel_link_m_n fdi_m_n; 1116 1117 bool ips_enabled; 1118 1119 bool crc_enabled; 1120 1121 bool enable_fbc; 1122 1123 bool double_wide; 1124 1125 int pbn; 1126 1127 struct intel_crtc_scaler_state scaler_state; 1128 1129 /* w/a for waiting 2 vblanks during crtc enable */ 1130 enum pipe hsw_workaround_pipe; 1131 1132 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ 1133 bool disable_lp_wm; 1134 1135 struct intel_crtc_wm_state wm; 1136 1137 int min_cdclk[I915_MAX_PLANES]; 1138 1139 u32 data_rate[I915_MAX_PLANES]; 1140 1141 /* FIXME unify with data_rate[] */ 1142 u64 plane_data_rate[I915_MAX_PLANES]; 1143 u64 uv_plane_data_rate[I915_MAX_PLANES]; 1144 1145 /* Gamma mode programmed on the pipe */ 1146 u32 gamma_mode; 1147 1148 union { 1149 /* CSC mode programmed on the pipe */ 1150 u32 csc_mode; 1151 1152 /* CHV CGM mode */ 1153 u32 cgm_mode; 1154 }; 1155 1156 /* bitmask of logically enabled planes (enum plane_id) */ 1157 u8 enabled_planes; 1158 1159 /* bitmask of actually visible planes (enum plane_id) */ 1160 u8 active_planes; 1161 u8 nv12_planes; 1162 u8 c8_planes; 1163 1164 /* bitmask of planes that will be updated during the commit */ 1165 u8 update_planes; 1166 1167 struct { 1168 u32 enable; 1169 u32 gcp; 1170 union hdmi_infoframe avi; 1171 union hdmi_infoframe spd; 1172 union hdmi_infoframe hdmi; 1173 union hdmi_infoframe drm; 1174 struct drm_dp_vsc_sdp vsc; 1175 } infoframes; 1176 1177 /* HDMI scrambling status */ 1178 bool hdmi_scrambling; 1179 1180 /* HDMI High TMDS char rate ratio */ 1181 bool hdmi_high_tmds_clock_ratio; 1182 1183 /* Output format RGB/YCBCR etc */ 1184 enum intel_output_format output_format; 1185 1186 /* enable pipe gamma? */ 1187 bool gamma_enable; 1188 1189 /* enable pipe csc? */ 1190 bool csc_enable; 1191 1192 /* enable pipe big joiner? */ 1193 bool bigjoiner; 1194 1195 /* big joiner slave crtc? */ 1196 bool bigjoiner_slave; 1197 1198 /* linked crtc for bigjoiner, either slave or master */ 1199 struct intel_crtc *bigjoiner_linked_crtc; 1200 1201 /* Display Stream compression state */ 1202 struct { 1203 bool compression_enable; 1204 bool dsc_split; 1205 u16 compressed_bpp; 1206 u8 slice_count; 1207 struct drm_dsc_config config; 1208 } dsc; 1209 1210 /* HSW+ linetime watermarks */ 1211 u16 linetime; 1212 u16 ips_linetime; 1213 1214 /* Forward Error correction State */ 1215 bool fec_enable; 1216 1217 /* Pointer to master transcoder in case of tiled displays */ 1218 enum transcoder master_transcoder; 1219 1220 /* Bitmask to indicate slaves attached */ 1221 u8 sync_mode_slaves_mask; 1222 1223 /* Only valid on TGL+ */ 1224 enum transcoder mst_master_transcoder; 1225 1226 /* For DSB related info */ 1227 struct intel_dsb *dsb; 1228 1229 u32 psr2_man_track_ctl; 1230 1231 /* Variable Refresh Rate state */ 1232 struct { 1233 bool enable; 1234 u8 pipeline_full; 1235 u16 flipline, vmin, vmax, guardband; 1236 } vrr; 1237 1238 /* Stream Splitter for eDP MSO */ 1239 struct { 1240 bool enable; 1241 u8 link_count; 1242 u8 pixel_overlap; 1243 } splitter; 1244 }; 1245 1246 enum intel_pipe_crc_source { 1247 INTEL_PIPE_CRC_SOURCE_NONE, 1248 INTEL_PIPE_CRC_SOURCE_PLANE1, 1249 INTEL_PIPE_CRC_SOURCE_PLANE2, 1250 INTEL_PIPE_CRC_SOURCE_PLANE3, 1251 INTEL_PIPE_CRC_SOURCE_PLANE4, 1252 INTEL_PIPE_CRC_SOURCE_PLANE5, 1253 INTEL_PIPE_CRC_SOURCE_PLANE6, 1254 INTEL_PIPE_CRC_SOURCE_PLANE7, 1255 INTEL_PIPE_CRC_SOURCE_PIPE, 1256 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1257 INTEL_PIPE_CRC_SOURCE_TV, 1258 INTEL_PIPE_CRC_SOURCE_DP_B, 1259 INTEL_PIPE_CRC_SOURCE_DP_C, 1260 INTEL_PIPE_CRC_SOURCE_DP_D, 1261 INTEL_PIPE_CRC_SOURCE_AUTO, 1262 INTEL_PIPE_CRC_SOURCE_MAX, 1263 }; 1264 1265 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1266 struct intel_pipe_crc { 1267 spinlock_t lock; 1268 int skipped; 1269 enum intel_pipe_crc_source source; 1270 }; 1271 1272 struct intel_crtc { 1273 struct drm_crtc base; 1274 enum pipe pipe; 1275 /* 1276 * Whether the crtc and the connected output pipeline is active. Implies 1277 * that crtc->enabled is set, i.e. the current mode configuration has 1278 * some outputs connected to this crtc. 1279 */ 1280 bool active; 1281 u8 plane_ids_mask; 1282 1283 /* I915_MODE_FLAG_* */ 1284 u8 mode_flags; 1285 1286 u16 vmax_vblank_start; 1287 1288 struct intel_display_power_domain_set enabled_power_domains; 1289 struct intel_overlay *overlay; 1290 1291 struct intel_crtc_state *config; 1292 1293 /* Access to these should be protected by dev_priv->irq_lock. */ 1294 bool cpu_fifo_underrun_disabled; 1295 bool pch_fifo_underrun_disabled; 1296 1297 /* per-pipe watermark state */ 1298 struct { 1299 /* watermarks currently being used */ 1300 union { 1301 struct intel_pipe_wm ilk; 1302 struct vlv_wm_state vlv; 1303 struct g4x_wm_state g4x; 1304 } active; 1305 } wm; 1306 1307 int scanline_offset; 1308 1309 struct { 1310 unsigned start_vbl_count; 1311 ktime_t start_vbl_time; 1312 int min_vbl, max_vbl; 1313 int scanline_start; 1314 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE 1315 struct { 1316 u64 min; 1317 u64 max; 1318 u64 sum; 1319 unsigned int over; 1320 unsigned int times[17]; /* [1us, 16ms] */ 1321 } vbl; 1322 #endif 1323 } debug; 1324 1325 /* scalers available on this crtc */ 1326 int num_scalers; 1327 1328 #ifdef CONFIG_DEBUG_FS 1329 struct intel_pipe_crc pipe_crc; 1330 #endif 1331 }; 1332 1333 struct intel_plane { 1334 struct drm_plane base; 1335 enum i9xx_plane_id i9xx_plane; 1336 enum plane_id id; 1337 enum pipe pipe; 1338 bool has_fbc; 1339 bool has_ccs; 1340 bool need_async_flip_disable_wa; 1341 u32 frontbuffer_bit; 1342 1343 struct { 1344 u32 base, cntl, size; 1345 } cursor; 1346 1347 /* 1348 * NOTE: Do not place new plane state fields here (e.g., when adding 1349 * new plane properties). New runtime state should now be placed in 1350 * the intel_plane_state structure and accessed via plane_state. 1351 */ 1352 1353 int (*min_width)(const struct drm_framebuffer *fb, 1354 int color_plane, 1355 unsigned int rotation); 1356 int (*max_width)(const struct drm_framebuffer *fb, 1357 int color_plane, 1358 unsigned int rotation); 1359 int (*max_height)(const struct drm_framebuffer *fb, 1360 int color_plane, 1361 unsigned int rotation); 1362 unsigned int (*max_stride)(struct intel_plane *plane, 1363 u32 pixel_format, u64 modifier, 1364 unsigned int rotation); 1365 void (*update_plane)(struct intel_plane *plane, 1366 const struct intel_crtc_state *crtc_state, 1367 const struct intel_plane_state *plane_state); 1368 void (*disable_plane)(struct intel_plane *plane, 1369 const struct intel_crtc_state *crtc_state); 1370 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe); 1371 int (*check_plane)(struct intel_crtc_state *crtc_state, 1372 struct intel_plane_state *plane_state); 1373 int (*min_cdclk)(const struct intel_crtc_state *crtc_state, 1374 const struct intel_plane_state *plane_state); 1375 void (*async_flip)(struct intel_plane *plane, 1376 const struct intel_crtc_state *crtc_state, 1377 const struct intel_plane_state *plane_state, 1378 bool async_flip); 1379 void (*enable_flip_done)(struct intel_plane *plane); 1380 void (*disable_flip_done)(struct intel_plane *plane); 1381 }; 1382 1383 struct intel_watermark_params { 1384 u16 fifo_size; 1385 u16 max_wm; 1386 u8 default_wm; 1387 u8 guard_size; 1388 u8 cacheline_size; 1389 }; 1390 1391 struct cxsr_latency { 1392 bool is_desktop : 1; 1393 bool is_ddr3 : 1; 1394 u16 fsb_freq; 1395 u16 mem_freq; 1396 u16 display_sr; 1397 u16 display_hpll_disable; 1398 u16 cursor_sr; 1399 u16 cursor_hpll_disable; 1400 }; 1401 1402 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) 1403 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 1404 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi) 1405 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 1406 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 1407 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 1408 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 1409 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi) 1410 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL) 1411 1412 struct intel_hdmi { 1413 i915_reg_t hdmi_reg; 1414 int ddc_bus; 1415 struct { 1416 enum drm_dp_dual_mode_type type; 1417 int max_tmds_clock; 1418 } dp_dual_mode; 1419 bool has_hdmi_sink; 1420 bool has_audio; 1421 struct intel_connector *attached_connector; 1422 struct cec_notifier *cec_notifier; 1423 }; 1424 1425 struct intel_dp_mst_encoder; 1426 /* 1427 * enum link_m_n_set: 1428 * When platform provides two set of M_N registers for dp, we can 1429 * program them and switch between them incase of DRRS. 1430 * But When only one such register is provided, we have to program the 1431 * required divider value on that registers itself based on the DRRS state. 1432 * 1433 * M1_N1 : Program dp_m_n on M1_N1 registers 1434 * dp_m2_n2 on M2_N2 registers (If supported) 1435 * 1436 * M2_N2 : Program dp_m2_n2 on M1_N1 registers 1437 * M2_N2 registers are not supported 1438 */ 1439 1440 enum link_m_n_set { 1441 /* Sets the m1_n1 and m2_n2 */ 1442 M1_N1 = 0, 1443 M2_N2 1444 }; 1445 1446 struct intel_dp_compliance_data { 1447 unsigned long edid; 1448 u8 video_pattern; 1449 u16 hdisplay, vdisplay; 1450 u8 bpc; 1451 struct drm_dp_phy_test_params phytest; 1452 }; 1453 1454 struct intel_dp_compliance { 1455 unsigned long test_type; 1456 struct intel_dp_compliance_data test_data; 1457 bool test_active; 1458 int test_link_rate; 1459 u8 test_lane_count; 1460 }; 1461 1462 struct intel_dp_pcon_frl { 1463 bool is_trained; 1464 int trained_rate_gbps; 1465 }; 1466 1467 struct intel_pps { 1468 int panel_power_up_delay; 1469 int panel_power_down_delay; 1470 int panel_power_cycle_delay; 1471 int backlight_on_delay; 1472 int backlight_off_delay; 1473 struct delayed_work panel_vdd_work; 1474 bool want_panel_vdd; 1475 unsigned long last_power_on; 1476 unsigned long last_backlight_off; 1477 ktime_t panel_power_off_time; 1478 intel_wakeref_t vdd_wakeref; 1479 1480 /* 1481 * Pipe whose power sequencer is currently locked into 1482 * this port. Only relevant on VLV/CHV. 1483 */ 1484 enum pipe pps_pipe; 1485 /* 1486 * Pipe currently driving the port. Used for preventing 1487 * the use of the PPS for any pipe currentrly driving 1488 * external DP as that will mess things up on VLV. 1489 */ 1490 enum pipe active_pipe; 1491 /* 1492 * Set if the sequencer may be reset due to a power transition, 1493 * requiring a reinitialization. Only relevant on BXT. 1494 */ 1495 bool pps_reset; 1496 struct edp_power_seq pps_delays; 1497 }; 1498 1499 struct intel_psr { 1500 /* Mutex for PSR state of the transcoder */ 1501 struct mutex lock; 1502 1503 #define I915_PSR_DEBUG_MODE_MASK 0x0f 1504 #define I915_PSR_DEBUG_DEFAULT 0x00 1505 #define I915_PSR_DEBUG_DISABLE 0x01 1506 #define I915_PSR_DEBUG_ENABLE 0x02 1507 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 1508 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4 1509 #define I915_PSR_DEBUG_IRQ 0x10 1510 1511 u32 debug; 1512 bool sink_support; 1513 bool source_support; 1514 bool enabled; 1515 bool paused; 1516 enum pipe pipe; 1517 enum transcoder transcoder; 1518 bool active; 1519 struct work_struct work; 1520 unsigned int busy_frontbuffer_bits; 1521 bool sink_psr2_support; 1522 bool link_standby; 1523 bool colorimetry_support; 1524 bool psr2_enabled; 1525 bool psr2_sel_fetch_enabled; 1526 bool req_psr2_sdp_prior_scanline; 1527 u8 sink_sync_latency; 1528 ktime_t last_entry_attempt; 1529 ktime_t last_exit; 1530 bool sink_not_reliable; 1531 bool irq_aux_error; 1532 u16 su_w_granularity; 1533 u16 su_y_granularity; 1534 u32 dc3co_exitline; 1535 u32 dc3co_exit_delay; 1536 struct delayed_work dc3co_work; 1537 }; 1538 1539 struct intel_dp { 1540 i915_reg_t output_reg; 1541 u32 DP; 1542 int link_rate; 1543 u8 lane_count; 1544 u8 sink_count; 1545 bool link_trained; 1546 bool has_hdmi_sink; 1547 bool has_audio; 1548 bool reset_link_params; 1549 bool use_max_params; 1550 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 1551 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 1552 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 1553 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; 1554 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; 1555 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; 1556 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; 1557 u8 fec_capable; 1558 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]; 1559 /* source rates */ 1560 int num_source_rates; 1561 const int *source_rates; 1562 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */ 1563 int num_sink_rates; 1564 int sink_rates[DP_MAX_SUPPORTED_RATES]; 1565 bool use_rate_select; 1566 /* intersection of source and sink rates */ 1567 int num_common_rates; 1568 int common_rates[DP_MAX_SUPPORTED_RATES]; 1569 /* Max lane count for the current link */ 1570 int max_link_lane_count; 1571 /* Max rate for the current link */ 1572 int max_link_rate; 1573 int mso_link_count; 1574 int mso_pixel_overlap; 1575 /* sink or branch descriptor */ 1576 struct drm_dp_desc desc; 1577 struct drm_dp_aux aux; 1578 u32 aux_busy_last_status; 1579 u8 train_set[4]; 1580 1581 struct intel_pps pps; 1582 1583 bool is_mst; 1584 int active_mst_links; 1585 1586 /* connector directly attached - won't be use for modeset in mst world */ 1587 struct intel_connector *attached_connector; 1588 1589 /* mst connector list */ 1590 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; 1591 struct drm_dp_mst_topology_mgr mst_mgr; 1592 1593 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index); 1594 /* 1595 * This function returns the value we have to program the AUX_CTL 1596 * register with to kick off an AUX transaction. 1597 */ 1598 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes, 1599 u32 aux_clock_divider); 1600 1601 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); 1602 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); 1603 1604 /* This is called before a link training is starterd */ 1605 void (*prepare_link_retrain)(struct intel_dp *intel_dp, 1606 const struct intel_crtc_state *crtc_state); 1607 void (*set_link_train)(struct intel_dp *intel_dp, 1608 const struct intel_crtc_state *crtc_state, 1609 u8 dp_train_pat); 1610 void (*set_idle_link_train)(struct intel_dp *intel_dp, 1611 const struct intel_crtc_state *crtc_state); 1612 1613 u8 (*preemph_max)(struct intel_dp *intel_dp); 1614 u8 (*voltage_max)(struct intel_dp *intel_dp, 1615 const struct intel_crtc_state *crtc_state); 1616 1617 /* Displayport compliance testing */ 1618 struct intel_dp_compliance compliance; 1619 1620 /* Downstream facing port caps */ 1621 struct { 1622 int min_tmds_clock, max_tmds_clock; 1623 int max_dotclock; 1624 int pcon_max_frl_bw; 1625 u8 max_bpc; 1626 bool ycbcr_444_to_420; 1627 bool rgb_to_ycbcr; 1628 } dfp; 1629 1630 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1631 struct pm_qos_request pm_qos; 1632 1633 /* Display stream compression testing */ 1634 bool force_dsc_en; 1635 int force_dsc_bpp; 1636 1637 bool hobl_failed; 1638 bool hobl_active; 1639 1640 struct intel_dp_pcon_frl frl; 1641 1642 struct intel_psr psr; 1643 }; 1644 1645 enum lspcon_vendor { 1646 LSPCON_VENDOR_MCA, 1647 LSPCON_VENDOR_PARADE 1648 }; 1649 1650 struct intel_lspcon { 1651 bool active; 1652 bool hdr_supported; 1653 enum drm_lspcon_mode mode; 1654 enum lspcon_vendor vendor; 1655 }; 1656 1657 struct intel_digital_port { 1658 struct intel_encoder base; 1659 u32 saved_port_bits; 1660 struct intel_dp dp; 1661 struct intel_hdmi hdmi; 1662 struct intel_lspcon lspcon; 1663 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); 1664 bool release_cl2_override; 1665 u8 max_lanes; 1666 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */ 1667 enum aux_ch aux_ch; 1668 enum intel_display_power_domain ddi_io_power_domain; 1669 intel_wakeref_t ddi_io_wakeref; 1670 intel_wakeref_t aux_wakeref; 1671 1672 struct mutex tc_lock; /* protects the TypeC port mode */ 1673 intel_wakeref_t tc_lock_wakeref; 1674 enum intel_display_power_domain tc_lock_power_domain; 1675 struct delayed_work tc_disconnect_phy_work; 1676 int tc_link_refcount; 1677 bool tc_legacy_port:1; 1678 char tc_port_name[8]; 1679 enum tc_port_mode tc_mode; 1680 enum phy_fia tc_phy_fia; 1681 u8 tc_phy_fia_idx; 1682 1683 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */ 1684 struct mutex hdcp_mutex; 1685 /* the number of pipes using HDCP signalling out of this port */ 1686 unsigned int num_hdcp_streams; 1687 /* port HDCP auth status */ 1688 bool hdcp_auth_status; 1689 /* HDCP port data need to pass to security f/w */ 1690 struct hdcp_port_data hdcp_port_data; 1691 /* Whether the MST topology supports HDCP Type 1 Content */ 1692 bool hdcp_mst_type1_capable; 1693 1694 void (*write_infoframe)(struct intel_encoder *encoder, 1695 const struct intel_crtc_state *crtc_state, 1696 unsigned int type, 1697 const void *frame, ssize_t len); 1698 void (*read_infoframe)(struct intel_encoder *encoder, 1699 const struct intel_crtc_state *crtc_state, 1700 unsigned int type, 1701 void *frame, ssize_t len); 1702 void (*set_infoframes)(struct intel_encoder *encoder, 1703 bool enable, 1704 const struct intel_crtc_state *crtc_state, 1705 const struct drm_connector_state *conn_state); 1706 u32 (*infoframes_enabled)(struct intel_encoder *encoder, 1707 const struct intel_crtc_state *pipe_config); 1708 bool (*connected)(struct intel_encoder *encoder); 1709 }; 1710 1711 struct intel_dp_mst_encoder { 1712 struct intel_encoder base; 1713 enum pipe pipe; 1714 struct intel_digital_port *primary; 1715 struct intel_connector *connector; 1716 }; 1717 1718 static inline enum dpio_channel 1719 vlv_dig_port_to_channel(struct intel_digital_port *dig_port) 1720 { 1721 switch (dig_port->base.port) { 1722 case PORT_B: 1723 case PORT_D: 1724 return DPIO_CH0; 1725 case PORT_C: 1726 return DPIO_CH1; 1727 default: 1728 BUG(); 1729 } 1730 } 1731 1732 static inline enum dpio_phy 1733 vlv_dig_port_to_phy(struct intel_digital_port *dig_port) 1734 { 1735 switch (dig_port->base.port) { 1736 case PORT_B: 1737 case PORT_C: 1738 return DPIO_PHY0; 1739 case PORT_D: 1740 return DPIO_PHY1; 1741 default: 1742 BUG(); 1743 } 1744 } 1745 1746 static inline enum dpio_channel 1747 vlv_pipe_to_channel(enum pipe pipe) 1748 { 1749 switch (pipe) { 1750 case PIPE_A: 1751 case PIPE_C: 1752 return DPIO_CH0; 1753 case PIPE_B: 1754 return DPIO_CH1; 1755 default: 1756 BUG(); 1757 } 1758 } 1759 1760 static inline bool intel_pipe_valid(struct drm_i915_private *i915, enum pipe pipe) 1761 { 1762 return (pipe >= 0 && 1763 pipe < ARRAY_SIZE(i915->pipe_to_crtc_mapping) && 1764 INTEL_INFO(i915)->pipe_mask & BIT(pipe) && 1765 i915->pipe_to_crtc_mapping[pipe]); 1766 } 1767 1768 static inline struct intel_crtc * 1769 intel_get_first_crtc(struct drm_i915_private *dev_priv) 1770 { 1771 return to_intel_crtc(drm_crtc_from_index(&dev_priv->drm, 0)); 1772 } 1773 1774 static inline struct intel_crtc * 1775 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 1776 { 1777 /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */ 1778 drm_WARN_ON(&dev_priv->drm, 1779 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe))); 1780 return dev_priv->pipe_to_crtc_mapping[pipe]; 1781 } 1782 1783 static inline struct intel_crtc * 1784 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane) 1785 { 1786 return dev_priv->plane_to_crtc_mapping[plane]; 1787 } 1788 1789 struct intel_load_detect_pipe { 1790 struct drm_atomic_state *restore_state; 1791 }; 1792 1793 static inline struct intel_encoder * 1794 intel_attached_encoder(struct intel_connector *connector) 1795 { 1796 return connector->encoder; 1797 } 1798 1799 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder) 1800 { 1801 switch (encoder->type) { 1802 case INTEL_OUTPUT_DDI: 1803 case INTEL_OUTPUT_DP: 1804 case INTEL_OUTPUT_EDP: 1805 case INTEL_OUTPUT_HDMI: 1806 return true; 1807 default: 1808 return false; 1809 } 1810 } 1811 1812 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder) 1813 { 1814 return encoder->type == INTEL_OUTPUT_DP_MST; 1815 } 1816 1817 static inline struct intel_dp_mst_encoder * 1818 enc_to_mst(struct intel_encoder *encoder) 1819 { 1820 return container_of(&encoder->base, struct intel_dp_mst_encoder, 1821 base.base); 1822 } 1823 1824 static inline struct intel_digital_port * 1825 enc_to_dig_port(struct intel_encoder *encoder) 1826 { 1827 struct intel_encoder *intel_encoder = encoder; 1828 1829 if (intel_encoder_is_dig_port(intel_encoder)) 1830 return container_of(&encoder->base, struct intel_digital_port, 1831 base.base); 1832 else if (intel_encoder_is_mst(intel_encoder)) 1833 return enc_to_mst(encoder)->primary; 1834 else 1835 return NULL; 1836 } 1837 1838 static inline struct intel_digital_port * 1839 intel_attached_dig_port(struct intel_connector *connector) 1840 { 1841 return enc_to_dig_port(intel_attached_encoder(connector)); 1842 } 1843 1844 static inline struct intel_hdmi * 1845 enc_to_intel_hdmi(struct intel_encoder *encoder) 1846 { 1847 return &enc_to_dig_port(encoder)->hdmi; 1848 } 1849 1850 static inline struct intel_hdmi * 1851 intel_attached_hdmi(struct intel_connector *connector) 1852 { 1853 return enc_to_intel_hdmi(intel_attached_encoder(connector)); 1854 } 1855 1856 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder) 1857 { 1858 return &enc_to_dig_port(encoder)->dp; 1859 } 1860 1861 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector) 1862 { 1863 return enc_to_intel_dp(intel_attached_encoder(connector)); 1864 } 1865 1866 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) 1867 { 1868 switch (encoder->type) { 1869 case INTEL_OUTPUT_DP: 1870 case INTEL_OUTPUT_EDP: 1871 return true; 1872 case INTEL_OUTPUT_DDI: 1873 /* Skip pure HDMI/DVI DDI encoders */ 1874 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg); 1875 default: 1876 return false; 1877 } 1878 } 1879 1880 static inline struct intel_lspcon * 1881 enc_to_intel_lspcon(struct intel_encoder *encoder) 1882 { 1883 return &enc_to_dig_port(encoder)->lspcon; 1884 } 1885 1886 static inline struct intel_digital_port * 1887 dp_to_dig_port(struct intel_dp *intel_dp) 1888 { 1889 return container_of(intel_dp, struct intel_digital_port, dp); 1890 } 1891 1892 static inline struct intel_lspcon * 1893 dp_to_lspcon(struct intel_dp *intel_dp) 1894 { 1895 return &dp_to_dig_port(intel_dp)->lspcon; 1896 } 1897 1898 static inline struct drm_i915_private * 1899 dp_to_i915(struct intel_dp *intel_dp) 1900 { 1901 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 1902 } 1903 1904 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ 1905 (intel_dp)->psr.source_support) 1906 1907 static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) 1908 { 1909 if (!intel_encoder_is_dp(encoder)) 1910 return false; 1911 1912 return CAN_PSR(enc_to_intel_dp(encoder)); 1913 } 1914 1915 static inline struct intel_digital_port * 1916 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 1917 { 1918 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 1919 } 1920 1921 static inline struct intel_plane_state * 1922 intel_atomic_get_plane_state(struct intel_atomic_state *state, 1923 struct intel_plane *plane) 1924 { 1925 struct drm_plane_state *ret = 1926 drm_atomic_get_plane_state(&state->base, &plane->base); 1927 1928 if (IS_ERR(ret)) 1929 return ERR_CAST(ret); 1930 1931 return to_intel_plane_state(ret); 1932 } 1933 1934 static inline struct intel_plane_state * 1935 intel_atomic_get_old_plane_state(struct intel_atomic_state *state, 1936 struct intel_plane *plane) 1937 { 1938 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base, 1939 &plane->base)); 1940 } 1941 1942 static inline struct intel_plane_state * 1943 intel_atomic_get_new_plane_state(struct intel_atomic_state *state, 1944 struct intel_plane *plane) 1945 { 1946 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base, 1947 &plane->base)); 1948 } 1949 1950 static inline struct intel_crtc_state * 1951 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state, 1952 struct intel_crtc *crtc) 1953 { 1954 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base, 1955 &crtc->base)); 1956 } 1957 1958 static inline struct intel_crtc_state * 1959 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state, 1960 struct intel_crtc *crtc) 1961 { 1962 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, 1963 &crtc->base)); 1964 } 1965 1966 static inline struct intel_digital_connector_state * 1967 intel_atomic_get_new_connector_state(struct intel_atomic_state *state, 1968 struct intel_connector *connector) 1969 { 1970 return to_intel_digital_connector_state( 1971 drm_atomic_get_new_connector_state(&state->base, 1972 &connector->base)); 1973 } 1974 1975 static inline struct intel_digital_connector_state * 1976 intel_atomic_get_old_connector_state(struct intel_atomic_state *state, 1977 struct intel_connector *connector) 1978 { 1979 return to_intel_digital_connector_state( 1980 drm_atomic_get_old_connector_state(&state->base, 1981 &connector->base)); 1982 } 1983 1984 /* intel_display.c */ 1985 static inline bool 1986 intel_crtc_has_type(const struct intel_crtc_state *crtc_state, 1987 enum intel_output_type type) 1988 { 1989 return crtc_state->output_types & (1 << type); 1990 } 1991 static inline bool 1992 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) 1993 { 1994 return crtc_state->output_types & 1995 ((1 << INTEL_OUTPUT_DP) | 1996 (1 << INTEL_OUTPUT_DP_MST) | 1997 (1 << INTEL_OUTPUT_EDP)); 1998 } 1999 2000 static inline bool 2001 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state) 2002 { 2003 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi); 2004 } 2005 2006 static inline void 2007 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) 2008 { 2009 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 2010 2011 drm_crtc_wait_one_vblank(&crtc->base); 2012 } 2013 2014 static inline void 2015 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe) 2016 { 2017 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 2018 2019 if (crtc->active) 2020 intel_wait_for_vblank(dev_priv, pipe); 2021 } 2022 2023 static inline bool intel_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier) 2024 { 2025 return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR; 2026 } 2027 2028 static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) 2029 { 2030 return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier); 2031 } 2032 2033 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state) 2034 { 2035 return i915_ggtt_offset(plane_state->ggtt_vma); 2036 } 2037 2038 static inline struct intel_frontbuffer * 2039 to_intel_frontbuffer(struct drm_framebuffer *fb) 2040 { 2041 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; 2042 } 2043 2044 static inline bool is_ccs_modifier(u64 modifier) 2045 { 2046 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || 2047 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || 2048 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || 2049 modifier == I915_FORMAT_MOD_Y_TILED_CCS || 2050 modifier == I915_FORMAT_MOD_Yf_TILED_CCS; 2051 } 2052 2053 static inline bool is_gen12_ccs_modifier(u64 modifier) 2054 { 2055 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || 2056 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || 2057 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; 2058 } 2059 2060 #endif /* __INTEL_DISPLAY_TYPES_H__ */ 2061