1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25 26 #ifndef __INTEL_DISPLAY_TYPES_H__ 27 #define __INTEL_DISPLAY_TYPES_H__ 28 29 #include <linux/i2c.h> 30 #include <linux/pm_qos.h> 31 #include <linux/pwm.h> 32 #include <linux/sched/clock.h> 33 34 #include <drm/display/drm_dp_dual_mode_helper.h> 35 #include <drm/display/drm_dp_mst_helper.h> 36 #include <drm/display/drm_dsc.h> 37 #include <drm/drm_atomic.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_encoder.h> 40 #include <drm/drm_fourcc.h> 41 #include <drm/drm_framebuffer.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_rect.h> 44 #include <drm/drm_vblank.h> 45 #include <drm/drm_vblank_work.h> 46 #include <drm/i915_hdcp_interface.h> 47 #include <media/cec-notifier.h> 48 49 #include "i915_vma.h" 50 #include "i915_vma_types.h" 51 #include "intel_bios.h" 52 #include "intel_display.h" 53 #include "intel_display_limits.h" 54 #include "intel_display_power.h" 55 #include "intel_dpll_mgr.h" 56 #include "intel_wm_types.h" 57 58 struct drm_printer; 59 struct __intel_global_objs_state; 60 struct intel_ddi_buf_trans; 61 struct intel_fbc; 62 struct intel_connector; 63 struct intel_tc_port; 64 65 /* 66 * Display related stuff 67 */ 68 69 /* these are outputs from the chip - integrated only 70 external chips are via DVO or SDVO output */ 71 enum intel_output_type { 72 INTEL_OUTPUT_UNUSED = 0, 73 INTEL_OUTPUT_ANALOG = 1, 74 INTEL_OUTPUT_DVO = 2, 75 INTEL_OUTPUT_SDVO = 3, 76 INTEL_OUTPUT_LVDS = 4, 77 INTEL_OUTPUT_TVOUT = 5, 78 INTEL_OUTPUT_HDMI = 6, 79 INTEL_OUTPUT_DP = 7, 80 INTEL_OUTPUT_EDP = 8, 81 INTEL_OUTPUT_DSI = 9, 82 INTEL_OUTPUT_DDI = 10, 83 INTEL_OUTPUT_DP_MST = 11, 84 }; 85 86 enum hdmi_force_audio { 87 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 88 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 89 HDMI_AUDIO_AUTO, /* trust EDID */ 90 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 91 }; 92 93 /* "Broadcast RGB" property */ 94 enum intel_broadcast_rgb { 95 INTEL_BROADCAST_RGB_AUTO, 96 INTEL_BROADCAST_RGB_FULL, 97 INTEL_BROADCAST_RGB_LIMITED, 98 }; 99 100 struct intel_fb_view { 101 /* 102 * The remap information used in the remapped and rotated views to 103 * create the DMA scatter-gather list for each FB color plane. This sg 104 * list is created along with the view type (gtt.type) specific 105 * i915_vma object and contains the list of FB object pages (reordered 106 * in the rotated view) that are visible in the view. 107 * In the normal view the FB object's backing store sg list is used 108 * directly and hence the remap information here is not used. 109 */ 110 struct i915_gtt_view gtt; 111 112 /* 113 * The GTT view (gtt.type) specific information for each FB color 114 * plane. In the normal GTT view all formats (up to 4 color planes), 115 * in the rotated and remapped GTT view all no-CCS formats (up to 2 116 * color planes) are supported. 117 * 118 * The view information shared by all FB color planes in the FB, 119 * like dst x/y and src/dst width, is stored separately in 120 * intel_plane_state. 121 */ 122 struct i915_color_plane_view { 123 u32 offset; 124 unsigned int x, y; 125 /* 126 * Plane stride in: 127 * bytes for 0/180 degree rotation 128 * pixels for 90/270 degree rotation 129 */ 130 unsigned int mapping_stride; 131 unsigned int scanout_stride; 132 } color_plane[4]; 133 }; 134 135 struct intel_framebuffer { 136 struct drm_framebuffer base; 137 struct intel_frontbuffer *frontbuffer; 138 139 /* Params to remap the FB pages and program the plane registers in each view. */ 140 struct intel_fb_view normal_view; 141 union { 142 struct intel_fb_view rotated_view; 143 struct intel_fb_view remapped_view; 144 }; 145 146 struct i915_address_space *dpt_vm; 147 }; 148 149 enum intel_hotplug_state { 150 INTEL_HOTPLUG_UNCHANGED, 151 INTEL_HOTPLUG_CHANGED, 152 INTEL_HOTPLUG_RETRY, 153 }; 154 155 struct intel_encoder { 156 struct drm_encoder base; 157 158 enum intel_output_type type; 159 enum port port; 160 u16 cloneable; 161 u8 pipe_mask; 162 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder, 163 struct intel_connector *connector); 164 enum intel_output_type (*compute_output_type)(struct intel_encoder *, 165 struct intel_crtc_state *, 166 struct drm_connector_state *); 167 int (*compute_config)(struct intel_encoder *, 168 struct intel_crtc_state *, 169 struct drm_connector_state *); 170 int (*compute_config_late)(struct intel_encoder *, 171 struct intel_crtc_state *, 172 struct drm_connector_state *); 173 void (*pre_pll_enable)(struct intel_atomic_state *, 174 struct intel_encoder *, 175 const struct intel_crtc_state *, 176 const struct drm_connector_state *); 177 void (*pre_enable)(struct intel_atomic_state *, 178 struct intel_encoder *, 179 const struct intel_crtc_state *, 180 const struct drm_connector_state *); 181 void (*enable)(struct intel_atomic_state *, 182 struct intel_encoder *, 183 const struct intel_crtc_state *, 184 const struct drm_connector_state *); 185 void (*disable)(struct intel_atomic_state *, 186 struct intel_encoder *, 187 const struct intel_crtc_state *, 188 const struct drm_connector_state *); 189 void (*post_disable)(struct intel_atomic_state *, 190 struct intel_encoder *, 191 const struct intel_crtc_state *, 192 const struct drm_connector_state *); 193 void (*post_pll_disable)(struct intel_atomic_state *, 194 struct intel_encoder *, 195 const struct intel_crtc_state *, 196 const struct drm_connector_state *); 197 void (*update_pipe)(struct intel_atomic_state *, 198 struct intel_encoder *, 199 const struct intel_crtc_state *, 200 const struct drm_connector_state *); 201 /* Read out the current hw state of this connector, returning true if 202 * the encoder is active. If the encoder is enabled it also set the pipe 203 * it is connected to in the pipe parameter. */ 204 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); 205 /* Reconstructs the equivalent mode flags for the current hardware 206 * state. This must be called _after_ display->get_pipe_config has 207 * pre-filled the pipe config. Note that intel_encoder->base.crtc must 208 * be set correctly before calling this function. */ 209 void (*get_config)(struct intel_encoder *, 210 struct intel_crtc_state *pipe_config); 211 212 /* 213 * Optional hook called during init/resume to sync any state 214 * stored in the encoder (eg. DP link parameters) wrt. the HW state. 215 */ 216 void (*sync_state)(struct intel_encoder *encoder, 217 const struct intel_crtc_state *crtc_state); 218 219 /* 220 * Optional hook, returning true if this encoder allows a fastset 221 * during the initial commit, false otherwise. 222 */ 223 bool (*initial_fastset_check)(struct intel_encoder *encoder, 224 struct intel_crtc_state *crtc_state); 225 226 /* 227 * Acquires the power domains needed for an active encoder during 228 * hardware state readout. 229 */ 230 void (*get_power_domains)(struct intel_encoder *encoder, 231 struct intel_crtc_state *crtc_state); 232 /* 233 * Called during system suspend after all pending requests for the 234 * encoder are flushed (for example for DP AUX transactions) and 235 * device interrupts are disabled. 236 */ 237 void (*suspend)(struct intel_encoder *); 238 /* 239 * Called during system reboot/shutdown after all the 240 * encoders have been disabled and suspended. 241 */ 242 void (*shutdown)(struct intel_encoder *encoder); 243 /* 244 * Enable/disable the clock to the port. 245 */ 246 void (*enable_clock)(struct intel_encoder *encoder, 247 const struct intel_crtc_state *crtc_state); 248 void (*disable_clock)(struct intel_encoder *encoder); 249 /* 250 * Returns whether the port clock is enabled or not. 251 */ 252 bool (*is_clock_enabled)(struct intel_encoder *encoder); 253 /* 254 * Returns the PLL type the port uses. 255 */ 256 enum icl_port_dpll_id (*port_pll_type)(struct intel_encoder *encoder, 257 const struct intel_crtc_state *crtc_state); 258 const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder, 259 const struct intel_crtc_state *crtc_state, 260 int *n_entries); 261 void (*set_signal_levels)(struct intel_encoder *encoder, 262 const struct intel_crtc_state *crtc_state); 263 264 enum hpd_pin hpd_pin; 265 enum intel_display_power_domain power_domain; 266 267 /* VBT information for this encoder (may be NULL for older platforms) */ 268 const struct intel_bios_encoder_data *devdata; 269 }; 270 271 struct intel_panel_bl_funcs { 272 /* Connector and platform specific backlight functions */ 273 int (*setup)(struct intel_connector *connector, enum pipe pipe); 274 u32 (*get)(struct intel_connector *connector, enum pipe pipe); 275 void (*set)(const struct drm_connector_state *conn_state, u32 level); 276 void (*disable)(const struct drm_connector_state *conn_state, u32 level); 277 void (*enable)(const struct intel_crtc_state *crtc_state, 278 const struct drm_connector_state *conn_state, u32 level); 279 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz); 280 }; 281 282 enum drrs_type { 283 DRRS_TYPE_NONE, 284 DRRS_TYPE_STATIC, 285 DRRS_TYPE_SEAMLESS, 286 }; 287 288 struct intel_vbt_panel_data { 289 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 290 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 291 292 /* Feature bits */ 293 int panel_type; 294 unsigned int lvds_dither:1; 295 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 296 297 bool vrr; 298 299 u8 seamless_drrs_min_refresh_rate; 300 enum drrs_type drrs_type; 301 302 struct { 303 int max_link_rate; 304 int rate; 305 int lanes; 306 int preemphasis; 307 int vswing; 308 int bpp; 309 struct edp_power_seq pps; 310 u8 drrs_msa_timing_delay; 311 bool low_vswing; 312 bool initialized; 313 bool hobl; 314 } edp; 315 316 struct { 317 bool enable; 318 bool full_link; 319 bool require_aux_wakeup; 320 int idle_frames; 321 int tp1_wakeup_time_us; 322 int tp2_tp3_wakeup_time_us; 323 int psr2_tp2_tp3_wakeup_time_us; 324 } psr; 325 326 struct { 327 u16 pwm_freq_hz; 328 u16 brightness_precision_bits; 329 u16 hdr_dpcd_refresh_timeout; 330 bool present; 331 bool active_low_pwm; 332 u8 min_brightness; /* min_brightness/255 of max */ 333 s8 controller; /* brightness controller number */ 334 enum intel_backlight_type type; 335 } backlight; 336 337 /* MIPI DSI */ 338 struct { 339 u16 panel_id; 340 struct mipi_config *config; 341 struct mipi_pps_data *pps; 342 u16 bl_ports; 343 u16 cabc_ports; 344 u8 seq_version; 345 u32 size; 346 u8 *data; 347 const u8 *sequence[MIPI_SEQ_MAX]; 348 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 349 enum drm_panel_orientation orientation; 350 } dsi; 351 }; 352 353 struct intel_panel { 354 /* Fixed EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 355 const struct drm_edid *fixed_edid; 356 357 struct list_head fixed_modes; 358 359 /* backlight */ 360 struct { 361 bool present; 362 u32 level; 363 u32 min; 364 u32 max; 365 bool enabled; 366 bool combination_mode; /* gen 2/4 only */ 367 bool active_low_pwm; 368 bool alternate_pwm_increment; /* lpt+ */ 369 370 /* PWM chip */ 371 u32 pwm_level_min; 372 u32 pwm_level_max; 373 bool pwm_enabled; 374 bool util_pin_active_low; /* bxt+ */ 375 u8 controller; /* bxt+ only */ 376 struct pwm_device *pwm; 377 struct pwm_state pwm_state; 378 379 /* DPCD backlight */ 380 union { 381 struct { 382 struct drm_edp_backlight_info info; 383 } vesa; 384 struct { 385 bool sdr_uses_aux; 386 } intel; 387 } edp; 388 389 struct backlight_device *device; 390 391 const struct intel_panel_bl_funcs *funcs; 392 const struct intel_panel_bl_funcs *pwm_funcs; 393 void (*power)(struct intel_connector *, bool enable); 394 } backlight; 395 396 struct intel_vbt_panel_data vbt; 397 }; 398 399 struct intel_digital_port; 400 401 enum check_link_response { 402 HDCP_LINK_PROTECTED = 0, 403 HDCP_TOPOLOGY_CHANGE, 404 HDCP_LINK_INTEGRITY_FAILURE, 405 HDCP_REAUTH_REQUEST 406 }; 407 408 /* 409 * This structure serves as a translation layer between the generic HDCP code 410 * and the bus-specific code. What that means is that HDCP over HDMI differs 411 * from HDCP over DP, so to account for these differences, we need to 412 * communicate with the receiver through this shim. 413 * 414 * For completeness, the 2 buses differ in the following ways: 415 * - DP AUX vs. DDC 416 * HDCP registers on the receiver are set via DP AUX for DP, and 417 * they are set via DDC for HDMI. 418 * - Receiver register offsets 419 * The offsets of the registers are different for DP vs. HDMI 420 * - Receiver register masks/offsets 421 * For instance, the ready bit for the KSV fifo is in a different 422 * place on DP vs HDMI 423 * - Receiver register names 424 * Seriously. In the DP spec, the 16-bit register containing 425 * downstream information is called BINFO, on HDMI it's called 426 * BSTATUS. To confuse matters further, DP has a BSTATUS register 427 * with a completely different definition. 428 * - KSV FIFO 429 * On HDMI, the ksv fifo is read all at once, whereas on DP it must 430 * be read 3 keys at a time 431 * - Aksv output 432 * Since Aksv is hidden in hardware, there's different procedures 433 * to send it over DP AUX vs DDC 434 */ 435 struct intel_hdcp_shim { 436 /* Outputs the transmitter's An and Aksv values to the receiver. */ 437 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an); 438 439 /* Reads the receiver's key selection vector */ 440 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv); 441 442 /* 443 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The 444 * definitions are the same in the respective specs, but the names are 445 * different. Call it BSTATUS since that's the name the HDMI spec 446 * uses and it was there first. 447 */ 448 int (*read_bstatus)(struct intel_digital_port *dig_port, 449 u8 *bstatus); 450 451 /* Determines whether a repeater is present downstream */ 452 int (*repeater_present)(struct intel_digital_port *dig_port, 453 bool *repeater_present); 454 455 /* Reads the receiver's Ri' value */ 456 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri); 457 458 /* Determines if the receiver's KSV FIFO is ready for consumption */ 459 int (*read_ksv_ready)(struct intel_digital_port *dig_port, 460 bool *ksv_ready); 461 462 /* Reads the ksv fifo for num_downstream devices */ 463 int (*read_ksv_fifo)(struct intel_digital_port *dig_port, 464 int num_downstream, u8 *ksv_fifo); 465 466 /* Reads a 32-bit part of V' from the receiver */ 467 int (*read_v_prime_part)(struct intel_digital_port *dig_port, 468 int i, u32 *part); 469 470 /* Enables HDCP signalling on the port */ 471 int (*toggle_signalling)(struct intel_digital_port *dig_port, 472 enum transcoder cpu_transcoder, 473 bool enable); 474 475 /* Enable/Disable stream encryption on DP MST Transport Link */ 476 int (*stream_encryption)(struct intel_connector *connector, 477 bool enable); 478 479 /* Ensures the link is still protected */ 480 bool (*check_link)(struct intel_digital_port *dig_port, 481 struct intel_connector *connector); 482 483 /* Detects panel's hdcp capability. This is optional for HDMI. */ 484 int (*hdcp_capable)(struct intel_digital_port *dig_port, 485 bool *hdcp_capable); 486 487 /* HDCP adaptation(DP/HDMI) required on the port */ 488 enum hdcp_wired_protocol protocol; 489 490 /* Detects whether sink is HDCP2.2 capable */ 491 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port, 492 bool *capable); 493 494 /* Write HDCP2.2 messages */ 495 int (*write_2_2_msg)(struct intel_digital_port *dig_port, 496 void *buf, size_t size); 497 498 /* Read HDCP2.2 messages */ 499 int (*read_2_2_msg)(struct intel_digital_port *dig_port, 500 u8 msg_id, void *buf, size_t size); 501 502 /* 503 * Implementation of DP HDCP2.2 Errata for the communication of stream 504 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to 505 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI. 506 */ 507 int (*config_stream_type)(struct intel_digital_port *dig_port, 508 bool is_repeater, u8 type); 509 510 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */ 511 int (*stream_2_2_encryption)(struct intel_connector *connector, 512 bool enable); 513 514 /* HDCP2.2 Link Integrity Check */ 515 int (*check_2_2_link)(struct intel_digital_port *dig_port, 516 struct intel_connector *connector); 517 }; 518 519 struct intel_hdcp { 520 const struct intel_hdcp_shim *shim; 521 /* Mutex for hdcp state of the connector */ 522 struct mutex mutex; 523 u64 value; 524 struct delayed_work check_work; 525 struct work_struct prop_work; 526 527 /* HDCP1.4 Encryption status */ 528 bool hdcp_encrypted; 529 530 /* HDCP2.2 related definitions */ 531 /* Flag indicates whether this connector supports HDCP2.2 or not. */ 532 bool hdcp2_supported; 533 534 /* HDCP2.2 Encryption status */ 535 bool hdcp2_encrypted; 536 537 /* 538 * Content Stream Type defined by content owner. TYPE0(0x0) content can 539 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1) 540 * content can flow only through a link protected by HDCP2.2. 541 */ 542 u8 content_type; 543 544 bool is_paired; 545 bool is_repeater; 546 547 /* 548 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT. 549 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List. 550 * When it rolls over re-auth has to be triggered. 551 */ 552 u32 seq_num_v; 553 554 /* 555 * Count of RepeaterAuth_Stream_Manage msg propagated. 556 * Initialized to 0 on AKE_INIT. Incremented after every successful 557 * transmission of RepeaterAuth_Stream_Manage message. When it rolls 558 * over re-Auth has to be triggered. 559 */ 560 u32 seq_num_m; 561 562 /* 563 * Work queue to signal the CP_IRQ. Used for the waiters to read the 564 * available information from HDCP DP sink. 565 */ 566 wait_queue_head_t cp_irq_queue; 567 atomic_t cp_irq_count; 568 int cp_irq_count_cached; 569 570 /* 571 * HDCP register access for gen12+ need the transcoder associated. 572 * Transcoder attached to the connector could be changed at modeset. 573 * Hence caching the transcoder here. 574 */ 575 enum transcoder cpu_transcoder; 576 /* Only used for DP MST stream encryption */ 577 enum transcoder stream_transcoder; 578 }; 579 580 struct intel_connector { 581 struct drm_connector base; 582 /* 583 * The fixed encoder this connector is connected to. 584 */ 585 struct intel_encoder *encoder; 586 587 /* ACPI device id for ACPI and driver cooperation */ 588 u32 acpi_device_id; 589 590 /* Reads out the current hw, returning true if the connector is enabled 591 * and active (i.e. dpms ON state). */ 592 bool (*get_hw_state)(struct intel_connector *); 593 594 /* Panel info for eDP and LVDS */ 595 struct intel_panel panel; 596 597 /* Cached EDID for detect. */ 598 const struct drm_edid *detect_edid; 599 600 /* Number of times hotplug detection was tried after an HPD interrupt */ 601 int hotplug_retries; 602 603 /* since POLL and HPD connectors may use the same HPD line keep the native 604 state of connector->polled in case hotplug storm detection changes it */ 605 u8 polled; 606 607 struct drm_dp_mst_port *port; 608 609 struct intel_dp *mst_port; 610 611 /* Work struct to schedule a uevent on link train failure */ 612 struct work_struct modeset_retry_work; 613 614 struct intel_hdcp hdcp; 615 }; 616 617 struct intel_digital_connector_state { 618 struct drm_connector_state base; 619 620 enum hdmi_force_audio force_audio; 621 int broadcast_rgb; 622 }; 623 624 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base) 625 626 struct dpll { 627 /* given values */ 628 int n; 629 int m1, m2; 630 int p1, p2; 631 /* derived values */ 632 int dot; 633 int vco; 634 int m; 635 int p; 636 }; 637 638 struct intel_atomic_state { 639 struct drm_atomic_state base; 640 641 intel_wakeref_t wakeref; 642 643 struct __intel_global_objs_state *global_objs; 644 int num_global_objs; 645 646 bool dpll_set, modeset; 647 648 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; 649 650 /* 651 * Current watermarks can't be trusted during hardware readout, so 652 * don't bother calculating intermediate watermarks. 653 */ 654 bool skip_intermediate_wm; 655 656 bool rps_interactive; 657 658 struct i915_sw_fence commit_ready; 659 660 struct llist_node freed; 661 }; 662 663 struct intel_plane_state { 664 struct drm_plane_state uapi; 665 666 /* 667 * actual hardware state, the state we program to the hardware. 668 * The following members are used to verify the hardware state: 669 * During initial hw readout, they need to be copied from uapi. 670 */ 671 struct { 672 struct drm_crtc *crtc; 673 struct drm_framebuffer *fb; 674 675 u16 alpha; 676 u16 pixel_blend_mode; 677 unsigned int rotation; 678 enum drm_color_encoding color_encoding; 679 enum drm_color_range color_range; 680 enum drm_scaling_filter scaling_filter; 681 } hw; 682 683 struct i915_vma *ggtt_vma; 684 struct i915_vma *dpt_vma; 685 unsigned long flags; 686 #define PLANE_HAS_FENCE BIT(0) 687 688 struct intel_fb_view view; 689 690 /* Plane pxp decryption state */ 691 bool decrypt; 692 693 /* Plane state to display black pixels when pxp is borked */ 694 bool force_black; 695 696 /* plane control register */ 697 u32 ctl; 698 699 /* plane color control register */ 700 u32 color_ctl; 701 702 /* chroma upsampler control register */ 703 u32 cus_ctl; 704 705 /* 706 * scaler_id 707 * = -1 : not using a scaler 708 * >= 0 : using a scalers 709 * 710 * plane requiring a scaler: 711 * - During check_plane, its bit is set in 712 * crtc_state->scaler_state.scaler_users by calling helper function 713 * update_scaler_plane. 714 * - scaler_id indicates the scaler it got assigned. 715 * 716 * plane doesn't require a scaler: 717 * - this can happen when scaling is no more required or plane simply 718 * got disabled. 719 * - During check_plane, corresponding bit is reset in 720 * crtc_state->scaler_state.scaler_users by calling helper function 721 * update_scaler_plane. 722 */ 723 int scaler_id; 724 725 /* 726 * planar_linked_plane: 727 * 728 * ICL planar formats require 2 planes that are updated as pairs. 729 * This member is used to make sure the other plane is also updated 730 * when required, and for update_slave() to find the correct 731 * plane_state to pass as argument. 732 */ 733 struct intel_plane *planar_linked_plane; 734 735 /* 736 * planar_slave: 737 * If set don't update use the linked plane's state for updating 738 * this plane during atomic commit with the update_slave() callback. 739 * 740 * It's also used by the watermark code to ignore wm calculations on 741 * this plane. They're calculated by the linked plane's wm code. 742 */ 743 u32 planar_slave; 744 745 struct drm_intel_sprite_colorkey ckey; 746 747 struct drm_rect psr2_sel_fetch_area; 748 749 /* Clear Color Value */ 750 u64 ccval; 751 752 const char *no_fbc_reason; 753 }; 754 755 struct intel_initial_plane_config { 756 struct intel_framebuffer *fb; 757 struct i915_vma *vma; 758 unsigned int tiling; 759 int size; 760 u32 base; 761 u8 rotation; 762 }; 763 764 struct intel_scaler { 765 int in_use; 766 u32 mode; 767 }; 768 769 struct intel_crtc_scaler_state { 770 #define SKL_NUM_SCALERS 2 771 struct intel_scaler scalers[SKL_NUM_SCALERS]; 772 773 /* 774 * scaler_users: keeps track of users requesting scalers on this crtc. 775 * 776 * If a bit is set, a user is using a scaler. 777 * Here user can be a plane or crtc as defined below: 778 * bits 0-30 - plane (bit position is index from drm_plane_index) 779 * bit 31 - crtc 780 * 781 * Instead of creating a new index to cover planes and crtc, using 782 * existing drm_plane_index for planes which is well less than 31 783 * planes and bit 31 for crtc. This should be fine to cover all 784 * our platforms. 785 * 786 * intel_atomic_setup_scalers will setup available scalers to users 787 * requesting scalers. It will gracefully fail if request exceeds 788 * avilability. 789 */ 790 #define SKL_CRTC_INDEX 31 791 unsigned scaler_users; 792 793 /* scaler used by crtc for panel fitting purpose */ 794 int scaler_id; 795 }; 796 797 /* {crtc,crtc_state}->mode_flags */ 798 /* Flag to get scanline using frame time stamps */ 799 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1) 800 /* Flag to use the scanline counter instead of the pixel counter */ 801 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2) 802 /* 803 * TE0 or TE1 flag is set if the crtc has a DSI encoder which 804 * is operating in command mode. 805 * Flag to use TE from DSI0 instead of VBI in command mode 806 */ 807 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3) 808 /* Flag to use TE from DSI1 instead of VBI in command mode */ 809 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4) 810 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */ 811 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5) 812 /* Do tricks to make vblank timestamps sane with VRR? */ 813 #define I915_MODE_FLAG_VRR (1<<6) 814 815 struct intel_wm_level { 816 bool enable; 817 u32 pri_val; 818 u32 spr_val; 819 u32 cur_val; 820 u32 fbc_val; 821 }; 822 823 struct intel_pipe_wm { 824 struct intel_wm_level wm[5]; 825 bool fbc_wm_enabled; 826 bool pipe_enabled; 827 bool sprites_enabled; 828 bool sprites_scaled; 829 }; 830 831 struct skl_wm_level { 832 u16 min_ddb_alloc; 833 u16 blocks; 834 u8 lines; 835 bool enable; 836 bool ignore_lines; 837 bool can_sagv; 838 }; 839 840 struct skl_plane_wm { 841 struct skl_wm_level wm[8]; 842 struct skl_wm_level uv_wm[8]; 843 struct skl_wm_level trans_wm; 844 struct { 845 struct skl_wm_level wm0; 846 struct skl_wm_level trans_wm; 847 } sagv; 848 bool is_planar; 849 }; 850 851 struct skl_pipe_wm { 852 struct skl_plane_wm planes[I915_MAX_PLANES]; 853 bool use_sagv_wm; 854 }; 855 856 enum vlv_wm_level { 857 VLV_WM_LEVEL_PM2, 858 VLV_WM_LEVEL_PM5, 859 VLV_WM_LEVEL_DDR_DVFS, 860 NUM_VLV_WM_LEVELS, 861 }; 862 863 struct vlv_wm_state { 864 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS]; 865 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS]; 866 u8 num_levels; 867 bool cxsr; 868 }; 869 870 struct vlv_fifo_state { 871 u16 plane[I915_MAX_PLANES]; 872 }; 873 874 enum g4x_wm_level { 875 G4X_WM_LEVEL_NORMAL, 876 G4X_WM_LEVEL_SR, 877 G4X_WM_LEVEL_HPLL, 878 NUM_G4X_WM_LEVELS, 879 }; 880 881 struct g4x_wm_state { 882 struct g4x_pipe_wm wm; 883 struct g4x_sr_wm sr; 884 struct g4x_sr_wm hpll; 885 bool cxsr; 886 bool hpll_en; 887 bool fbc_en; 888 }; 889 890 struct intel_crtc_wm_state { 891 union { 892 /* 893 * raw: 894 * The "raw" watermark values produced by the formula 895 * given the plane's current state. They do not consider 896 * how much FIFO is actually allocated for each plane. 897 * 898 * optimal: 899 * The "optimal" watermark values given the current 900 * state of the planes and the amount of FIFO 901 * allocated to each, ignoring any previous state 902 * of the planes. 903 * 904 * intermediate: 905 * The "intermediate" watermark values when transitioning 906 * between the old and new "optimal" values. Used when 907 * the watermark registers are single buffered and hence 908 * their state changes asynchronously with regards to the 909 * actual plane registers. These are essentially the 910 * worst case combination of the old and new "optimal" 911 * watermarks, which are therefore safe to use when the 912 * plane is in either its old or new state. 913 */ 914 struct { 915 struct intel_pipe_wm intermediate; 916 struct intel_pipe_wm optimal; 917 } ilk; 918 919 struct { 920 struct skl_pipe_wm raw; 921 /* gen9+ only needs 1-step wm programming */ 922 struct skl_pipe_wm optimal; 923 struct skl_ddb_entry ddb; 924 /* 925 * pre-icl: for packed/planar CbCr 926 * icl+: for everything 927 */ 928 struct skl_ddb_entry plane_ddb[I915_MAX_PLANES]; 929 /* pre-icl: for planar Y */ 930 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES]; 931 } skl; 932 933 struct { 934 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */ 935 struct vlv_wm_state intermediate; /* inverted */ 936 struct vlv_wm_state optimal; /* inverted */ 937 struct vlv_fifo_state fifo_state; 938 } vlv; 939 940 struct { 941 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS]; 942 struct g4x_wm_state intermediate; 943 struct g4x_wm_state optimal; 944 } g4x; 945 }; 946 947 /* 948 * Platforms with two-step watermark programming will need to 949 * update watermark programming post-vblank to switch from the 950 * safe intermediate watermarks to the optimal final 951 * watermarks. 952 */ 953 bool need_postvbl_update; 954 }; 955 956 enum intel_output_format { 957 INTEL_OUTPUT_FORMAT_RGB, 958 INTEL_OUTPUT_FORMAT_YCBCR420, 959 INTEL_OUTPUT_FORMAT_YCBCR444, 960 }; 961 962 struct intel_mpllb_state { 963 u32 clock; /* in KHz */ 964 u32 ref_control; 965 u32 mpllb_cp; 966 u32 mpllb_div; 967 u32 mpllb_div2; 968 u32 mpllb_fracn1; 969 u32 mpllb_fracn2; 970 u32 mpllb_sscen; 971 u32 mpllb_sscstep; 972 }; 973 974 /* Used by dp and fdi links */ 975 struct intel_link_m_n { 976 u32 tu; 977 u32 data_m; 978 u32 data_n; 979 u32 link_m; 980 u32 link_n; 981 }; 982 983 struct intel_crtc_state { 984 /* 985 * uapi (drm) state. This is the software state shown to userspace. 986 * In particular, the following members are used for bookkeeping: 987 * - crtc 988 * - state 989 * - *_changed 990 * - event 991 * - commit 992 * - mode_blob 993 */ 994 struct drm_crtc_state uapi; 995 996 /* 997 * actual hardware state, the state we program to the hardware. 998 * The following members are used to verify the hardware state: 999 * - enable 1000 * - active 1001 * - mode / pipe_mode / adjusted_mode 1002 * - color property blobs. 1003 * 1004 * During initial hw readout, they need to be copied to uapi. 1005 * 1006 * Bigjoiner will allow a transcoder mode that spans 2 pipes; 1007 * Use the pipe_mode for calculations like watermarks, pipe 1008 * scaler, and bandwidth. 1009 * 1010 * Use adjusted_mode for things that need to know the full 1011 * mode on the transcoder, which spans all pipes. 1012 */ 1013 struct { 1014 bool active, enable; 1015 /* logical state of LUTs */ 1016 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; 1017 struct drm_display_mode mode, pipe_mode, adjusted_mode; 1018 enum drm_scaling_filter scaling_filter; 1019 } hw; 1020 1021 /* actual state of LUTs */ 1022 struct drm_property_blob *pre_csc_lut, *post_csc_lut; 1023 1024 /** 1025 * quirks - bitfield with hw state readout quirks 1026 * 1027 * For various reasons the hw state readout code might not be able to 1028 * completely faithfully read out the current state. These cases are 1029 * tracked with quirk flags so that fastboot and state checker can act 1030 * accordingly. 1031 */ 1032 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ 1033 unsigned long quirks; 1034 1035 unsigned fb_bits; /* framebuffers to flip */ 1036 bool update_pipe; /* can a fast modeset be performed? */ 1037 bool disable_cxsr; 1038 bool update_wm_pre, update_wm_post; /* watermarks are updated */ 1039 bool fifo_changed; /* FIFO split is changed */ 1040 bool preload_luts; 1041 bool inherited; /* state inherited from BIOS? */ 1042 1043 /* Ask the hardware to actually async flip? */ 1044 bool do_async_flip; 1045 1046 /* Pipe source size (ie. panel fitter input size) 1047 * All planes will be positioned inside this space, 1048 * and get clipped at the edges. */ 1049 struct drm_rect pipe_src; 1050 1051 /* 1052 * Pipe pixel rate, adjusted for 1053 * panel fitter/pipe scaler downscaling. 1054 */ 1055 unsigned int pixel_rate; 1056 1057 /* Whether to set up the PCH/FDI. Note that we never allow sharing 1058 * between pch encoders and cpu encoders. */ 1059 bool has_pch_encoder; 1060 1061 /* Are we sending infoframes on the attached port */ 1062 bool has_infoframe; 1063 1064 /* CPU Transcoder for the pipe. Currently this can only differ from the 1065 * pipe on Haswell and later (where we have a special eDP transcoder) 1066 * and Broxton (where we have special DSI transcoders). */ 1067 enum transcoder cpu_transcoder; 1068 1069 /* 1070 * Use reduced/limited/broadcast rbg range, compressing from the full 1071 * range fed into the crtcs. 1072 */ 1073 bool limited_color_range; 1074 1075 /* Bitmask of encoder types (enum intel_output_type) 1076 * driven by the pipe. 1077 */ 1078 unsigned int output_types; 1079 1080 /* Whether we should send NULL infoframes. Required for audio. */ 1081 bool has_hdmi_sink; 1082 1083 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or 1084 * has_dp_encoder is set. */ 1085 bool has_audio; 1086 1087 /* 1088 * Enable dithering, used when the selected pipe bpp doesn't match the 1089 * plane bpp. 1090 */ 1091 bool dither; 1092 1093 /* 1094 * Dither gets enabled for 18bpp which causes CRC mismatch errors for 1095 * compliance video pattern tests. 1096 * Disable dither only if it is a compliance test request for 1097 * 18bpp. 1098 */ 1099 bool dither_force_disable; 1100 1101 /* Controls for the clock computation, to override various stages. */ 1102 bool clock_set; 1103 1104 /* SDVO TV has a bunch of special case. To make multifunction encoders 1105 * work correctly, we need to track this at runtime.*/ 1106 bool sdvo_tv_clock; 1107 1108 /* 1109 * crtc bandwidth limit, don't increase pipe bpp or clock if not really 1110 * required. This is set in the 2nd loop of calling encoder's 1111 * ->compute_config if the first pick doesn't work out. 1112 */ 1113 bool bw_constrained; 1114 1115 /* Settings for the intel dpll used on pretty much everything but 1116 * haswell. */ 1117 struct dpll dpll; 1118 1119 /* Selected dpll when shared or NULL. */ 1120 struct intel_shared_dpll *shared_dpll; 1121 1122 /* Actual register state of the dpll, for shared dpll cross-checking. */ 1123 union { 1124 struct intel_dpll_hw_state dpll_hw_state; 1125 struct intel_mpllb_state mpllb_state; 1126 }; 1127 1128 /* 1129 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by 1130 * setting shared_dpll and dpll_hw_state to one of these reserved ones. 1131 */ 1132 struct icl_port_dpll { 1133 struct intel_shared_dpll *pll; 1134 struct intel_dpll_hw_state hw_state; 1135 } icl_port_dplls[ICL_PORT_DPLL_COUNT]; 1136 1137 /* DSI PLL registers */ 1138 struct { 1139 u32 ctrl, div; 1140 } dsi_pll; 1141 1142 int pipe_bpp; 1143 struct intel_link_m_n dp_m_n; 1144 1145 /* m2_n2 for eDP downclock */ 1146 struct intel_link_m_n dp_m2_n2; 1147 bool has_drrs; 1148 bool seamless_m_n; 1149 1150 /* PSR is supported but might not be enabled due the lack of enabled planes */ 1151 bool has_psr; 1152 bool has_psr2; 1153 bool enable_psr2_sel_fetch; 1154 bool req_psr2_sdp_prior_scanline; 1155 bool wm_level_disabled; 1156 u32 dc3co_exitline; 1157 u16 su_y_granularity; 1158 struct drm_dp_vsc_sdp psr_vsc; 1159 1160 /* 1161 * Frequence the dpll for the port should run at. Differs from the 1162 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also 1163 * already multiplied by pixel_multiplier. 1164 */ 1165 int port_clock; 1166 1167 /* Used by SDVO (and if we ever fix it, HDMI). */ 1168 unsigned pixel_multiplier; 1169 1170 /* I915_MODE_FLAG_* */ 1171 u8 mode_flags; 1172 1173 u8 lane_count; 1174 1175 /* 1176 * Used by platforms having DP/HDMI PHY with programmable lane 1177 * latency optimization. 1178 */ 1179 u8 lane_lat_optim_mask; 1180 1181 /* minimum acceptable voltage level */ 1182 u8 min_voltage_level; 1183 1184 /* Panel fitter controls for gen2-gen4 + VLV */ 1185 struct { 1186 u32 control; 1187 u32 pgm_ratios; 1188 u32 lvds_border_bits; 1189 } gmch_pfit; 1190 1191 /* Panel fitter placement and size for Ironlake+ */ 1192 struct { 1193 struct drm_rect dst; 1194 bool enabled; 1195 bool force_thru; 1196 } pch_pfit; 1197 1198 /* FDI configuration, only valid if has_pch_encoder is set. */ 1199 int fdi_lanes; 1200 struct intel_link_m_n fdi_m_n; 1201 1202 bool ips_enabled; 1203 1204 bool crc_enabled; 1205 1206 bool double_wide; 1207 1208 int pbn; 1209 1210 struct intel_crtc_scaler_state scaler_state; 1211 1212 /* w/a for waiting 2 vblanks during crtc enable */ 1213 enum pipe hsw_workaround_pipe; 1214 1215 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ 1216 bool disable_lp_wm; 1217 1218 struct intel_crtc_wm_state wm; 1219 1220 int min_cdclk[I915_MAX_PLANES]; 1221 1222 /* for packed/planar CbCr */ 1223 u32 data_rate[I915_MAX_PLANES]; 1224 /* for planar Y */ 1225 u32 data_rate_y[I915_MAX_PLANES]; 1226 1227 /* FIXME unify with data_rate[]? */ 1228 u64 rel_data_rate[I915_MAX_PLANES]; 1229 u64 rel_data_rate_y[I915_MAX_PLANES]; 1230 1231 /* Gamma mode programmed on the pipe */ 1232 u32 gamma_mode; 1233 1234 union { 1235 /* CSC mode programmed on the pipe */ 1236 u32 csc_mode; 1237 1238 /* CHV CGM mode */ 1239 u32 cgm_mode; 1240 }; 1241 1242 /* bitmask of logically enabled planes (enum plane_id) */ 1243 u8 enabled_planes; 1244 1245 /* bitmask of actually visible planes (enum plane_id) */ 1246 u8 active_planes; 1247 u8 scaled_planes; 1248 u8 nv12_planes; 1249 u8 c8_planes; 1250 1251 /* bitmask of planes that will be updated during the commit */ 1252 u8 update_planes; 1253 1254 /* bitmask of planes with async flip active */ 1255 u8 async_flip_planes; 1256 1257 u8 framestart_delay; /* 1-4 */ 1258 u8 msa_timing_delay; /* 0-3 */ 1259 1260 struct { 1261 u32 enable; 1262 u32 gcp; 1263 union hdmi_infoframe avi; 1264 union hdmi_infoframe spd; 1265 union hdmi_infoframe hdmi; 1266 union hdmi_infoframe drm; 1267 struct drm_dp_vsc_sdp vsc; 1268 } infoframes; 1269 1270 u8 eld[MAX_ELD_BYTES]; 1271 1272 /* HDMI scrambling status */ 1273 bool hdmi_scrambling; 1274 1275 /* HDMI High TMDS char rate ratio */ 1276 bool hdmi_high_tmds_clock_ratio; 1277 1278 /* Output format RGB/YCBCR etc */ 1279 enum intel_output_format output_format; 1280 1281 /* enable pipe gamma? */ 1282 bool gamma_enable; 1283 1284 /* enable pipe csc? */ 1285 bool csc_enable; 1286 1287 /* big joiner pipe bitmask */ 1288 u8 bigjoiner_pipes; 1289 1290 /* Display Stream compression state */ 1291 struct { 1292 bool compression_enable; 1293 bool dsc_split; 1294 u16 compressed_bpp; 1295 u8 slice_count; 1296 struct drm_dsc_config config; 1297 } dsc; 1298 1299 /* HSW+ linetime watermarks */ 1300 u16 linetime; 1301 u16 ips_linetime; 1302 1303 /* Forward Error correction State */ 1304 bool fec_enable; 1305 1306 bool sdp_split_enable; 1307 1308 /* Pointer to master transcoder in case of tiled displays */ 1309 enum transcoder master_transcoder; 1310 1311 /* Bitmask to indicate slaves attached */ 1312 u8 sync_mode_slaves_mask; 1313 1314 /* Only valid on TGL+ */ 1315 enum transcoder mst_master_transcoder; 1316 1317 /* For DSB related info */ 1318 struct intel_dsb *dsb; 1319 1320 u32 psr2_man_track_ctl; 1321 1322 /* Variable Refresh Rate state */ 1323 struct { 1324 bool enable; 1325 u8 pipeline_full; 1326 u16 flipline, vmin, vmax, guardband; 1327 } vrr; 1328 1329 /* Stream Splitter for eDP MSO */ 1330 struct { 1331 bool enable; 1332 u8 link_count; 1333 u8 pixel_overlap; 1334 } splitter; 1335 1336 /* for loading single buffered registers during vblank */ 1337 struct drm_vblank_work vblank_work; 1338 }; 1339 1340 enum intel_pipe_crc_source { 1341 INTEL_PIPE_CRC_SOURCE_NONE, 1342 INTEL_PIPE_CRC_SOURCE_PLANE1, 1343 INTEL_PIPE_CRC_SOURCE_PLANE2, 1344 INTEL_PIPE_CRC_SOURCE_PLANE3, 1345 INTEL_PIPE_CRC_SOURCE_PLANE4, 1346 INTEL_PIPE_CRC_SOURCE_PLANE5, 1347 INTEL_PIPE_CRC_SOURCE_PLANE6, 1348 INTEL_PIPE_CRC_SOURCE_PLANE7, 1349 INTEL_PIPE_CRC_SOURCE_PIPE, 1350 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1351 INTEL_PIPE_CRC_SOURCE_TV, 1352 INTEL_PIPE_CRC_SOURCE_DP_B, 1353 INTEL_PIPE_CRC_SOURCE_DP_C, 1354 INTEL_PIPE_CRC_SOURCE_DP_D, 1355 INTEL_PIPE_CRC_SOURCE_AUTO, 1356 INTEL_PIPE_CRC_SOURCE_MAX, 1357 }; 1358 1359 enum drrs_refresh_rate { 1360 DRRS_REFRESH_RATE_HIGH, 1361 DRRS_REFRESH_RATE_LOW, 1362 }; 1363 1364 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1365 struct intel_pipe_crc { 1366 spinlock_t lock; 1367 int skipped; 1368 enum intel_pipe_crc_source source; 1369 }; 1370 1371 struct intel_crtc { 1372 struct drm_crtc base; 1373 enum pipe pipe; 1374 /* 1375 * Whether the crtc and the connected output pipeline is active. Implies 1376 * that crtc->enabled is set, i.e. the current mode configuration has 1377 * some outputs connected to this crtc. 1378 */ 1379 bool active; 1380 u8 plane_ids_mask; 1381 1382 /* I915_MODE_FLAG_* */ 1383 u8 mode_flags; 1384 1385 u16 vmax_vblank_start; 1386 1387 struct intel_display_power_domain_set enabled_power_domains; 1388 struct intel_display_power_domain_set hw_readout_power_domains; 1389 struct intel_overlay *overlay; 1390 1391 struct intel_crtc_state *config; 1392 1393 /* Access to these should be protected by dev_priv->irq_lock. */ 1394 bool cpu_fifo_underrun_disabled; 1395 bool pch_fifo_underrun_disabled; 1396 1397 /* per-pipe watermark state */ 1398 struct { 1399 /* watermarks currently being used */ 1400 union { 1401 struct intel_pipe_wm ilk; 1402 struct vlv_wm_state vlv; 1403 struct g4x_wm_state g4x; 1404 } active; 1405 } wm; 1406 1407 struct { 1408 struct mutex mutex; 1409 struct delayed_work work; 1410 enum drrs_refresh_rate refresh_rate; 1411 unsigned int frontbuffer_bits; 1412 unsigned int busy_frontbuffer_bits; 1413 enum transcoder cpu_transcoder; 1414 struct intel_link_m_n m_n, m2_n2; 1415 } drrs; 1416 1417 int scanline_offset; 1418 1419 struct { 1420 unsigned start_vbl_count; 1421 ktime_t start_vbl_time; 1422 int min_vbl, max_vbl; 1423 int scanline_start; 1424 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE 1425 struct { 1426 u64 min; 1427 u64 max; 1428 u64 sum; 1429 unsigned int over; 1430 unsigned int times[17]; /* [1us, 16ms] */ 1431 } vbl; 1432 #endif 1433 } debug; 1434 1435 /* scalers available on this crtc */ 1436 int num_scalers; 1437 1438 /* for loading single buffered registers during vblank */ 1439 struct pm_qos_request vblank_pm_qos; 1440 1441 #ifdef CONFIG_DEBUG_FS 1442 struct intel_pipe_crc pipe_crc; 1443 #endif 1444 }; 1445 1446 struct intel_plane { 1447 struct drm_plane base; 1448 enum i9xx_plane_id i9xx_plane; 1449 enum plane_id id; 1450 enum pipe pipe; 1451 bool need_async_flip_disable_wa; 1452 u32 frontbuffer_bit; 1453 1454 struct { 1455 u32 base, cntl, size; 1456 } cursor; 1457 1458 struct intel_fbc *fbc; 1459 1460 /* 1461 * NOTE: Do not place new plane state fields here (e.g., when adding 1462 * new plane properties). New runtime state should now be placed in 1463 * the intel_plane_state structure and accessed via plane_state. 1464 */ 1465 1466 int (*min_width)(const struct drm_framebuffer *fb, 1467 int color_plane, 1468 unsigned int rotation); 1469 int (*max_width)(const struct drm_framebuffer *fb, 1470 int color_plane, 1471 unsigned int rotation); 1472 int (*max_height)(const struct drm_framebuffer *fb, 1473 int color_plane, 1474 unsigned int rotation); 1475 unsigned int (*max_stride)(struct intel_plane *plane, 1476 u32 pixel_format, u64 modifier, 1477 unsigned int rotation); 1478 /* Write all non-self arming plane registers */ 1479 void (*update_noarm)(struct intel_plane *plane, 1480 const struct intel_crtc_state *crtc_state, 1481 const struct intel_plane_state *plane_state); 1482 /* Write all self-arming plane registers */ 1483 void (*update_arm)(struct intel_plane *plane, 1484 const struct intel_crtc_state *crtc_state, 1485 const struct intel_plane_state *plane_state); 1486 /* Disable the plane, must arm */ 1487 void (*disable_arm)(struct intel_plane *plane, 1488 const struct intel_crtc_state *crtc_state); 1489 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe); 1490 int (*check_plane)(struct intel_crtc_state *crtc_state, 1491 struct intel_plane_state *plane_state); 1492 int (*min_cdclk)(const struct intel_crtc_state *crtc_state, 1493 const struct intel_plane_state *plane_state); 1494 void (*async_flip)(struct intel_plane *plane, 1495 const struct intel_crtc_state *crtc_state, 1496 const struct intel_plane_state *plane_state, 1497 bool async_flip); 1498 void (*enable_flip_done)(struct intel_plane *plane); 1499 void (*disable_flip_done)(struct intel_plane *plane); 1500 }; 1501 1502 struct intel_watermark_params { 1503 u16 fifo_size; 1504 u16 max_wm; 1505 u8 default_wm; 1506 u8 guard_size; 1507 u8 cacheline_size; 1508 }; 1509 1510 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) 1511 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 1512 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi) 1513 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 1514 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 1515 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 1516 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 1517 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi) 1518 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL) 1519 1520 struct intel_hdmi { 1521 i915_reg_t hdmi_reg; 1522 int ddc_bus; 1523 struct { 1524 enum drm_dp_dual_mode_type type; 1525 int max_tmds_clock; 1526 } dp_dual_mode; 1527 bool has_hdmi_sink; 1528 bool has_audio; 1529 struct intel_connector *attached_connector; 1530 struct cec_notifier *cec_notifier; 1531 }; 1532 1533 struct intel_dp_mst_encoder; 1534 1535 struct intel_dp_compliance_data { 1536 unsigned long edid; 1537 u8 video_pattern; 1538 u16 hdisplay, vdisplay; 1539 u8 bpc; 1540 struct drm_dp_phy_test_params phytest; 1541 }; 1542 1543 struct intel_dp_compliance { 1544 unsigned long test_type; 1545 struct intel_dp_compliance_data test_data; 1546 bool test_active; 1547 int test_link_rate; 1548 u8 test_lane_count; 1549 }; 1550 1551 struct intel_dp_pcon_frl { 1552 bool is_trained; 1553 int trained_rate_gbps; 1554 }; 1555 1556 struct intel_pps { 1557 int panel_power_up_delay; 1558 int panel_power_down_delay; 1559 int panel_power_cycle_delay; 1560 int backlight_on_delay; 1561 int backlight_off_delay; 1562 struct delayed_work panel_vdd_work; 1563 bool want_panel_vdd; 1564 bool initializing; 1565 unsigned long last_power_on; 1566 unsigned long last_backlight_off; 1567 ktime_t panel_power_off_time; 1568 intel_wakeref_t vdd_wakeref; 1569 1570 union { 1571 /* 1572 * Pipe whose power sequencer is currently locked into 1573 * this port. Only relevant on VLV/CHV. 1574 */ 1575 enum pipe pps_pipe; 1576 1577 /* 1578 * Power sequencer index. Only relevant on BXT+. 1579 */ 1580 int pps_idx; 1581 }; 1582 1583 /* 1584 * Pipe currently driving the port. Used for preventing 1585 * the use of the PPS for any pipe currentrly driving 1586 * external DP as that will mess things up on VLV. 1587 */ 1588 enum pipe active_pipe; 1589 /* 1590 * Set if the sequencer may be reset due to a power transition, 1591 * requiring a reinitialization. Only relevant on BXT+. 1592 */ 1593 bool pps_reset; 1594 struct edp_power_seq pps_delays; 1595 struct edp_power_seq bios_pps_delays; 1596 }; 1597 1598 struct intel_psr { 1599 /* Mutex for PSR state of the transcoder */ 1600 struct mutex lock; 1601 1602 #define I915_PSR_DEBUG_MODE_MASK 0x0f 1603 #define I915_PSR_DEBUG_DEFAULT 0x00 1604 #define I915_PSR_DEBUG_DISABLE 0x01 1605 #define I915_PSR_DEBUG_ENABLE 0x02 1606 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 1607 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4 1608 #define I915_PSR_DEBUG_IRQ 0x10 1609 1610 u32 debug; 1611 bool sink_support; 1612 bool source_support; 1613 bool enabled; 1614 bool paused; 1615 enum pipe pipe; 1616 enum transcoder transcoder; 1617 bool active; 1618 struct work_struct work; 1619 unsigned int busy_frontbuffer_bits; 1620 bool sink_psr2_support; 1621 bool link_standby; 1622 bool colorimetry_support; 1623 bool psr2_enabled; 1624 bool psr2_sel_fetch_enabled; 1625 bool psr2_sel_fetch_cff_enabled; 1626 bool req_psr2_sdp_prior_scanline; 1627 u8 sink_sync_latency; 1628 u8 io_wake_lines; 1629 u8 fast_wake_lines; 1630 ktime_t last_entry_attempt; 1631 ktime_t last_exit; 1632 bool sink_not_reliable; 1633 bool irq_aux_error; 1634 u16 su_w_granularity; 1635 u16 su_y_granularity; 1636 u32 dc3co_exitline; 1637 u32 dc3co_exit_delay; 1638 struct delayed_work dc3co_work; 1639 }; 1640 1641 struct intel_dp { 1642 i915_reg_t output_reg; 1643 u32 DP; 1644 int link_rate; 1645 u8 lane_count; 1646 u8 sink_count; 1647 bool link_trained; 1648 bool has_hdmi_sink; 1649 bool has_audio; 1650 bool reset_link_params; 1651 bool use_max_params; 1652 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 1653 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 1654 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 1655 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; 1656 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; 1657 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; 1658 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; 1659 u8 fec_capable; 1660 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]; 1661 /* source rates */ 1662 int num_source_rates; 1663 const int *source_rates; 1664 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */ 1665 int num_sink_rates; 1666 int sink_rates[DP_MAX_SUPPORTED_RATES]; 1667 bool use_rate_select; 1668 /* Max sink lane count as reported by DP_MAX_LANE_COUNT */ 1669 int max_sink_lane_count; 1670 /* intersection of source and sink rates */ 1671 int num_common_rates; 1672 int common_rates[DP_MAX_SUPPORTED_RATES]; 1673 /* Max lane count for the current link */ 1674 int max_link_lane_count; 1675 /* Max rate for the current link */ 1676 int max_link_rate; 1677 int mso_link_count; 1678 int mso_pixel_overlap; 1679 /* sink or branch descriptor */ 1680 struct drm_dp_desc desc; 1681 struct drm_dp_aux aux; 1682 u32 aux_busy_last_status; 1683 u8 train_set[4]; 1684 1685 struct intel_pps pps; 1686 1687 bool is_mst; 1688 int active_mst_links; 1689 1690 /* connector directly attached - won't be use for modeset in mst world */ 1691 struct intel_connector *attached_connector; 1692 1693 /* mst connector list */ 1694 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; 1695 struct drm_dp_mst_topology_mgr mst_mgr; 1696 1697 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index); 1698 /* 1699 * This function returns the value we have to program the AUX_CTL 1700 * register with to kick off an AUX transaction. 1701 */ 1702 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes, 1703 u32 aux_clock_divider); 1704 1705 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); 1706 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); 1707 1708 /* This is called before a link training is starterd */ 1709 void (*prepare_link_retrain)(struct intel_dp *intel_dp, 1710 const struct intel_crtc_state *crtc_state); 1711 void (*set_link_train)(struct intel_dp *intel_dp, 1712 const struct intel_crtc_state *crtc_state, 1713 u8 dp_train_pat); 1714 void (*set_idle_link_train)(struct intel_dp *intel_dp, 1715 const struct intel_crtc_state *crtc_state); 1716 1717 u8 (*preemph_max)(struct intel_dp *intel_dp); 1718 u8 (*voltage_max)(struct intel_dp *intel_dp, 1719 const struct intel_crtc_state *crtc_state); 1720 1721 /* Displayport compliance testing */ 1722 struct intel_dp_compliance compliance; 1723 1724 /* Downstream facing port caps */ 1725 struct { 1726 int min_tmds_clock, max_tmds_clock; 1727 int max_dotclock; 1728 int pcon_max_frl_bw; 1729 u8 max_bpc; 1730 bool ycbcr_444_to_420; 1731 bool rgb_to_ycbcr; 1732 } dfp; 1733 1734 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1735 struct pm_qos_request pm_qos; 1736 1737 /* Display stream compression testing */ 1738 bool force_dsc_en; 1739 int force_dsc_output_format; 1740 int force_dsc_bpc; 1741 1742 bool hobl_failed; 1743 bool hobl_active; 1744 1745 struct intel_dp_pcon_frl frl; 1746 1747 struct intel_psr psr; 1748 1749 /* When we last wrote the OUI for eDP */ 1750 unsigned long last_oui_write; 1751 }; 1752 1753 enum lspcon_vendor { 1754 LSPCON_VENDOR_MCA, 1755 LSPCON_VENDOR_PARADE 1756 }; 1757 1758 struct intel_lspcon { 1759 bool active; 1760 bool hdr_supported; 1761 enum drm_lspcon_mode mode; 1762 enum lspcon_vendor vendor; 1763 }; 1764 1765 struct intel_digital_port { 1766 struct intel_encoder base; 1767 u32 saved_port_bits; 1768 struct intel_dp dp; 1769 struct intel_hdmi hdmi; 1770 struct intel_lspcon lspcon; 1771 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); 1772 bool release_cl2_override; 1773 u8 max_lanes; 1774 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */ 1775 enum aux_ch aux_ch; 1776 enum intel_display_power_domain ddi_io_power_domain; 1777 intel_wakeref_t ddi_io_wakeref; 1778 intel_wakeref_t aux_wakeref; 1779 1780 struct intel_tc_port *tc; 1781 1782 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */ 1783 struct mutex hdcp_mutex; 1784 /* the number of pipes using HDCP signalling out of this port */ 1785 unsigned int num_hdcp_streams; 1786 /* port HDCP auth status */ 1787 bool hdcp_auth_status; 1788 /* HDCP port data need to pass to security f/w */ 1789 struct hdcp_port_data hdcp_port_data; 1790 /* Whether the MST topology supports HDCP Type 1 Content */ 1791 bool hdcp_mst_type1_capable; 1792 1793 void (*write_infoframe)(struct intel_encoder *encoder, 1794 const struct intel_crtc_state *crtc_state, 1795 unsigned int type, 1796 const void *frame, ssize_t len); 1797 void (*read_infoframe)(struct intel_encoder *encoder, 1798 const struct intel_crtc_state *crtc_state, 1799 unsigned int type, 1800 void *frame, ssize_t len); 1801 void (*set_infoframes)(struct intel_encoder *encoder, 1802 bool enable, 1803 const struct intel_crtc_state *crtc_state, 1804 const struct drm_connector_state *conn_state); 1805 u32 (*infoframes_enabled)(struct intel_encoder *encoder, 1806 const struct intel_crtc_state *pipe_config); 1807 bool (*connected)(struct intel_encoder *encoder); 1808 }; 1809 1810 struct intel_dp_mst_encoder { 1811 struct intel_encoder base; 1812 enum pipe pipe; 1813 struct intel_digital_port *primary; 1814 struct intel_connector *connector; 1815 }; 1816 1817 struct intel_load_detect_pipe { 1818 struct drm_atomic_state *restore_state; 1819 }; 1820 1821 static inline struct intel_encoder * 1822 intel_attached_encoder(struct intel_connector *connector) 1823 { 1824 return connector->encoder; 1825 } 1826 1827 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder) 1828 { 1829 switch (encoder->type) { 1830 case INTEL_OUTPUT_DDI: 1831 case INTEL_OUTPUT_DP: 1832 case INTEL_OUTPUT_EDP: 1833 case INTEL_OUTPUT_HDMI: 1834 return true; 1835 default: 1836 return false; 1837 } 1838 } 1839 1840 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder) 1841 { 1842 return encoder->type == INTEL_OUTPUT_DP_MST; 1843 } 1844 1845 static inline struct intel_dp_mst_encoder * 1846 enc_to_mst(struct intel_encoder *encoder) 1847 { 1848 return container_of(&encoder->base, struct intel_dp_mst_encoder, 1849 base.base); 1850 } 1851 1852 static inline struct intel_digital_port * 1853 enc_to_dig_port(struct intel_encoder *encoder) 1854 { 1855 struct intel_encoder *intel_encoder = encoder; 1856 1857 if (intel_encoder_is_dig_port(intel_encoder)) 1858 return container_of(&encoder->base, struct intel_digital_port, 1859 base.base); 1860 else if (intel_encoder_is_mst(intel_encoder)) 1861 return enc_to_mst(encoder)->primary; 1862 else 1863 return NULL; 1864 } 1865 1866 static inline struct intel_digital_port * 1867 intel_attached_dig_port(struct intel_connector *connector) 1868 { 1869 return enc_to_dig_port(intel_attached_encoder(connector)); 1870 } 1871 1872 static inline struct intel_hdmi * 1873 enc_to_intel_hdmi(struct intel_encoder *encoder) 1874 { 1875 return &enc_to_dig_port(encoder)->hdmi; 1876 } 1877 1878 static inline struct intel_hdmi * 1879 intel_attached_hdmi(struct intel_connector *connector) 1880 { 1881 return enc_to_intel_hdmi(intel_attached_encoder(connector)); 1882 } 1883 1884 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder) 1885 { 1886 return &enc_to_dig_port(encoder)->dp; 1887 } 1888 1889 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector) 1890 { 1891 return enc_to_intel_dp(intel_attached_encoder(connector)); 1892 } 1893 1894 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) 1895 { 1896 switch (encoder->type) { 1897 case INTEL_OUTPUT_DP: 1898 case INTEL_OUTPUT_EDP: 1899 return true; 1900 case INTEL_OUTPUT_DDI: 1901 /* Skip pure HDMI/DVI DDI encoders */ 1902 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg); 1903 default: 1904 return false; 1905 } 1906 } 1907 1908 static inline struct intel_lspcon * 1909 enc_to_intel_lspcon(struct intel_encoder *encoder) 1910 { 1911 return &enc_to_dig_port(encoder)->lspcon; 1912 } 1913 1914 static inline struct intel_digital_port * 1915 dp_to_dig_port(struct intel_dp *intel_dp) 1916 { 1917 return container_of(intel_dp, struct intel_digital_port, dp); 1918 } 1919 1920 static inline struct intel_lspcon * 1921 dp_to_lspcon(struct intel_dp *intel_dp) 1922 { 1923 return &dp_to_dig_port(intel_dp)->lspcon; 1924 } 1925 1926 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev) 1927 1928 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ 1929 (intel_dp)->psr.source_support) 1930 1931 static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) 1932 { 1933 if (!intel_encoder_is_dp(encoder)) 1934 return false; 1935 1936 return CAN_PSR(enc_to_intel_dp(encoder)); 1937 } 1938 1939 static inline struct intel_digital_port * 1940 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 1941 { 1942 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 1943 } 1944 1945 static inline struct intel_plane_state * 1946 intel_atomic_get_plane_state(struct intel_atomic_state *state, 1947 struct intel_plane *plane) 1948 { 1949 struct drm_plane_state *ret = 1950 drm_atomic_get_plane_state(&state->base, &plane->base); 1951 1952 if (IS_ERR(ret)) 1953 return ERR_CAST(ret); 1954 1955 return to_intel_plane_state(ret); 1956 } 1957 1958 static inline struct intel_plane_state * 1959 intel_atomic_get_old_plane_state(struct intel_atomic_state *state, 1960 struct intel_plane *plane) 1961 { 1962 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base, 1963 &plane->base)); 1964 } 1965 1966 static inline struct intel_plane_state * 1967 intel_atomic_get_new_plane_state(struct intel_atomic_state *state, 1968 struct intel_plane *plane) 1969 { 1970 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base, 1971 &plane->base)); 1972 } 1973 1974 static inline struct intel_crtc_state * 1975 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state, 1976 struct intel_crtc *crtc) 1977 { 1978 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base, 1979 &crtc->base)); 1980 } 1981 1982 static inline struct intel_crtc_state * 1983 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state, 1984 struct intel_crtc *crtc) 1985 { 1986 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, 1987 &crtc->base)); 1988 } 1989 1990 static inline struct intel_digital_connector_state * 1991 intel_atomic_get_new_connector_state(struct intel_atomic_state *state, 1992 struct intel_connector *connector) 1993 { 1994 return to_intel_digital_connector_state( 1995 drm_atomic_get_new_connector_state(&state->base, 1996 &connector->base)); 1997 } 1998 1999 static inline struct intel_digital_connector_state * 2000 intel_atomic_get_old_connector_state(struct intel_atomic_state *state, 2001 struct intel_connector *connector) 2002 { 2003 return to_intel_digital_connector_state( 2004 drm_atomic_get_old_connector_state(&state->base, 2005 &connector->base)); 2006 } 2007 2008 /* intel_display.c */ 2009 static inline bool 2010 intel_crtc_has_type(const struct intel_crtc_state *crtc_state, 2011 enum intel_output_type type) 2012 { 2013 return crtc_state->output_types & BIT(type); 2014 } 2015 2016 static inline bool 2017 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) 2018 { 2019 return crtc_state->output_types & 2020 (BIT(INTEL_OUTPUT_DP) | 2021 BIT(INTEL_OUTPUT_DP_MST) | 2022 BIT(INTEL_OUTPUT_EDP)); 2023 } 2024 2025 static inline bool 2026 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state) 2027 { 2028 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi); 2029 } 2030 2031 static inline bool 2032 intel_crtc_needs_fastset(const struct intel_crtc_state *crtc_state) 2033 { 2034 return crtc_state->update_pipe; 2035 } 2036 2037 static inline bool 2038 intel_crtc_needs_color_update(const struct intel_crtc_state *crtc_state) 2039 { 2040 return crtc_state->uapi.color_mgmt_changed || 2041 intel_crtc_needs_fastset(crtc_state) || 2042 intel_crtc_needs_modeset(crtc_state); 2043 } 2044 2045 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state) 2046 { 2047 return i915_ggtt_offset(plane_state->ggtt_vma); 2048 } 2049 2050 static inline struct intel_frontbuffer * 2051 to_intel_frontbuffer(struct drm_framebuffer *fb) 2052 { 2053 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; 2054 } 2055 2056 #endif /* __INTEL_DISPLAY_TYPES_H__ */ 2057