1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25 26 #ifndef __INTEL_DISPLAY_TYPES_H__ 27 #define __INTEL_DISPLAY_TYPES_H__ 28 29 #include <linux/async.h> 30 #include <linux/i2c.h> 31 #include <linux/pwm.h> 32 #include <linux/sched/clock.h> 33 34 #include <drm/drm_atomic.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_dp_dual_mode_helper.h> 37 #include <drm/drm_dp_mst_helper.h> 38 #include <drm/drm_encoder.h> 39 #include <drm/drm_fb_helper.h> 40 #include <drm/drm_fourcc.h> 41 #include <drm/drm_probe_helper.h> 42 #include <drm/drm_rect.h> 43 #include <drm/drm_vblank.h> 44 #include <drm/i915_mei_hdcp_interface.h> 45 #include <media/cec-notifier.h> 46 47 #include "i915_drv.h" 48 49 struct drm_printer; 50 struct __intel_global_objs_state; 51 52 /* 53 * Display related stuff 54 */ 55 56 /* these are outputs from the chip - integrated only 57 external chips are via DVO or SDVO output */ 58 enum intel_output_type { 59 INTEL_OUTPUT_UNUSED = 0, 60 INTEL_OUTPUT_ANALOG = 1, 61 INTEL_OUTPUT_DVO = 2, 62 INTEL_OUTPUT_SDVO = 3, 63 INTEL_OUTPUT_LVDS = 4, 64 INTEL_OUTPUT_TVOUT = 5, 65 INTEL_OUTPUT_HDMI = 6, 66 INTEL_OUTPUT_DP = 7, 67 INTEL_OUTPUT_EDP = 8, 68 INTEL_OUTPUT_DSI = 9, 69 INTEL_OUTPUT_DDI = 10, 70 INTEL_OUTPUT_DP_MST = 11, 71 }; 72 73 enum hdmi_force_audio { 74 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 75 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 76 HDMI_AUDIO_AUTO, /* trust EDID */ 77 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 78 }; 79 80 /* "Broadcast RGB" property */ 81 enum intel_broadcast_rgb { 82 INTEL_BROADCAST_RGB_AUTO, 83 INTEL_BROADCAST_RGB_FULL, 84 INTEL_BROADCAST_RGB_LIMITED, 85 }; 86 87 struct intel_fb_view { 88 /* 89 * The remap information used in the remapped and rotated views to 90 * create the DMA scatter-gather list for each FB color plane. This sg 91 * list is created along with the view type (gtt.type) specific 92 * i915_vma object and contains the list of FB object pages (reordered 93 * in the rotated view) that are visible in the view. 94 * In the normal view the FB object's backing store sg list is used 95 * directly and hence the remap information here is not used. 96 */ 97 struct i915_ggtt_view gtt; 98 99 /* 100 * The GTT view (gtt.type) specific information for each FB color 101 * plane. In the normal GTT view all formats (up to 4 color planes), 102 * in the rotated and remapped GTT view all no-CCS formats (up to 2 103 * color planes) are supported. 104 * 105 * TODO: add support for CCS formats in the remapped GTT view. 106 * 107 * The view information shared by all FB color planes in the FB, 108 * like dst x/y and src/dst width, is stored separately in 109 * intel_plane_state. 110 */ 111 struct i915_color_plane_view { 112 u32 offset; 113 unsigned int x, y; 114 /* 115 * Plane stride in: 116 * bytes for 0/180 degree rotation 117 * pixels for 90/270 degree rotation 118 */ 119 unsigned int stride; 120 } color_plane[4]; 121 }; 122 123 struct intel_framebuffer { 124 struct drm_framebuffer base; 125 struct intel_frontbuffer *frontbuffer; 126 127 /* Params to remap the FB pages and program the plane registers in each view. */ 128 struct intel_fb_view normal_view; 129 union { 130 struct intel_fb_view rotated_view; 131 struct intel_fb_view remapped_view; 132 }; 133 134 struct i915_address_space *dpt_vm; 135 }; 136 137 struct intel_fbdev { 138 struct drm_fb_helper helper; 139 struct intel_framebuffer *fb; 140 struct i915_vma *vma; 141 unsigned long vma_flags; 142 async_cookie_t cookie; 143 int preferred_bpp; 144 145 /* Whether or not fbdev hpd processing is temporarily suspended */ 146 bool hpd_suspended : 1; 147 /* Set when a hotplug was received while HPD processing was 148 * suspended 149 */ 150 bool hpd_waiting : 1; 151 152 /* Protects hpd_suspended */ 153 struct mutex hpd_lock; 154 }; 155 156 enum intel_hotplug_state { 157 INTEL_HOTPLUG_UNCHANGED, 158 INTEL_HOTPLUG_CHANGED, 159 INTEL_HOTPLUG_RETRY, 160 }; 161 162 struct intel_encoder { 163 struct drm_encoder base; 164 165 enum intel_output_type type; 166 enum port port; 167 u16 cloneable; 168 u8 pipe_mask; 169 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder, 170 struct intel_connector *connector); 171 enum intel_output_type (*compute_output_type)(struct intel_encoder *, 172 struct intel_crtc_state *, 173 struct drm_connector_state *); 174 int (*compute_config)(struct intel_encoder *, 175 struct intel_crtc_state *, 176 struct drm_connector_state *); 177 int (*compute_config_late)(struct intel_encoder *, 178 struct intel_crtc_state *, 179 struct drm_connector_state *); 180 void (*update_prepare)(struct intel_atomic_state *, 181 struct intel_encoder *, 182 struct intel_crtc *); 183 void (*pre_pll_enable)(struct intel_atomic_state *, 184 struct intel_encoder *, 185 const struct intel_crtc_state *, 186 const struct drm_connector_state *); 187 void (*pre_enable)(struct intel_atomic_state *, 188 struct intel_encoder *, 189 const struct intel_crtc_state *, 190 const struct drm_connector_state *); 191 void (*enable)(struct intel_atomic_state *, 192 struct intel_encoder *, 193 const struct intel_crtc_state *, 194 const struct drm_connector_state *); 195 void (*update_complete)(struct intel_atomic_state *, 196 struct intel_encoder *, 197 struct intel_crtc *); 198 void (*disable)(struct intel_atomic_state *, 199 struct intel_encoder *, 200 const struct intel_crtc_state *, 201 const struct drm_connector_state *); 202 void (*post_disable)(struct intel_atomic_state *, 203 struct intel_encoder *, 204 const struct intel_crtc_state *, 205 const struct drm_connector_state *); 206 void (*post_pll_disable)(struct intel_atomic_state *, 207 struct intel_encoder *, 208 const struct intel_crtc_state *, 209 const struct drm_connector_state *); 210 void (*update_pipe)(struct intel_atomic_state *, 211 struct intel_encoder *, 212 const struct intel_crtc_state *, 213 const struct drm_connector_state *); 214 /* Read out the current hw state of this connector, returning true if 215 * the encoder is active. If the encoder is enabled it also set the pipe 216 * it is connected to in the pipe parameter. */ 217 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); 218 /* Reconstructs the equivalent mode flags for the current hardware 219 * state. This must be called _after_ display->get_pipe_config has 220 * pre-filled the pipe config. Note that intel_encoder->base.crtc must 221 * be set correctly before calling this function. */ 222 void (*get_config)(struct intel_encoder *, 223 struct intel_crtc_state *pipe_config); 224 225 /* 226 * Optional hook called during init/resume to sync any state 227 * stored in the encoder (eg. DP link parameters) wrt. the HW state. 228 */ 229 void (*sync_state)(struct intel_encoder *encoder, 230 const struct intel_crtc_state *crtc_state); 231 232 /* 233 * Optional hook, returning true if this encoder allows a fastset 234 * during the initial commit, false otherwise. 235 */ 236 bool (*initial_fastset_check)(struct intel_encoder *encoder, 237 struct intel_crtc_state *crtc_state); 238 239 /* 240 * Acquires the power domains needed for an active encoder during 241 * hardware state readout. 242 */ 243 void (*get_power_domains)(struct intel_encoder *encoder, 244 struct intel_crtc_state *crtc_state); 245 /* 246 * Called during system suspend after all pending requests for the 247 * encoder are flushed (for example for DP AUX transactions) and 248 * device interrupts are disabled. 249 */ 250 void (*suspend)(struct intel_encoder *); 251 /* 252 * Called during system reboot/shutdown after all the 253 * encoders have been disabled and suspended. 254 */ 255 void (*shutdown)(struct intel_encoder *encoder); 256 /* 257 * Enable/disable the clock to the port. 258 */ 259 void (*enable_clock)(struct intel_encoder *encoder, 260 const struct intel_crtc_state *crtc_state); 261 void (*disable_clock)(struct intel_encoder *encoder); 262 /* 263 * Returns whether the port clock is enabled or not. 264 */ 265 bool (*is_clock_enabled)(struct intel_encoder *encoder); 266 enum hpd_pin hpd_pin; 267 enum intel_display_power_domain power_domain; 268 /* for communication with audio component; protected by av_mutex */ 269 const struct drm_connector *audio_connector; 270 271 /* VBT information for this encoder (may be NULL for older platforms) */ 272 const struct intel_bios_encoder_data *devdata; 273 }; 274 275 struct intel_panel_bl_funcs { 276 /* Connector and platform specific backlight functions */ 277 int (*setup)(struct intel_connector *connector, enum pipe pipe); 278 u32 (*get)(struct intel_connector *connector, enum pipe pipe); 279 void (*set)(const struct drm_connector_state *conn_state, u32 level); 280 void (*disable)(const struct drm_connector_state *conn_state, u32 level); 281 void (*enable)(const struct intel_crtc_state *crtc_state, 282 const struct drm_connector_state *conn_state, u32 level); 283 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz); 284 }; 285 286 struct intel_panel { 287 struct drm_display_mode *fixed_mode; 288 struct drm_display_mode *downclock_mode; 289 290 /* backlight */ 291 struct { 292 bool present; 293 u32 level; 294 u32 min; 295 u32 max; 296 bool enabled; 297 bool combination_mode; /* gen 2/4 only */ 298 bool active_low_pwm; 299 bool alternate_pwm_increment; /* lpt+ */ 300 301 /* PWM chip */ 302 u32 pwm_level_min; 303 u32 pwm_level_max; 304 bool pwm_enabled; 305 bool util_pin_active_low; /* bxt+ */ 306 u8 controller; /* bxt+ only */ 307 struct pwm_device *pwm; 308 struct pwm_state pwm_state; 309 310 /* DPCD backlight */ 311 union { 312 struct { 313 struct drm_edp_backlight_info info; 314 } vesa; 315 struct { 316 bool sdr_uses_aux; 317 } intel; 318 } edp; 319 320 struct backlight_device *device; 321 322 const struct intel_panel_bl_funcs *funcs; 323 const struct intel_panel_bl_funcs *pwm_funcs; 324 void (*power)(struct intel_connector *, bool enable); 325 } backlight; 326 }; 327 328 struct intel_digital_port; 329 330 enum check_link_response { 331 HDCP_LINK_PROTECTED = 0, 332 HDCP_TOPOLOGY_CHANGE, 333 HDCP_LINK_INTEGRITY_FAILURE, 334 HDCP_REAUTH_REQUEST 335 }; 336 337 /* 338 * This structure serves as a translation layer between the generic HDCP code 339 * and the bus-specific code. What that means is that HDCP over HDMI differs 340 * from HDCP over DP, so to account for these differences, we need to 341 * communicate with the receiver through this shim. 342 * 343 * For completeness, the 2 buses differ in the following ways: 344 * - DP AUX vs. DDC 345 * HDCP registers on the receiver are set via DP AUX for DP, and 346 * they are set via DDC for HDMI. 347 * - Receiver register offsets 348 * The offsets of the registers are different for DP vs. HDMI 349 * - Receiver register masks/offsets 350 * For instance, the ready bit for the KSV fifo is in a different 351 * place on DP vs HDMI 352 * - Receiver register names 353 * Seriously. In the DP spec, the 16-bit register containing 354 * downstream information is called BINFO, on HDMI it's called 355 * BSTATUS. To confuse matters further, DP has a BSTATUS register 356 * with a completely different definition. 357 * - KSV FIFO 358 * On HDMI, the ksv fifo is read all at once, whereas on DP it must 359 * be read 3 keys at a time 360 * - Aksv output 361 * Since Aksv is hidden in hardware, there's different procedures 362 * to send it over DP AUX vs DDC 363 */ 364 struct intel_hdcp_shim { 365 /* Outputs the transmitter's An and Aksv values to the receiver. */ 366 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an); 367 368 /* Reads the receiver's key selection vector */ 369 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv); 370 371 /* 372 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The 373 * definitions are the same in the respective specs, but the names are 374 * different. Call it BSTATUS since that's the name the HDMI spec 375 * uses and it was there first. 376 */ 377 int (*read_bstatus)(struct intel_digital_port *dig_port, 378 u8 *bstatus); 379 380 /* Determines whether a repeater is present downstream */ 381 int (*repeater_present)(struct intel_digital_port *dig_port, 382 bool *repeater_present); 383 384 /* Reads the receiver's Ri' value */ 385 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri); 386 387 /* Determines if the receiver's KSV FIFO is ready for consumption */ 388 int (*read_ksv_ready)(struct intel_digital_port *dig_port, 389 bool *ksv_ready); 390 391 /* Reads the ksv fifo for num_downstream devices */ 392 int (*read_ksv_fifo)(struct intel_digital_port *dig_port, 393 int num_downstream, u8 *ksv_fifo); 394 395 /* Reads a 32-bit part of V' from the receiver */ 396 int (*read_v_prime_part)(struct intel_digital_port *dig_port, 397 int i, u32 *part); 398 399 /* Enables HDCP signalling on the port */ 400 int (*toggle_signalling)(struct intel_digital_port *dig_port, 401 enum transcoder cpu_transcoder, 402 bool enable); 403 404 /* Enable/Disable stream encryption on DP MST Transport Link */ 405 int (*stream_encryption)(struct intel_connector *connector, 406 bool enable); 407 408 /* Ensures the link is still protected */ 409 bool (*check_link)(struct intel_digital_port *dig_port, 410 struct intel_connector *connector); 411 412 /* Detects panel's hdcp capability. This is optional for HDMI. */ 413 int (*hdcp_capable)(struct intel_digital_port *dig_port, 414 bool *hdcp_capable); 415 416 /* HDCP adaptation(DP/HDMI) required on the port */ 417 enum hdcp_wired_protocol protocol; 418 419 /* Detects whether sink is HDCP2.2 capable */ 420 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port, 421 bool *capable); 422 423 /* Detects whether a HDCP 1.4 sink connected in MST topology */ 424 int (*streams_type1_capable)(struct intel_connector *connector, 425 bool *capable); 426 427 /* Write HDCP2.2 messages */ 428 int (*write_2_2_msg)(struct intel_digital_port *dig_port, 429 void *buf, size_t size); 430 431 /* Read HDCP2.2 messages */ 432 int (*read_2_2_msg)(struct intel_digital_port *dig_port, 433 u8 msg_id, void *buf, size_t size); 434 435 /* 436 * Implementation of DP HDCP2.2 Errata for the communication of stream 437 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to 438 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI. 439 */ 440 int (*config_stream_type)(struct intel_digital_port *dig_port, 441 bool is_repeater, u8 type); 442 443 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */ 444 int (*stream_2_2_encryption)(struct intel_connector *connector, 445 bool enable); 446 447 /* HDCP2.2 Link Integrity Check */ 448 int (*check_2_2_link)(struct intel_digital_port *dig_port, 449 struct intel_connector *connector); 450 }; 451 452 struct intel_hdcp { 453 const struct intel_hdcp_shim *shim; 454 /* Mutex for hdcp state of the connector */ 455 struct mutex mutex; 456 u64 value; 457 struct delayed_work check_work; 458 struct work_struct prop_work; 459 460 /* HDCP1.4 Encryption status */ 461 bool hdcp_encrypted; 462 463 /* HDCP2.2 related definitions */ 464 /* Flag indicates whether this connector supports HDCP2.2 or not. */ 465 bool hdcp2_supported; 466 467 /* HDCP2.2 Encryption status */ 468 bool hdcp2_encrypted; 469 470 /* 471 * Content Stream Type defined by content owner. TYPE0(0x0) content can 472 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1) 473 * content can flow only through a link protected by HDCP2.2. 474 */ 475 u8 content_type; 476 477 bool is_paired; 478 bool is_repeater; 479 480 /* 481 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT. 482 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List. 483 * When it rolls over re-auth has to be triggered. 484 */ 485 u32 seq_num_v; 486 487 /* 488 * Count of RepeaterAuth_Stream_Manage msg propagated. 489 * Initialized to 0 on AKE_INIT. Incremented after every successful 490 * transmission of RepeaterAuth_Stream_Manage message. When it rolls 491 * over re-Auth has to be triggered. 492 */ 493 u32 seq_num_m; 494 495 /* 496 * Work queue to signal the CP_IRQ. Used for the waiters to read the 497 * available information from HDCP DP sink. 498 */ 499 wait_queue_head_t cp_irq_queue; 500 atomic_t cp_irq_count; 501 int cp_irq_count_cached; 502 503 /* 504 * HDCP register access for gen12+ need the transcoder associated. 505 * Transcoder attached to the connector could be changed at modeset. 506 * Hence caching the transcoder here. 507 */ 508 enum transcoder cpu_transcoder; 509 /* Only used for DP MST stream encryption */ 510 enum transcoder stream_transcoder; 511 }; 512 513 struct intel_connector { 514 struct drm_connector base; 515 /* 516 * The fixed encoder this connector is connected to. 517 */ 518 struct intel_encoder *encoder; 519 520 /* ACPI device id for ACPI and driver cooperation */ 521 u32 acpi_device_id; 522 523 /* Reads out the current hw, returning true if the connector is enabled 524 * and active (i.e. dpms ON state). */ 525 bool (*get_hw_state)(struct intel_connector *); 526 527 /* Panel info for eDP and LVDS */ 528 struct intel_panel panel; 529 530 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 531 struct edid *edid; 532 struct edid *detect_edid; 533 534 /* Number of times hotplug detection was tried after an HPD interrupt */ 535 int hotplug_retries; 536 537 /* since POLL and HPD connectors may use the same HPD line keep the native 538 state of connector->polled in case hotplug storm detection changes it */ 539 u8 polled; 540 541 struct drm_dp_mst_port *port; 542 543 struct intel_dp *mst_port; 544 545 /* Work struct to schedule a uevent on link train failure */ 546 struct work_struct modeset_retry_work; 547 548 struct intel_hdcp hdcp; 549 }; 550 551 struct intel_digital_connector_state { 552 struct drm_connector_state base; 553 554 enum hdmi_force_audio force_audio; 555 int broadcast_rgb; 556 }; 557 558 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base) 559 560 struct dpll { 561 /* given values */ 562 int n; 563 int m1, m2; 564 int p1, p2; 565 /* derived values */ 566 int dot; 567 int vco; 568 int m; 569 int p; 570 }; 571 572 struct intel_atomic_state { 573 struct drm_atomic_state base; 574 575 intel_wakeref_t wakeref; 576 577 struct __intel_global_objs_state *global_objs; 578 int num_global_objs; 579 580 bool dpll_set, modeset; 581 582 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; 583 584 /* 585 * Current watermarks can't be trusted during hardware readout, so 586 * don't bother calculating intermediate watermarks. 587 */ 588 bool skip_intermediate_wm; 589 590 bool rps_interactive; 591 592 struct i915_sw_fence commit_ready; 593 594 struct llist_node freed; 595 }; 596 597 struct intel_plane_state { 598 struct drm_plane_state uapi; 599 600 /* 601 * actual hardware state, the state we program to the hardware. 602 * The following members are used to verify the hardware state: 603 * During initial hw readout, they need to be copied from uapi. 604 */ 605 struct { 606 struct drm_crtc *crtc; 607 struct drm_framebuffer *fb; 608 609 u16 alpha; 610 u16 pixel_blend_mode; 611 unsigned int rotation; 612 enum drm_color_encoding color_encoding; 613 enum drm_color_range color_range; 614 enum drm_scaling_filter scaling_filter; 615 } hw; 616 617 struct i915_vma *ggtt_vma; 618 struct i915_vma *dpt_vma; 619 unsigned long flags; 620 #define PLANE_HAS_FENCE BIT(0) 621 622 struct intel_fb_view view; 623 624 /* plane control register */ 625 u32 ctl; 626 627 /* plane color control register */ 628 u32 color_ctl; 629 630 /* chroma upsampler control register */ 631 u32 cus_ctl; 632 633 /* 634 * scaler_id 635 * = -1 : not using a scaler 636 * >= 0 : using a scalers 637 * 638 * plane requiring a scaler: 639 * - During check_plane, its bit is set in 640 * crtc_state->scaler_state.scaler_users by calling helper function 641 * update_scaler_plane. 642 * - scaler_id indicates the scaler it got assigned. 643 * 644 * plane doesn't require a scaler: 645 * - this can happen when scaling is no more required or plane simply 646 * got disabled. 647 * - During check_plane, corresponding bit is reset in 648 * crtc_state->scaler_state.scaler_users by calling helper function 649 * update_scaler_plane. 650 */ 651 int scaler_id; 652 653 /* 654 * planar_linked_plane: 655 * 656 * ICL planar formats require 2 planes that are updated as pairs. 657 * This member is used to make sure the other plane is also updated 658 * when required, and for update_slave() to find the correct 659 * plane_state to pass as argument. 660 */ 661 struct intel_plane *planar_linked_plane; 662 663 /* 664 * planar_slave: 665 * If set don't update use the linked plane's state for updating 666 * this plane during atomic commit with the update_slave() callback. 667 * 668 * It's also used by the watermark code to ignore wm calculations on 669 * this plane. They're calculated by the linked plane's wm code. 670 */ 671 u32 planar_slave; 672 673 struct drm_intel_sprite_colorkey ckey; 674 675 struct drm_rect psr2_sel_fetch_area; 676 677 /* Clear Color Value */ 678 u64 ccval; 679 }; 680 681 struct intel_initial_plane_config { 682 struct intel_framebuffer *fb; 683 struct i915_vma *vma; 684 unsigned int tiling; 685 int size; 686 u32 base; 687 u8 rotation; 688 }; 689 690 struct intel_scaler { 691 int in_use; 692 u32 mode; 693 }; 694 695 struct intel_crtc_scaler_state { 696 #define SKL_NUM_SCALERS 2 697 struct intel_scaler scalers[SKL_NUM_SCALERS]; 698 699 /* 700 * scaler_users: keeps track of users requesting scalers on this crtc. 701 * 702 * If a bit is set, a user is using a scaler. 703 * Here user can be a plane or crtc as defined below: 704 * bits 0-30 - plane (bit position is index from drm_plane_index) 705 * bit 31 - crtc 706 * 707 * Instead of creating a new index to cover planes and crtc, using 708 * existing drm_plane_index for planes which is well less than 31 709 * planes and bit 31 for crtc. This should be fine to cover all 710 * our platforms. 711 * 712 * intel_atomic_setup_scalers will setup available scalers to users 713 * requesting scalers. It will gracefully fail if request exceeds 714 * avilability. 715 */ 716 #define SKL_CRTC_INDEX 31 717 unsigned scaler_users; 718 719 /* scaler used by crtc for panel fitting purpose */ 720 int scaler_id; 721 }; 722 723 /* {crtc,crtc_state}->mode_flags */ 724 /* Flag to get scanline using frame time stamps */ 725 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1) 726 /* Flag to use the scanline counter instead of the pixel counter */ 727 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2) 728 /* 729 * TE0 or TE1 flag is set if the crtc has a DSI encoder which 730 * is operating in command mode. 731 * Flag to use TE from DSI0 instead of VBI in command mode 732 */ 733 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3) 734 /* Flag to use TE from DSI1 instead of VBI in command mode */ 735 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4) 736 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */ 737 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5) 738 /* Do tricks to make vblank timestamps sane with VRR? */ 739 #define I915_MODE_FLAG_VRR (1<<6) 740 741 struct intel_wm_level { 742 bool enable; 743 u32 pri_val; 744 u32 spr_val; 745 u32 cur_val; 746 u32 fbc_val; 747 }; 748 749 struct intel_pipe_wm { 750 struct intel_wm_level wm[5]; 751 bool fbc_wm_enabled; 752 bool pipe_enabled; 753 bool sprites_enabled; 754 bool sprites_scaled; 755 }; 756 757 struct skl_wm_level { 758 u16 min_ddb_alloc; 759 u16 blocks; 760 u8 lines; 761 bool enable; 762 bool ignore_lines; 763 bool can_sagv; 764 }; 765 766 struct skl_plane_wm { 767 struct skl_wm_level wm[8]; 768 struct skl_wm_level uv_wm[8]; 769 struct skl_wm_level trans_wm; 770 struct { 771 struct skl_wm_level wm0; 772 struct skl_wm_level trans_wm; 773 } sagv; 774 bool is_planar; 775 }; 776 777 struct skl_pipe_wm { 778 struct skl_plane_wm planes[I915_MAX_PLANES]; 779 bool use_sagv_wm; 780 }; 781 782 enum vlv_wm_level { 783 VLV_WM_LEVEL_PM2, 784 VLV_WM_LEVEL_PM5, 785 VLV_WM_LEVEL_DDR_DVFS, 786 NUM_VLV_WM_LEVELS, 787 }; 788 789 struct vlv_wm_state { 790 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS]; 791 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS]; 792 u8 num_levels; 793 bool cxsr; 794 }; 795 796 struct vlv_fifo_state { 797 u16 plane[I915_MAX_PLANES]; 798 }; 799 800 enum g4x_wm_level { 801 G4X_WM_LEVEL_NORMAL, 802 G4X_WM_LEVEL_SR, 803 G4X_WM_LEVEL_HPLL, 804 NUM_G4X_WM_LEVELS, 805 }; 806 807 struct g4x_wm_state { 808 struct g4x_pipe_wm wm; 809 struct g4x_sr_wm sr; 810 struct g4x_sr_wm hpll; 811 bool cxsr; 812 bool hpll_en; 813 bool fbc_en; 814 }; 815 816 struct intel_crtc_wm_state { 817 union { 818 /* 819 * raw: 820 * The "raw" watermark values produced by the formula 821 * given the plane's current state. They do not consider 822 * how much FIFO is actually allocated for each plane. 823 * 824 * optimal: 825 * The "optimal" watermark values given the current 826 * state of the planes and the amount of FIFO 827 * allocated to each, ignoring any previous state 828 * of the planes. 829 * 830 * intermediate: 831 * The "intermediate" watermark values when transitioning 832 * between the old and new "optimal" values. Used when 833 * the watermark registers are single buffered and hence 834 * their state changes asynchronously with regards to the 835 * actual plane registers. These are essentially the 836 * worst case combination of the old and new "optimal" 837 * watermarks, which are therefore safe to use when the 838 * plane is in either its old or new state. 839 */ 840 struct { 841 struct intel_pipe_wm intermediate; 842 struct intel_pipe_wm optimal; 843 } ilk; 844 845 struct { 846 struct skl_pipe_wm raw; 847 /* gen9+ only needs 1-step wm programming */ 848 struct skl_pipe_wm optimal; 849 struct skl_ddb_entry ddb; 850 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES]; 851 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES]; 852 } skl; 853 854 struct { 855 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */ 856 struct vlv_wm_state intermediate; /* inverted */ 857 struct vlv_wm_state optimal; /* inverted */ 858 struct vlv_fifo_state fifo_state; 859 } vlv; 860 861 struct { 862 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS]; 863 struct g4x_wm_state intermediate; 864 struct g4x_wm_state optimal; 865 } g4x; 866 }; 867 868 /* 869 * Platforms with two-step watermark programming will need to 870 * update watermark programming post-vblank to switch from the 871 * safe intermediate watermarks to the optimal final 872 * watermarks. 873 */ 874 bool need_postvbl_update; 875 }; 876 877 enum intel_output_format { 878 INTEL_OUTPUT_FORMAT_RGB, 879 INTEL_OUTPUT_FORMAT_YCBCR420, 880 INTEL_OUTPUT_FORMAT_YCBCR444, 881 }; 882 883 struct intel_crtc_state { 884 /* 885 * uapi (drm) state. This is the software state shown to userspace. 886 * In particular, the following members are used for bookkeeping: 887 * - crtc 888 * - state 889 * - *_changed 890 * - event 891 * - commit 892 * - mode_blob 893 */ 894 struct drm_crtc_state uapi; 895 896 /* 897 * actual hardware state, the state we program to the hardware. 898 * The following members are used to verify the hardware state: 899 * - enable 900 * - active 901 * - mode / pipe_mode / adjusted_mode 902 * - color property blobs. 903 * 904 * During initial hw readout, they need to be copied to uapi. 905 * 906 * Bigjoiner will allow a transcoder mode that spans 2 pipes; 907 * Use the pipe_mode for calculations like watermarks, pipe 908 * scaler, and bandwidth. 909 * 910 * Use adjusted_mode for things that need to know the full 911 * mode on the transcoder, which spans all pipes. 912 */ 913 struct { 914 bool active, enable; 915 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; 916 struct drm_display_mode mode, pipe_mode, adjusted_mode; 917 enum drm_scaling_filter scaling_filter; 918 } hw; 919 920 /** 921 * quirks - bitfield with hw state readout quirks 922 * 923 * For various reasons the hw state readout code might not be able to 924 * completely faithfully read out the current state. These cases are 925 * tracked with quirk flags so that fastboot and state checker can act 926 * accordingly. 927 */ 928 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ 929 #define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */ 930 unsigned long quirks; 931 932 unsigned fb_bits; /* framebuffers to flip */ 933 bool update_pipe; /* can a fast modeset be performed? */ 934 bool disable_cxsr; 935 bool update_wm_pre, update_wm_post; /* watermarks are updated */ 936 bool fifo_changed; /* FIFO split is changed */ 937 bool preload_luts; 938 bool inherited; /* state inherited from BIOS? */ 939 940 /* Pipe source size (ie. panel fitter input size) 941 * All planes will be positioned inside this space, 942 * and get clipped at the edges. */ 943 int pipe_src_w, pipe_src_h; 944 945 /* 946 * Pipe pixel rate, adjusted for 947 * panel fitter/pipe scaler downscaling. 948 */ 949 unsigned int pixel_rate; 950 951 /* Whether to set up the PCH/FDI. Note that we never allow sharing 952 * between pch encoders and cpu encoders. */ 953 bool has_pch_encoder; 954 955 /* Are we sending infoframes on the attached port */ 956 bool has_infoframe; 957 958 /* CPU Transcoder for the pipe. Currently this can only differ from the 959 * pipe on Haswell and later (where we have a special eDP transcoder) 960 * and Broxton (where we have special DSI transcoders). */ 961 enum transcoder cpu_transcoder; 962 963 /* 964 * Use reduced/limited/broadcast rbg range, compressing from the full 965 * range fed into the crtcs. 966 */ 967 bool limited_color_range; 968 969 /* Bitmask of encoder types (enum intel_output_type) 970 * driven by the pipe. 971 */ 972 unsigned int output_types; 973 974 /* Whether we should send NULL infoframes. Required for audio. */ 975 bool has_hdmi_sink; 976 977 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or 978 * has_dp_encoder is set. */ 979 bool has_audio; 980 981 /* 982 * Enable dithering, used when the selected pipe bpp doesn't match the 983 * plane bpp. 984 */ 985 bool dither; 986 987 /* 988 * Dither gets enabled for 18bpp which causes CRC mismatch errors for 989 * compliance video pattern tests. 990 * Disable dither only if it is a compliance test request for 991 * 18bpp. 992 */ 993 bool dither_force_disable; 994 995 /* Controls for the clock computation, to override various stages. */ 996 bool clock_set; 997 998 /* SDVO TV has a bunch of special case. To make multifunction encoders 999 * work correctly, we need to track this at runtime.*/ 1000 bool sdvo_tv_clock; 1001 1002 /* 1003 * crtc bandwidth limit, don't increase pipe bpp or clock if not really 1004 * required. This is set in the 2nd loop of calling encoder's 1005 * ->compute_config if the first pick doesn't work out. 1006 */ 1007 bool bw_constrained; 1008 1009 /* Settings for the intel dpll used on pretty much everything but 1010 * haswell. */ 1011 struct dpll dpll; 1012 1013 /* Selected dpll when shared or NULL. */ 1014 struct intel_shared_dpll *shared_dpll; 1015 1016 /* Actual register state of the dpll, for shared dpll cross-checking. */ 1017 struct intel_dpll_hw_state dpll_hw_state; 1018 1019 /* 1020 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by 1021 * setting shared_dpll and dpll_hw_state to one of these reserved ones. 1022 */ 1023 struct icl_port_dpll { 1024 struct intel_shared_dpll *pll; 1025 struct intel_dpll_hw_state hw_state; 1026 } icl_port_dplls[ICL_PORT_DPLL_COUNT]; 1027 1028 /* DSI PLL registers */ 1029 struct { 1030 u32 ctrl, div; 1031 } dsi_pll; 1032 1033 int pipe_bpp; 1034 struct intel_link_m_n dp_m_n; 1035 1036 /* m2_n2 for eDP downclock */ 1037 struct intel_link_m_n dp_m2_n2; 1038 bool has_drrs; 1039 1040 bool has_psr; 1041 bool has_psr2; 1042 bool enable_psr2_sel_fetch; 1043 u32 dc3co_exitline; 1044 1045 /* 1046 * Frequence the dpll for the port should run at. Differs from the 1047 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also 1048 * already multiplied by pixel_multiplier. 1049 */ 1050 int port_clock; 1051 1052 /* Used by SDVO (and if we ever fix it, HDMI). */ 1053 unsigned pixel_multiplier; 1054 1055 /* I915_MODE_FLAG_* */ 1056 u8 mode_flags; 1057 1058 u8 lane_count; 1059 1060 /* 1061 * Used by platforms having DP/HDMI PHY with programmable lane 1062 * latency optimization. 1063 */ 1064 u8 lane_lat_optim_mask; 1065 1066 /* minimum acceptable voltage level */ 1067 u8 min_voltage_level; 1068 1069 /* Panel fitter controls for gen2-gen4 + VLV */ 1070 struct { 1071 u32 control; 1072 u32 pgm_ratios; 1073 u32 lvds_border_bits; 1074 } gmch_pfit; 1075 1076 /* Panel fitter placement and size for Ironlake+ */ 1077 struct { 1078 struct drm_rect dst; 1079 bool enabled; 1080 bool force_thru; 1081 } pch_pfit; 1082 1083 /* FDI configuration, only valid if has_pch_encoder is set. */ 1084 int fdi_lanes; 1085 struct intel_link_m_n fdi_m_n; 1086 1087 bool ips_enabled; 1088 1089 bool crc_enabled; 1090 1091 bool enable_fbc; 1092 1093 bool double_wide; 1094 1095 int pbn; 1096 1097 struct intel_crtc_scaler_state scaler_state; 1098 1099 /* w/a for waiting 2 vblanks during crtc enable */ 1100 enum pipe hsw_workaround_pipe; 1101 1102 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ 1103 bool disable_lp_wm; 1104 1105 struct intel_crtc_wm_state wm; 1106 1107 int min_cdclk[I915_MAX_PLANES]; 1108 1109 u32 data_rate[I915_MAX_PLANES]; 1110 1111 /* FIXME unify with data_rate[] */ 1112 u64 plane_data_rate[I915_MAX_PLANES]; 1113 u64 uv_plane_data_rate[I915_MAX_PLANES]; 1114 1115 /* Gamma mode programmed on the pipe */ 1116 u32 gamma_mode; 1117 1118 union { 1119 /* CSC mode programmed on the pipe */ 1120 u32 csc_mode; 1121 1122 /* CHV CGM mode */ 1123 u32 cgm_mode; 1124 }; 1125 1126 /* bitmask of logically enabled planes (enum plane_id) */ 1127 u8 enabled_planes; 1128 1129 /* bitmask of actually visible planes (enum plane_id) */ 1130 u8 active_planes; 1131 u8 nv12_planes; 1132 u8 c8_planes; 1133 1134 /* bitmask of planes that will be updated during the commit */ 1135 u8 update_planes; 1136 1137 struct { 1138 u32 enable; 1139 u32 gcp; 1140 union hdmi_infoframe avi; 1141 union hdmi_infoframe spd; 1142 union hdmi_infoframe hdmi; 1143 union hdmi_infoframe drm; 1144 struct drm_dp_vsc_sdp vsc; 1145 } infoframes; 1146 1147 /* HDMI scrambling status */ 1148 bool hdmi_scrambling; 1149 1150 /* HDMI High TMDS char rate ratio */ 1151 bool hdmi_high_tmds_clock_ratio; 1152 1153 /* Output format RGB/YCBCR etc */ 1154 enum intel_output_format output_format; 1155 1156 /* enable pipe gamma? */ 1157 bool gamma_enable; 1158 1159 /* enable pipe csc? */ 1160 bool csc_enable; 1161 1162 /* enable pipe big joiner? */ 1163 bool bigjoiner; 1164 1165 /* big joiner slave crtc? */ 1166 bool bigjoiner_slave; 1167 1168 /* linked crtc for bigjoiner, either slave or master */ 1169 struct intel_crtc *bigjoiner_linked_crtc; 1170 1171 /* Display Stream compression state */ 1172 struct { 1173 bool compression_enable; 1174 bool dsc_split; 1175 u16 compressed_bpp; 1176 u8 slice_count; 1177 struct drm_dsc_config config; 1178 } dsc; 1179 1180 /* HSW+ linetime watermarks */ 1181 u16 linetime; 1182 u16 ips_linetime; 1183 1184 /* Forward Error correction State */ 1185 bool fec_enable; 1186 1187 /* Pointer to master transcoder in case of tiled displays */ 1188 enum transcoder master_transcoder; 1189 1190 /* Bitmask to indicate slaves attached */ 1191 u8 sync_mode_slaves_mask; 1192 1193 /* Only valid on TGL+ */ 1194 enum transcoder mst_master_transcoder; 1195 1196 /* For DSB related info */ 1197 struct intel_dsb *dsb; 1198 1199 u32 psr2_man_track_ctl; 1200 1201 /* Variable Refresh Rate state */ 1202 struct { 1203 bool enable; 1204 u8 pipeline_full; 1205 u16 flipline, vmin, vmax, guardband; 1206 } vrr; 1207 1208 /* Stream Splitter for eDP MSO */ 1209 struct { 1210 bool enable; 1211 u8 link_count; 1212 u8 pixel_overlap; 1213 } splitter; 1214 }; 1215 1216 enum intel_pipe_crc_source { 1217 INTEL_PIPE_CRC_SOURCE_NONE, 1218 INTEL_PIPE_CRC_SOURCE_PLANE1, 1219 INTEL_PIPE_CRC_SOURCE_PLANE2, 1220 INTEL_PIPE_CRC_SOURCE_PLANE3, 1221 INTEL_PIPE_CRC_SOURCE_PLANE4, 1222 INTEL_PIPE_CRC_SOURCE_PLANE5, 1223 INTEL_PIPE_CRC_SOURCE_PLANE6, 1224 INTEL_PIPE_CRC_SOURCE_PLANE7, 1225 INTEL_PIPE_CRC_SOURCE_PIPE, 1226 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1227 INTEL_PIPE_CRC_SOURCE_TV, 1228 INTEL_PIPE_CRC_SOURCE_DP_B, 1229 INTEL_PIPE_CRC_SOURCE_DP_C, 1230 INTEL_PIPE_CRC_SOURCE_DP_D, 1231 INTEL_PIPE_CRC_SOURCE_AUTO, 1232 INTEL_PIPE_CRC_SOURCE_MAX, 1233 }; 1234 1235 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1236 struct intel_pipe_crc { 1237 spinlock_t lock; 1238 int skipped; 1239 enum intel_pipe_crc_source source; 1240 }; 1241 1242 struct intel_crtc { 1243 struct drm_crtc base; 1244 enum pipe pipe; 1245 /* 1246 * Whether the crtc and the connected output pipeline is active. Implies 1247 * that crtc->enabled is set, i.e. the current mode configuration has 1248 * some outputs connected to this crtc. 1249 */ 1250 bool active; 1251 u8 plane_ids_mask; 1252 1253 /* I915_MODE_FLAG_* */ 1254 u8 mode_flags; 1255 1256 u16 vmax_vblank_start; 1257 1258 struct intel_display_power_domain_set enabled_power_domains; 1259 struct intel_overlay *overlay; 1260 1261 struct intel_crtc_state *config; 1262 1263 /* Access to these should be protected by dev_priv->irq_lock. */ 1264 bool cpu_fifo_underrun_disabled; 1265 bool pch_fifo_underrun_disabled; 1266 1267 /* per-pipe watermark state */ 1268 struct { 1269 /* watermarks currently being used */ 1270 union { 1271 struct intel_pipe_wm ilk; 1272 struct vlv_wm_state vlv; 1273 struct g4x_wm_state g4x; 1274 } active; 1275 } wm; 1276 1277 int scanline_offset; 1278 1279 struct { 1280 unsigned start_vbl_count; 1281 ktime_t start_vbl_time; 1282 int min_vbl, max_vbl; 1283 int scanline_start; 1284 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE 1285 struct { 1286 u64 min; 1287 u64 max; 1288 u64 sum; 1289 unsigned int over; 1290 unsigned int times[17]; /* [1us, 16ms] */ 1291 } vbl; 1292 #endif 1293 } debug; 1294 1295 /* scalers available on this crtc */ 1296 int num_scalers; 1297 1298 #ifdef CONFIG_DEBUG_FS 1299 struct intel_pipe_crc pipe_crc; 1300 #endif 1301 }; 1302 1303 struct intel_plane { 1304 struct drm_plane base; 1305 enum i9xx_plane_id i9xx_plane; 1306 enum plane_id id; 1307 enum pipe pipe; 1308 bool has_fbc; 1309 bool has_ccs; 1310 bool need_async_flip_disable_wa; 1311 u32 frontbuffer_bit; 1312 1313 struct { 1314 u32 base, cntl, size; 1315 } cursor; 1316 1317 /* 1318 * NOTE: Do not place new plane state fields here (e.g., when adding 1319 * new plane properties). New runtime state should now be placed in 1320 * the intel_plane_state structure and accessed via plane_state. 1321 */ 1322 1323 int (*min_width)(const struct drm_framebuffer *fb, 1324 int color_plane, 1325 unsigned int rotation); 1326 int (*max_width)(const struct drm_framebuffer *fb, 1327 int color_plane, 1328 unsigned int rotation); 1329 int (*max_height)(const struct drm_framebuffer *fb, 1330 int color_plane, 1331 unsigned int rotation); 1332 unsigned int (*max_stride)(struct intel_plane *plane, 1333 u32 pixel_format, u64 modifier, 1334 unsigned int rotation); 1335 void (*update_plane)(struct intel_plane *plane, 1336 const struct intel_crtc_state *crtc_state, 1337 const struct intel_plane_state *plane_state); 1338 void (*disable_plane)(struct intel_plane *plane, 1339 const struct intel_crtc_state *crtc_state); 1340 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe); 1341 int (*check_plane)(struct intel_crtc_state *crtc_state, 1342 struct intel_plane_state *plane_state); 1343 int (*min_cdclk)(const struct intel_crtc_state *crtc_state, 1344 const struct intel_plane_state *plane_state); 1345 void (*async_flip)(struct intel_plane *plane, 1346 const struct intel_crtc_state *crtc_state, 1347 const struct intel_plane_state *plane_state, 1348 bool async_flip); 1349 void (*enable_flip_done)(struct intel_plane *plane); 1350 void (*disable_flip_done)(struct intel_plane *plane); 1351 }; 1352 1353 struct intel_watermark_params { 1354 u16 fifo_size; 1355 u16 max_wm; 1356 u8 default_wm; 1357 u8 guard_size; 1358 u8 cacheline_size; 1359 }; 1360 1361 struct cxsr_latency { 1362 bool is_desktop : 1; 1363 bool is_ddr3 : 1; 1364 u16 fsb_freq; 1365 u16 mem_freq; 1366 u16 display_sr; 1367 u16 display_hpll_disable; 1368 u16 cursor_sr; 1369 u16 cursor_hpll_disable; 1370 }; 1371 1372 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) 1373 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 1374 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi) 1375 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 1376 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 1377 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 1378 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 1379 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi) 1380 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL) 1381 1382 struct intel_hdmi { 1383 i915_reg_t hdmi_reg; 1384 int ddc_bus; 1385 struct { 1386 enum drm_dp_dual_mode_type type; 1387 int max_tmds_clock; 1388 } dp_dual_mode; 1389 bool has_hdmi_sink; 1390 bool has_audio; 1391 struct intel_connector *attached_connector; 1392 struct cec_notifier *cec_notifier; 1393 }; 1394 1395 struct intel_dp_mst_encoder; 1396 /* 1397 * enum link_m_n_set: 1398 * When platform provides two set of M_N registers for dp, we can 1399 * program them and switch between them incase of DRRS. 1400 * But When only one such register is provided, we have to program the 1401 * required divider value on that registers itself based on the DRRS state. 1402 * 1403 * M1_N1 : Program dp_m_n on M1_N1 registers 1404 * dp_m2_n2 on M2_N2 registers (If supported) 1405 * 1406 * M2_N2 : Program dp_m2_n2 on M1_N1 registers 1407 * M2_N2 registers are not supported 1408 */ 1409 1410 enum link_m_n_set { 1411 /* Sets the m1_n1 and m2_n2 */ 1412 M1_N1 = 0, 1413 M2_N2 1414 }; 1415 1416 struct intel_dp_compliance_data { 1417 unsigned long edid; 1418 u8 video_pattern; 1419 u16 hdisplay, vdisplay; 1420 u8 bpc; 1421 struct drm_dp_phy_test_params phytest; 1422 }; 1423 1424 struct intel_dp_compliance { 1425 unsigned long test_type; 1426 struct intel_dp_compliance_data test_data; 1427 bool test_active; 1428 int test_link_rate; 1429 u8 test_lane_count; 1430 }; 1431 1432 struct intel_dp_pcon_frl { 1433 bool is_trained; 1434 int trained_rate_gbps; 1435 }; 1436 1437 struct intel_pps { 1438 int panel_power_up_delay; 1439 int panel_power_down_delay; 1440 int panel_power_cycle_delay; 1441 int backlight_on_delay; 1442 int backlight_off_delay; 1443 struct delayed_work panel_vdd_work; 1444 bool want_panel_vdd; 1445 unsigned long last_power_on; 1446 unsigned long last_backlight_off; 1447 ktime_t panel_power_off_time; 1448 intel_wakeref_t vdd_wakeref; 1449 1450 /* 1451 * Pipe whose power sequencer is currently locked into 1452 * this port. Only relevant on VLV/CHV. 1453 */ 1454 enum pipe pps_pipe; 1455 /* 1456 * Pipe currently driving the port. Used for preventing 1457 * the use of the PPS for any pipe currentrly driving 1458 * external DP as that will mess things up on VLV. 1459 */ 1460 enum pipe active_pipe; 1461 /* 1462 * Set if the sequencer may be reset due to a power transition, 1463 * requiring a reinitialization. Only relevant on BXT. 1464 */ 1465 bool pps_reset; 1466 struct edp_power_seq pps_delays; 1467 }; 1468 1469 struct intel_psr { 1470 /* Mutex for PSR state of the transcoder */ 1471 struct mutex lock; 1472 1473 #define I915_PSR_DEBUG_MODE_MASK 0x0f 1474 #define I915_PSR_DEBUG_DEFAULT 0x00 1475 #define I915_PSR_DEBUG_DISABLE 0x01 1476 #define I915_PSR_DEBUG_ENABLE 0x02 1477 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 1478 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4 1479 #define I915_PSR_DEBUG_IRQ 0x10 1480 1481 u32 debug; 1482 bool sink_support; 1483 bool source_support; 1484 bool enabled; 1485 bool paused; 1486 enum pipe pipe; 1487 enum transcoder transcoder; 1488 bool active; 1489 struct work_struct work; 1490 unsigned int busy_frontbuffer_bits; 1491 bool sink_psr2_support; 1492 bool link_standby; 1493 bool colorimetry_support; 1494 bool psr2_enabled; 1495 bool psr2_sel_fetch_enabled; 1496 u8 sink_sync_latency; 1497 ktime_t last_entry_attempt; 1498 ktime_t last_exit; 1499 bool sink_not_reliable; 1500 bool irq_aux_error; 1501 u16 su_x_granularity; 1502 u32 dc3co_exitline; 1503 u32 dc3co_exit_delay; 1504 struct delayed_work dc3co_work; 1505 struct drm_dp_vsc_sdp vsc; 1506 }; 1507 1508 struct intel_dp { 1509 i915_reg_t output_reg; 1510 u32 DP; 1511 int link_rate; 1512 u8 lane_count; 1513 u8 sink_count; 1514 bool link_trained; 1515 bool has_hdmi_sink; 1516 bool has_audio; 1517 bool reset_link_params; 1518 bool use_max_params; 1519 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 1520 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 1521 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 1522 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; 1523 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; 1524 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; 1525 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; 1526 u8 fec_capable; 1527 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]; 1528 /* source rates */ 1529 int num_source_rates; 1530 const int *source_rates; 1531 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */ 1532 int num_sink_rates; 1533 int sink_rates[DP_MAX_SUPPORTED_RATES]; 1534 bool use_rate_select; 1535 /* intersection of source and sink rates */ 1536 int num_common_rates; 1537 int common_rates[DP_MAX_SUPPORTED_RATES]; 1538 /* Max lane count for the current link */ 1539 int max_link_lane_count; 1540 /* Max rate for the current link */ 1541 int max_link_rate; 1542 int mso_link_count; 1543 int mso_pixel_overlap; 1544 /* sink or branch descriptor */ 1545 struct drm_dp_desc desc; 1546 struct drm_dp_aux aux; 1547 u32 aux_busy_last_status; 1548 u8 train_set[4]; 1549 1550 struct intel_pps pps; 1551 1552 bool can_mst; /* this port supports mst */ 1553 bool is_mst; 1554 int active_mst_links; 1555 1556 /* connector directly attached - won't be use for modeset in mst world */ 1557 struct intel_connector *attached_connector; 1558 1559 /* mst connector list */ 1560 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; 1561 struct drm_dp_mst_topology_mgr mst_mgr; 1562 1563 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index); 1564 /* 1565 * This function returns the value we have to program the AUX_CTL 1566 * register with to kick off an AUX transaction. 1567 */ 1568 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes, 1569 u32 aux_clock_divider); 1570 1571 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); 1572 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); 1573 1574 /* This is called before a link training is starterd */ 1575 void (*prepare_link_retrain)(struct intel_dp *intel_dp, 1576 const struct intel_crtc_state *crtc_state); 1577 void (*set_link_train)(struct intel_dp *intel_dp, 1578 const struct intel_crtc_state *crtc_state, 1579 u8 dp_train_pat); 1580 void (*set_idle_link_train)(struct intel_dp *intel_dp, 1581 const struct intel_crtc_state *crtc_state); 1582 void (*set_signal_levels)(struct intel_dp *intel_dp, 1583 const struct intel_crtc_state *crtc_state); 1584 1585 u8 (*preemph_max)(struct intel_dp *intel_dp); 1586 u8 (*voltage_max)(struct intel_dp *intel_dp, 1587 const struct intel_crtc_state *crtc_state); 1588 1589 /* Displayport compliance testing */ 1590 struct intel_dp_compliance compliance; 1591 1592 /* Downstream facing port caps */ 1593 struct { 1594 int min_tmds_clock, max_tmds_clock; 1595 int max_dotclock; 1596 int pcon_max_frl_bw; 1597 u8 max_bpc; 1598 bool ycbcr_444_to_420; 1599 bool rgb_to_ycbcr; 1600 } dfp; 1601 1602 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1603 struct pm_qos_request pm_qos; 1604 1605 /* Display stream compression testing */ 1606 bool force_dsc_en; 1607 1608 bool hobl_failed; 1609 bool hobl_active; 1610 1611 struct intel_dp_pcon_frl frl; 1612 1613 struct intel_psr psr; 1614 }; 1615 1616 enum lspcon_vendor { 1617 LSPCON_VENDOR_MCA, 1618 LSPCON_VENDOR_PARADE 1619 }; 1620 1621 struct intel_lspcon { 1622 bool active; 1623 bool hdr_supported; 1624 enum drm_lspcon_mode mode; 1625 enum lspcon_vendor vendor; 1626 }; 1627 1628 struct intel_digital_port { 1629 struct intel_encoder base; 1630 u32 saved_port_bits; 1631 struct intel_dp dp; 1632 struct intel_hdmi hdmi; 1633 struct intel_lspcon lspcon; 1634 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); 1635 bool release_cl2_override; 1636 u8 max_lanes; 1637 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */ 1638 enum aux_ch aux_ch; 1639 enum intel_display_power_domain ddi_io_power_domain; 1640 intel_wakeref_t ddi_io_wakeref; 1641 intel_wakeref_t aux_wakeref; 1642 struct mutex tc_lock; /* protects the TypeC port mode */ 1643 intel_wakeref_t tc_lock_wakeref; 1644 int tc_link_refcount; 1645 bool tc_legacy_port:1; 1646 char tc_port_name[8]; 1647 enum tc_port_mode tc_mode; 1648 enum phy_fia tc_phy_fia; 1649 u8 tc_phy_fia_idx; 1650 1651 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */ 1652 struct mutex hdcp_mutex; 1653 /* the number of pipes using HDCP signalling out of this port */ 1654 unsigned int num_hdcp_streams; 1655 /* port HDCP auth status */ 1656 bool hdcp_auth_status; 1657 /* HDCP port data need to pass to security f/w */ 1658 struct hdcp_port_data hdcp_port_data; 1659 1660 void (*write_infoframe)(struct intel_encoder *encoder, 1661 const struct intel_crtc_state *crtc_state, 1662 unsigned int type, 1663 const void *frame, ssize_t len); 1664 void (*read_infoframe)(struct intel_encoder *encoder, 1665 const struct intel_crtc_state *crtc_state, 1666 unsigned int type, 1667 void *frame, ssize_t len); 1668 void (*set_infoframes)(struct intel_encoder *encoder, 1669 bool enable, 1670 const struct intel_crtc_state *crtc_state, 1671 const struct drm_connector_state *conn_state); 1672 u32 (*infoframes_enabled)(struct intel_encoder *encoder, 1673 const struct intel_crtc_state *pipe_config); 1674 bool (*connected)(struct intel_encoder *encoder); 1675 }; 1676 1677 struct intel_dp_mst_encoder { 1678 struct intel_encoder base; 1679 enum pipe pipe; 1680 struct intel_digital_port *primary; 1681 struct intel_connector *connector; 1682 }; 1683 1684 static inline enum dpio_channel 1685 vlv_dig_port_to_channel(struct intel_digital_port *dig_port) 1686 { 1687 switch (dig_port->base.port) { 1688 case PORT_B: 1689 case PORT_D: 1690 return DPIO_CH0; 1691 case PORT_C: 1692 return DPIO_CH1; 1693 default: 1694 BUG(); 1695 } 1696 } 1697 1698 static inline enum dpio_phy 1699 vlv_dig_port_to_phy(struct intel_digital_port *dig_port) 1700 { 1701 switch (dig_port->base.port) { 1702 case PORT_B: 1703 case PORT_C: 1704 return DPIO_PHY0; 1705 case PORT_D: 1706 return DPIO_PHY1; 1707 default: 1708 BUG(); 1709 } 1710 } 1711 1712 static inline enum dpio_channel 1713 vlv_pipe_to_channel(enum pipe pipe) 1714 { 1715 switch (pipe) { 1716 case PIPE_A: 1717 case PIPE_C: 1718 return DPIO_CH0; 1719 case PIPE_B: 1720 return DPIO_CH1; 1721 default: 1722 BUG(); 1723 } 1724 } 1725 1726 static inline struct intel_crtc * 1727 intel_get_first_crtc(struct drm_i915_private *dev_priv) 1728 { 1729 return to_intel_crtc(drm_crtc_from_index(&dev_priv->drm, 0)); 1730 } 1731 1732 static inline struct intel_crtc * 1733 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 1734 { 1735 /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */ 1736 drm_WARN_ON(&dev_priv->drm, 1737 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe))); 1738 return dev_priv->pipe_to_crtc_mapping[pipe]; 1739 } 1740 1741 static inline struct intel_crtc * 1742 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane) 1743 { 1744 return dev_priv->plane_to_crtc_mapping[plane]; 1745 } 1746 1747 struct intel_load_detect_pipe { 1748 struct drm_atomic_state *restore_state; 1749 }; 1750 1751 static inline struct intel_encoder * 1752 intel_attached_encoder(struct intel_connector *connector) 1753 { 1754 return connector->encoder; 1755 } 1756 1757 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder) 1758 { 1759 switch (encoder->type) { 1760 case INTEL_OUTPUT_DDI: 1761 case INTEL_OUTPUT_DP: 1762 case INTEL_OUTPUT_EDP: 1763 case INTEL_OUTPUT_HDMI: 1764 return true; 1765 default: 1766 return false; 1767 } 1768 } 1769 1770 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder) 1771 { 1772 return encoder->type == INTEL_OUTPUT_DP_MST; 1773 } 1774 1775 static inline struct intel_dp_mst_encoder * 1776 enc_to_mst(struct intel_encoder *encoder) 1777 { 1778 return container_of(&encoder->base, struct intel_dp_mst_encoder, 1779 base.base); 1780 } 1781 1782 static inline struct intel_digital_port * 1783 enc_to_dig_port(struct intel_encoder *encoder) 1784 { 1785 struct intel_encoder *intel_encoder = encoder; 1786 1787 if (intel_encoder_is_dig_port(intel_encoder)) 1788 return container_of(&encoder->base, struct intel_digital_port, 1789 base.base); 1790 else if (intel_encoder_is_mst(intel_encoder)) 1791 return enc_to_mst(encoder)->primary; 1792 else 1793 return NULL; 1794 } 1795 1796 static inline struct intel_digital_port * 1797 intel_attached_dig_port(struct intel_connector *connector) 1798 { 1799 return enc_to_dig_port(intel_attached_encoder(connector)); 1800 } 1801 1802 static inline struct intel_hdmi * 1803 enc_to_intel_hdmi(struct intel_encoder *encoder) 1804 { 1805 return &enc_to_dig_port(encoder)->hdmi; 1806 } 1807 1808 static inline struct intel_hdmi * 1809 intel_attached_hdmi(struct intel_connector *connector) 1810 { 1811 return enc_to_intel_hdmi(intel_attached_encoder(connector)); 1812 } 1813 1814 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder) 1815 { 1816 return &enc_to_dig_port(encoder)->dp; 1817 } 1818 1819 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector) 1820 { 1821 return enc_to_intel_dp(intel_attached_encoder(connector)); 1822 } 1823 1824 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) 1825 { 1826 switch (encoder->type) { 1827 case INTEL_OUTPUT_DP: 1828 case INTEL_OUTPUT_EDP: 1829 return true; 1830 case INTEL_OUTPUT_DDI: 1831 /* Skip pure HDMI/DVI DDI encoders */ 1832 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg); 1833 default: 1834 return false; 1835 } 1836 } 1837 1838 static inline struct intel_lspcon * 1839 enc_to_intel_lspcon(struct intel_encoder *encoder) 1840 { 1841 return &enc_to_dig_port(encoder)->lspcon; 1842 } 1843 1844 static inline struct intel_digital_port * 1845 dp_to_dig_port(struct intel_dp *intel_dp) 1846 { 1847 return container_of(intel_dp, struct intel_digital_port, dp); 1848 } 1849 1850 static inline struct intel_lspcon * 1851 dp_to_lspcon(struct intel_dp *intel_dp) 1852 { 1853 return &dp_to_dig_port(intel_dp)->lspcon; 1854 } 1855 1856 static inline struct drm_i915_private * 1857 dp_to_i915(struct intel_dp *intel_dp) 1858 { 1859 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 1860 } 1861 1862 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ 1863 (intel_dp)->psr.source_support) 1864 1865 static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) 1866 { 1867 if (!intel_encoder_is_dp(encoder)) 1868 return false; 1869 1870 return CAN_PSR(enc_to_intel_dp(encoder)); 1871 } 1872 1873 static inline struct intel_digital_port * 1874 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 1875 { 1876 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 1877 } 1878 1879 static inline struct intel_plane_state * 1880 intel_atomic_get_plane_state(struct intel_atomic_state *state, 1881 struct intel_plane *plane) 1882 { 1883 struct drm_plane_state *ret = 1884 drm_atomic_get_plane_state(&state->base, &plane->base); 1885 1886 if (IS_ERR(ret)) 1887 return ERR_CAST(ret); 1888 1889 return to_intel_plane_state(ret); 1890 } 1891 1892 static inline struct intel_plane_state * 1893 intel_atomic_get_old_plane_state(struct intel_atomic_state *state, 1894 struct intel_plane *plane) 1895 { 1896 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base, 1897 &plane->base)); 1898 } 1899 1900 static inline struct intel_plane_state * 1901 intel_atomic_get_new_plane_state(struct intel_atomic_state *state, 1902 struct intel_plane *plane) 1903 { 1904 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base, 1905 &plane->base)); 1906 } 1907 1908 static inline struct intel_crtc_state * 1909 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state, 1910 struct intel_crtc *crtc) 1911 { 1912 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base, 1913 &crtc->base)); 1914 } 1915 1916 static inline struct intel_crtc_state * 1917 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state, 1918 struct intel_crtc *crtc) 1919 { 1920 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, 1921 &crtc->base)); 1922 } 1923 1924 static inline struct intel_digital_connector_state * 1925 intel_atomic_get_new_connector_state(struct intel_atomic_state *state, 1926 struct intel_connector *connector) 1927 { 1928 return to_intel_digital_connector_state( 1929 drm_atomic_get_new_connector_state(&state->base, 1930 &connector->base)); 1931 } 1932 1933 static inline struct intel_digital_connector_state * 1934 intel_atomic_get_old_connector_state(struct intel_atomic_state *state, 1935 struct intel_connector *connector) 1936 { 1937 return to_intel_digital_connector_state( 1938 drm_atomic_get_old_connector_state(&state->base, 1939 &connector->base)); 1940 } 1941 1942 /* intel_display.c */ 1943 static inline bool 1944 intel_crtc_has_type(const struct intel_crtc_state *crtc_state, 1945 enum intel_output_type type) 1946 { 1947 return crtc_state->output_types & (1 << type); 1948 } 1949 static inline bool 1950 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) 1951 { 1952 return crtc_state->output_types & 1953 ((1 << INTEL_OUTPUT_DP) | 1954 (1 << INTEL_OUTPUT_DP_MST) | 1955 (1 << INTEL_OUTPUT_EDP)); 1956 } 1957 1958 static inline bool 1959 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state) 1960 { 1961 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi); 1962 } 1963 1964 static inline void 1965 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) 1966 { 1967 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1968 1969 drm_crtc_wait_one_vblank(&crtc->base); 1970 } 1971 1972 static inline void 1973 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe) 1974 { 1975 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1976 1977 if (crtc->active) 1978 intel_wait_for_vblank(dev_priv, pipe); 1979 } 1980 1981 static inline bool intel_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier) 1982 { 1983 return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR; 1984 } 1985 1986 static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) 1987 { 1988 return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier); 1989 } 1990 1991 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state) 1992 { 1993 return i915_ggtt_offset(plane_state->ggtt_vma); 1994 } 1995 1996 static inline struct intel_frontbuffer * 1997 to_intel_frontbuffer(struct drm_framebuffer *fb) 1998 { 1999 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; 2000 } 2001 2002 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) 2003 { 2004 if (dev_priv->params.panel_use_ssc >= 0) 2005 return dev_priv->params.panel_use_ssc != 0; 2006 return dev_priv->vbt.lvds_use_ssc 2007 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); 2008 } 2009 2010 static inline u32 i9xx_dpll_compute_fp(struct dpll *dpll) 2011 { 2012 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; 2013 } 2014 2015 static inline u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv, 2016 const struct intel_crtc_state *pipe_config) 2017 { 2018 if (HAS_DDI(dev_priv)) 2019 return pipe_config->port_clock; /* SPLL */ 2020 else 2021 return dev_priv->fdi_pll_freq; 2022 } 2023 2024 static inline bool is_ccs_modifier(u64 modifier) 2025 { 2026 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || 2027 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || 2028 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || 2029 modifier == I915_FORMAT_MOD_Y_TILED_CCS || 2030 modifier == I915_FORMAT_MOD_Yf_TILED_CCS; 2031 } 2032 2033 static inline bool is_gen12_ccs_modifier(u64 modifier) 2034 { 2035 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || 2036 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || 2037 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; 2038 } 2039 2040 #endif /* __INTEL_DISPLAY_TYPES_H__ */ 2041