1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25 26 #ifndef __INTEL_DISPLAY_TYPES_H__ 27 #define __INTEL_DISPLAY_TYPES_H__ 28 29 #include <linux/i2c.h> 30 #include <linux/pm_qos.h> 31 #include <linux/pwm.h> 32 #include <linux/sched/clock.h> 33 34 #include <drm/display/drm_dp_dual_mode_helper.h> 35 #include <drm/display/drm_dp_mst_helper.h> 36 #include <drm/display/drm_dsc.h> 37 #include <drm/drm_atomic.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_encoder.h> 40 #include <drm/drm_fourcc.h> 41 #include <drm/drm_framebuffer.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_rect.h> 44 #include <drm/drm_vblank.h> 45 #include <drm/drm_vblank_work.h> 46 #include <drm/i915_hdcp_interface.h> 47 #include <media/cec-notifier.h> 48 49 #include "i915_vma.h" 50 #include "i915_vma_types.h" 51 #include "intel_bios.h" 52 #include "intel_display.h" 53 #include "intel_display_limits.h" 54 #include "intel_display_power.h" 55 #include "intel_dpll_mgr.h" 56 #include "intel_wm_types.h" 57 58 struct drm_printer; 59 struct __intel_global_objs_state; 60 struct intel_ddi_buf_trans; 61 struct intel_fbc; 62 struct intel_connector; 63 struct intel_tc_port; 64 65 /* 66 * Display related stuff 67 */ 68 69 /* these are outputs from the chip - integrated only 70 external chips are via DVO or SDVO output */ 71 enum intel_output_type { 72 INTEL_OUTPUT_UNUSED = 0, 73 INTEL_OUTPUT_ANALOG = 1, 74 INTEL_OUTPUT_DVO = 2, 75 INTEL_OUTPUT_SDVO = 3, 76 INTEL_OUTPUT_LVDS = 4, 77 INTEL_OUTPUT_TVOUT = 5, 78 INTEL_OUTPUT_HDMI = 6, 79 INTEL_OUTPUT_DP = 7, 80 INTEL_OUTPUT_EDP = 8, 81 INTEL_OUTPUT_DSI = 9, 82 INTEL_OUTPUT_DDI = 10, 83 INTEL_OUTPUT_DP_MST = 11, 84 }; 85 86 enum hdmi_force_audio { 87 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 88 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 89 HDMI_AUDIO_AUTO, /* trust EDID */ 90 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 91 }; 92 93 /* "Broadcast RGB" property */ 94 enum intel_broadcast_rgb { 95 INTEL_BROADCAST_RGB_AUTO, 96 INTEL_BROADCAST_RGB_FULL, 97 INTEL_BROADCAST_RGB_LIMITED, 98 }; 99 100 struct intel_fb_view { 101 /* 102 * The remap information used in the remapped and rotated views to 103 * create the DMA scatter-gather list for each FB color plane. This sg 104 * list is created along with the view type (gtt.type) specific 105 * i915_vma object and contains the list of FB object pages (reordered 106 * in the rotated view) that are visible in the view. 107 * In the normal view the FB object's backing store sg list is used 108 * directly and hence the remap information here is not used. 109 */ 110 struct i915_gtt_view gtt; 111 112 /* 113 * The GTT view (gtt.type) specific information for each FB color 114 * plane. In the normal GTT view all formats (up to 4 color planes), 115 * in the rotated and remapped GTT view all no-CCS formats (up to 2 116 * color planes) are supported. 117 * 118 * The view information shared by all FB color planes in the FB, 119 * like dst x/y and src/dst width, is stored separately in 120 * intel_plane_state. 121 */ 122 struct i915_color_plane_view { 123 u32 offset; 124 unsigned int x, y; 125 /* 126 * Plane stride in: 127 * bytes for 0/180 degree rotation 128 * pixels for 90/270 degree rotation 129 */ 130 unsigned int mapping_stride; 131 unsigned int scanout_stride; 132 } color_plane[4]; 133 }; 134 135 struct intel_framebuffer { 136 struct drm_framebuffer base; 137 struct intel_frontbuffer *frontbuffer; 138 139 /* Params to remap the FB pages and program the plane registers in each view. */ 140 struct intel_fb_view normal_view; 141 union { 142 struct intel_fb_view rotated_view; 143 struct intel_fb_view remapped_view; 144 }; 145 146 struct i915_address_space *dpt_vm; 147 }; 148 149 enum intel_hotplug_state { 150 INTEL_HOTPLUG_UNCHANGED, 151 INTEL_HOTPLUG_CHANGED, 152 INTEL_HOTPLUG_RETRY, 153 }; 154 155 struct intel_encoder { 156 struct drm_encoder base; 157 158 enum intel_output_type type; 159 enum port port; 160 u16 cloneable; 161 u8 pipe_mask; 162 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder, 163 struct intel_connector *connector); 164 enum intel_output_type (*compute_output_type)(struct intel_encoder *, 165 struct intel_crtc_state *, 166 struct drm_connector_state *); 167 int (*compute_config)(struct intel_encoder *, 168 struct intel_crtc_state *, 169 struct drm_connector_state *); 170 int (*compute_config_late)(struct intel_encoder *, 171 struct intel_crtc_state *, 172 struct drm_connector_state *); 173 void (*pre_pll_enable)(struct intel_atomic_state *, 174 struct intel_encoder *, 175 const struct intel_crtc_state *, 176 const struct drm_connector_state *); 177 void (*pre_enable)(struct intel_atomic_state *, 178 struct intel_encoder *, 179 const struct intel_crtc_state *, 180 const struct drm_connector_state *); 181 void (*enable)(struct intel_atomic_state *, 182 struct intel_encoder *, 183 const struct intel_crtc_state *, 184 const struct drm_connector_state *); 185 void (*disable)(struct intel_atomic_state *, 186 struct intel_encoder *, 187 const struct intel_crtc_state *, 188 const struct drm_connector_state *); 189 void (*post_disable)(struct intel_atomic_state *, 190 struct intel_encoder *, 191 const struct intel_crtc_state *, 192 const struct drm_connector_state *); 193 void (*post_pll_disable)(struct intel_atomic_state *, 194 struct intel_encoder *, 195 const struct intel_crtc_state *, 196 const struct drm_connector_state *); 197 void (*update_pipe)(struct intel_atomic_state *, 198 struct intel_encoder *, 199 const struct intel_crtc_state *, 200 const struct drm_connector_state *); 201 /* Read out the current hw state of this connector, returning true if 202 * the encoder is active. If the encoder is enabled it also set the pipe 203 * it is connected to in the pipe parameter. */ 204 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); 205 /* Reconstructs the equivalent mode flags for the current hardware 206 * state. This must be called _after_ display->get_pipe_config has 207 * pre-filled the pipe config. Note that intel_encoder->base.crtc must 208 * be set correctly before calling this function. */ 209 void (*get_config)(struct intel_encoder *, 210 struct intel_crtc_state *pipe_config); 211 212 /* 213 * Optional hook called during init/resume to sync any state 214 * stored in the encoder (eg. DP link parameters) wrt. the HW state. 215 */ 216 void (*sync_state)(struct intel_encoder *encoder, 217 const struct intel_crtc_state *crtc_state); 218 219 /* 220 * Optional hook, returning true if this encoder allows a fastset 221 * during the initial commit, false otherwise. 222 */ 223 bool (*initial_fastset_check)(struct intel_encoder *encoder, 224 struct intel_crtc_state *crtc_state); 225 226 /* 227 * Acquires the power domains needed for an active encoder during 228 * hardware state readout. 229 */ 230 void (*get_power_domains)(struct intel_encoder *encoder, 231 struct intel_crtc_state *crtc_state); 232 /* 233 * Called during system suspend after all pending requests for the 234 * encoder are flushed (for example for DP AUX transactions) and 235 * device interrupts are disabled. 236 * All modeset locks are held while the hook is called. 237 */ 238 void (*suspend)(struct intel_encoder *); 239 /* 240 * Called without the modeset locks held after the suspend() hook for 241 * all encoders have been called. 242 */ 243 void (*suspend_complete)(struct intel_encoder *encoder); 244 /* 245 * Called during system reboot/shutdown after all the 246 * encoders have been disabled and suspended. 247 * All modeset locks are held while the hook is called. 248 */ 249 void (*shutdown)(struct intel_encoder *encoder); 250 /* 251 * Called without the modeset locks held after the shutdown() hook for 252 * all encoders have been called. 253 */ 254 void (*shutdown_complete)(struct intel_encoder *encoder); 255 /* 256 * Enable/disable the clock to the port. 257 */ 258 void (*enable_clock)(struct intel_encoder *encoder, 259 const struct intel_crtc_state *crtc_state); 260 void (*disable_clock)(struct intel_encoder *encoder); 261 /* 262 * Returns whether the port clock is enabled or not. 263 */ 264 bool (*is_clock_enabled)(struct intel_encoder *encoder); 265 /* 266 * Returns the PLL type the port uses. 267 */ 268 enum icl_port_dpll_id (*port_pll_type)(struct intel_encoder *encoder, 269 const struct intel_crtc_state *crtc_state); 270 const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder, 271 const struct intel_crtc_state *crtc_state, 272 int *n_entries); 273 void (*set_signal_levels)(struct intel_encoder *encoder, 274 const struct intel_crtc_state *crtc_state); 275 276 enum hpd_pin hpd_pin; 277 enum intel_display_power_domain power_domain; 278 279 /* VBT information for this encoder (may be NULL for older platforms) */ 280 const struct intel_bios_encoder_data *devdata; 281 }; 282 283 struct intel_panel_bl_funcs { 284 /* Connector and platform specific backlight functions */ 285 int (*setup)(struct intel_connector *connector, enum pipe pipe); 286 u32 (*get)(struct intel_connector *connector, enum pipe pipe); 287 void (*set)(const struct drm_connector_state *conn_state, u32 level); 288 void (*disable)(const struct drm_connector_state *conn_state, u32 level); 289 void (*enable)(const struct intel_crtc_state *crtc_state, 290 const struct drm_connector_state *conn_state, u32 level); 291 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz); 292 }; 293 294 enum drrs_type { 295 DRRS_TYPE_NONE, 296 DRRS_TYPE_STATIC, 297 DRRS_TYPE_SEAMLESS, 298 }; 299 300 struct intel_vbt_panel_data { 301 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 302 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 303 304 /* Feature bits */ 305 int panel_type; 306 unsigned int lvds_dither:1; 307 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 308 309 bool vrr; 310 311 u8 seamless_drrs_min_refresh_rate; 312 enum drrs_type drrs_type; 313 314 struct { 315 int max_link_rate; 316 int rate; 317 int lanes; 318 int preemphasis; 319 int vswing; 320 int bpp; 321 struct edp_power_seq pps; 322 u8 drrs_msa_timing_delay; 323 bool low_vswing; 324 bool initialized; 325 bool hobl; 326 } edp; 327 328 struct { 329 bool enable; 330 bool full_link; 331 bool require_aux_wakeup; 332 int idle_frames; 333 int tp1_wakeup_time_us; 334 int tp2_tp3_wakeup_time_us; 335 int psr2_tp2_tp3_wakeup_time_us; 336 } psr; 337 338 struct { 339 u16 pwm_freq_hz; 340 u16 brightness_precision_bits; 341 u16 hdr_dpcd_refresh_timeout; 342 bool present; 343 bool active_low_pwm; 344 u8 min_brightness; /* min_brightness/255 of max */ 345 s8 controller; /* brightness controller number */ 346 enum intel_backlight_type type; 347 } backlight; 348 349 /* MIPI DSI */ 350 struct { 351 u16 panel_id; 352 struct mipi_config *config; 353 struct mipi_pps_data *pps; 354 u16 bl_ports; 355 u16 cabc_ports; 356 u8 seq_version; 357 u32 size; 358 u8 *data; 359 const u8 *sequence[MIPI_SEQ_MAX]; 360 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 361 enum drm_panel_orientation orientation; 362 } dsi; 363 }; 364 365 struct intel_panel { 366 /* Fixed EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 367 const struct drm_edid *fixed_edid; 368 369 struct list_head fixed_modes; 370 371 /* backlight */ 372 struct { 373 bool present; 374 u32 level; 375 u32 min; 376 u32 max; 377 bool enabled; 378 bool combination_mode; /* gen 2/4 only */ 379 bool active_low_pwm; 380 bool alternate_pwm_increment; /* lpt+ */ 381 382 /* PWM chip */ 383 u32 pwm_level_min; 384 u32 pwm_level_max; 385 bool pwm_enabled; 386 bool util_pin_active_low; /* bxt+ */ 387 u8 controller; /* bxt+ only */ 388 struct pwm_device *pwm; 389 struct pwm_state pwm_state; 390 391 /* DPCD backlight */ 392 union { 393 struct { 394 struct drm_edp_backlight_info info; 395 } vesa; 396 struct { 397 bool sdr_uses_aux; 398 } intel; 399 } edp; 400 401 struct backlight_device *device; 402 403 const struct intel_panel_bl_funcs *funcs; 404 const struct intel_panel_bl_funcs *pwm_funcs; 405 void (*power)(struct intel_connector *, bool enable); 406 } backlight; 407 408 struct intel_vbt_panel_data vbt; 409 }; 410 411 struct intel_digital_port; 412 413 enum check_link_response { 414 HDCP_LINK_PROTECTED = 0, 415 HDCP_TOPOLOGY_CHANGE, 416 HDCP_LINK_INTEGRITY_FAILURE, 417 HDCP_REAUTH_REQUEST 418 }; 419 420 /* 421 * This structure serves as a translation layer between the generic HDCP code 422 * and the bus-specific code. What that means is that HDCP over HDMI differs 423 * from HDCP over DP, so to account for these differences, we need to 424 * communicate with the receiver through this shim. 425 * 426 * For completeness, the 2 buses differ in the following ways: 427 * - DP AUX vs. DDC 428 * HDCP registers on the receiver are set via DP AUX for DP, and 429 * they are set via DDC for HDMI. 430 * - Receiver register offsets 431 * The offsets of the registers are different for DP vs. HDMI 432 * - Receiver register masks/offsets 433 * For instance, the ready bit for the KSV fifo is in a different 434 * place on DP vs HDMI 435 * - Receiver register names 436 * Seriously. In the DP spec, the 16-bit register containing 437 * downstream information is called BINFO, on HDMI it's called 438 * BSTATUS. To confuse matters further, DP has a BSTATUS register 439 * with a completely different definition. 440 * - KSV FIFO 441 * On HDMI, the ksv fifo is read all at once, whereas on DP it must 442 * be read 3 keys at a time 443 * - Aksv output 444 * Since Aksv is hidden in hardware, there's different procedures 445 * to send it over DP AUX vs DDC 446 */ 447 struct intel_hdcp_shim { 448 /* Outputs the transmitter's An and Aksv values to the receiver. */ 449 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an); 450 451 /* Reads the receiver's key selection vector */ 452 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv); 453 454 /* 455 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The 456 * definitions are the same in the respective specs, but the names are 457 * different. Call it BSTATUS since that's the name the HDMI spec 458 * uses and it was there first. 459 */ 460 int (*read_bstatus)(struct intel_digital_port *dig_port, 461 u8 *bstatus); 462 463 /* Determines whether a repeater is present downstream */ 464 int (*repeater_present)(struct intel_digital_port *dig_port, 465 bool *repeater_present); 466 467 /* Reads the receiver's Ri' value */ 468 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri); 469 470 /* Determines if the receiver's KSV FIFO is ready for consumption */ 471 int (*read_ksv_ready)(struct intel_digital_port *dig_port, 472 bool *ksv_ready); 473 474 /* Reads the ksv fifo for num_downstream devices */ 475 int (*read_ksv_fifo)(struct intel_digital_port *dig_port, 476 int num_downstream, u8 *ksv_fifo); 477 478 /* Reads a 32-bit part of V' from the receiver */ 479 int (*read_v_prime_part)(struct intel_digital_port *dig_port, 480 int i, u32 *part); 481 482 /* Enables HDCP signalling on the port */ 483 int (*toggle_signalling)(struct intel_digital_port *dig_port, 484 enum transcoder cpu_transcoder, 485 bool enable); 486 487 /* Enable/Disable stream encryption on DP MST Transport Link */ 488 int (*stream_encryption)(struct intel_connector *connector, 489 bool enable); 490 491 /* Ensures the link is still protected */ 492 bool (*check_link)(struct intel_digital_port *dig_port, 493 struct intel_connector *connector); 494 495 /* Detects panel's hdcp capability. This is optional for HDMI. */ 496 int (*hdcp_capable)(struct intel_digital_port *dig_port, 497 bool *hdcp_capable); 498 499 /* HDCP adaptation(DP/HDMI) required on the port */ 500 enum hdcp_wired_protocol protocol; 501 502 /* Detects whether sink is HDCP2.2 capable */ 503 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port, 504 bool *capable); 505 506 /* Write HDCP2.2 messages */ 507 int (*write_2_2_msg)(struct intel_digital_port *dig_port, 508 void *buf, size_t size); 509 510 /* Read HDCP2.2 messages */ 511 int (*read_2_2_msg)(struct intel_digital_port *dig_port, 512 u8 msg_id, void *buf, size_t size); 513 514 /* 515 * Implementation of DP HDCP2.2 Errata for the communication of stream 516 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to 517 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI. 518 */ 519 int (*config_stream_type)(struct intel_digital_port *dig_port, 520 bool is_repeater, u8 type); 521 522 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */ 523 int (*stream_2_2_encryption)(struct intel_connector *connector, 524 bool enable); 525 526 /* HDCP2.2 Link Integrity Check */ 527 int (*check_2_2_link)(struct intel_digital_port *dig_port, 528 struct intel_connector *connector); 529 }; 530 531 struct intel_hdcp { 532 const struct intel_hdcp_shim *shim; 533 /* Mutex for hdcp state of the connector */ 534 struct mutex mutex; 535 u64 value; 536 struct delayed_work check_work; 537 struct work_struct prop_work; 538 539 /* HDCP1.4 Encryption status */ 540 bool hdcp_encrypted; 541 542 /* HDCP2.2 related definitions */ 543 /* Flag indicates whether this connector supports HDCP2.2 or not. */ 544 bool hdcp2_supported; 545 546 /* HDCP2.2 Encryption status */ 547 bool hdcp2_encrypted; 548 549 /* 550 * Content Stream Type defined by content owner. TYPE0(0x0) content can 551 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1) 552 * content can flow only through a link protected by HDCP2.2. 553 */ 554 u8 content_type; 555 556 bool is_paired; 557 bool is_repeater; 558 559 /* 560 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT. 561 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List. 562 * When it rolls over re-auth has to be triggered. 563 */ 564 u32 seq_num_v; 565 566 /* 567 * Count of RepeaterAuth_Stream_Manage msg propagated. 568 * Initialized to 0 on AKE_INIT. Incremented after every successful 569 * transmission of RepeaterAuth_Stream_Manage message. When it rolls 570 * over re-Auth has to be triggered. 571 */ 572 u32 seq_num_m; 573 574 /* 575 * Work queue to signal the CP_IRQ. Used for the waiters to read the 576 * available information from HDCP DP sink. 577 */ 578 wait_queue_head_t cp_irq_queue; 579 atomic_t cp_irq_count; 580 int cp_irq_count_cached; 581 582 /* 583 * HDCP register access for gen12+ need the transcoder associated. 584 * Transcoder attached to the connector could be changed at modeset. 585 * Hence caching the transcoder here. 586 */ 587 enum transcoder cpu_transcoder; 588 /* Only used for DP MST stream encryption */ 589 enum transcoder stream_transcoder; 590 }; 591 592 struct intel_connector { 593 struct drm_connector base; 594 /* 595 * The fixed encoder this connector is connected to. 596 */ 597 struct intel_encoder *encoder; 598 599 /* ACPI device id for ACPI and driver cooperation */ 600 u32 acpi_device_id; 601 602 /* Reads out the current hw, returning true if the connector is enabled 603 * and active (i.e. dpms ON state). */ 604 bool (*get_hw_state)(struct intel_connector *); 605 606 /* Panel info for eDP and LVDS */ 607 struct intel_panel panel; 608 609 /* Cached EDID for detect. */ 610 const struct drm_edid *detect_edid; 611 612 /* Number of times hotplug detection was tried after an HPD interrupt */ 613 int hotplug_retries; 614 615 /* since POLL and HPD connectors may use the same HPD line keep the native 616 state of connector->polled in case hotplug storm detection changes it */ 617 u8 polled; 618 619 struct drm_dp_mst_port *port; 620 621 struct intel_dp *mst_port; 622 623 /* Work struct to schedule a uevent on link train failure */ 624 struct work_struct modeset_retry_work; 625 626 struct intel_hdcp hdcp; 627 }; 628 629 struct intel_digital_connector_state { 630 struct drm_connector_state base; 631 632 enum hdmi_force_audio force_audio; 633 int broadcast_rgb; 634 }; 635 636 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base) 637 638 struct dpll { 639 /* given values */ 640 int n; 641 int m1, m2; 642 int p1, p2; 643 /* derived values */ 644 int dot; 645 int vco; 646 int m; 647 int p; 648 }; 649 650 struct intel_atomic_state { 651 struct drm_atomic_state base; 652 653 intel_wakeref_t wakeref; 654 655 struct __intel_global_objs_state *global_objs; 656 int num_global_objs; 657 658 /* Internal commit, as opposed to userspace/client initiated one */ 659 bool internal; 660 661 bool dpll_set, modeset; 662 663 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; 664 665 /* 666 * Current watermarks can't be trusted during hardware readout, so 667 * don't bother calculating intermediate watermarks. 668 */ 669 bool skip_intermediate_wm; 670 671 bool rps_interactive; 672 673 struct i915_sw_fence commit_ready; 674 675 struct llist_node freed; 676 }; 677 678 struct intel_plane_state { 679 struct drm_plane_state uapi; 680 681 /* 682 * actual hardware state, the state we program to the hardware. 683 * The following members are used to verify the hardware state: 684 * During initial hw readout, they need to be copied from uapi. 685 */ 686 struct { 687 struct drm_crtc *crtc; 688 struct drm_framebuffer *fb; 689 690 u16 alpha; 691 u16 pixel_blend_mode; 692 unsigned int rotation; 693 enum drm_color_encoding color_encoding; 694 enum drm_color_range color_range; 695 enum drm_scaling_filter scaling_filter; 696 } hw; 697 698 struct i915_vma *ggtt_vma; 699 struct i915_vma *dpt_vma; 700 unsigned long flags; 701 #define PLANE_HAS_FENCE BIT(0) 702 703 struct intel_fb_view view; 704 705 /* Plane pxp decryption state */ 706 bool decrypt; 707 708 /* Plane state to display black pixels when pxp is borked */ 709 bool force_black; 710 711 /* plane control register */ 712 u32 ctl; 713 714 /* plane color control register */ 715 u32 color_ctl; 716 717 /* chroma upsampler control register */ 718 u32 cus_ctl; 719 720 /* 721 * scaler_id 722 * = -1 : not using a scaler 723 * >= 0 : using a scalers 724 * 725 * plane requiring a scaler: 726 * - During check_plane, its bit is set in 727 * crtc_state->scaler_state.scaler_users by calling helper function 728 * update_scaler_plane. 729 * - scaler_id indicates the scaler it got assigned. 730 * 731 * plane doesn't require a scaler: 732 * - this can happen when scaling is no more required or plane simply 733 * got disabled. 734 * - During check_plane, corresponding bit is reset in 735 * crtc_state->scaler_state.scaler_users by calling helper function 736 * update_scaler_plane. 737 */ 738 int scaler_id; 739 740 /* 741 * planar_linked_plane: 742 * 743 * ICL planar formats require 2 planes that are updated as pairs. 744 * This member is used to make sure the other plane is also updated 745 * when required, and for update_slave() to find the correct 746 * plane_state to pass as argument. 747 */ 748 struct intel_plane *planar_linked_plane; 749 750 /* 751 * planar_slave: 752 * If set don't update use the linked plane's state for updating 753 * this plane during atomic commit with the update_slave() callback. 754 * 755 * It's also used by the watermark code to ignore wm calculations on 756 * this plane. They're calculated by the linked plane's wm code. 757 */ 758 u32 planar_slave; 759 760 struct drm_intel_sprite_colorkey ckey; 761 762 struct drm_rect psr2_sel_fetch_area; 763 764 /* Clear Color Value */ 765 u64 ccval; 766 767 const char *no_fbc_reason; 768 }; 769 770 struct intel_initial_plane_config { 771 struct intel_framebuffer *fb; 772 struct i915_vma *vma; 773 unsigned int tiling; 774 int size; 775 u32 base; 776 u8 rotation; 777 }; 778 779 struct intel_scaler { 780 int in_use; 781 u32 mode; 782 }; 783 784 struct intel_crtc_scaler_state { 785 #define SKL_NUM_SCALERS 2 786 struct intel_scaler scalers[SKL_NUM_SCALERS]; 787 788 /* 789 * scaler_users: keeps track of users requesting scalers on this crtc. 790 * 791 * If a bit is set, a user is using a scaler. 792 * Here user can be a plane or crtc as defined below: 793 * bits 0-30 - plane (bit position is index from drm_plane_index) 794 * bit 31 - crtc 795 * 796 * Instead of creating a new index to cover planes and crtc, using 797 * existing drm_plane_index for planes which is well less than 31 798 * planes and bit 31 for crtc. This should be fine to cover all 799 * our platforms. 800 * 801 * intel_atomic_setup_scalers will setup available scalers to users 802 * requesting scalers. It will gracefully fail if request exceeds 803 * avilability. 804 */ 805 #define SKL_CRTC_INDEX 31 806 unsigned scaler_users; 807 808 /* scaler used by crtc for panel fitting purpose */ 809 int scaler_id; 810 }; 811 812 /* {crtc,crtc_state}->mode_flags */ 813 /* Flag to get scanline using frame time stamps */ 814 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1) 815 /* Flag to use the scanline counter instead of the pixel counter */ 816 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2) 817 /* 818 * TE0 or TE1 flag is set if the crtc has a DSI encoder which 819 * is operating in command mode. 820 * Flag to use TE from DSI0 instead of VBI in command mode 821 */ 822 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3) 823 /* Flag to use TE from DSI1 instead of VBI in command mode */ 824 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4) 825 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */ 826 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5) 827 /* Do tricks to make vblank timestamps sane with VRR? */ 828 #define I915_MODE_FLAG_VRR (1<<6) 829 830 struct intel_wm_level { 831 bool enable; 832 u32 pri_val; 833 u32 spr_val; 834 u32 cur_val; 835 u32 fbc_val; 836 }; 837 838 struct intel_pipe_wm { 839 struct intel_wm_level wm[5]; 840 bool fbc_wm_enabled; 841 bool pipe_enabled; 842 bool sprites_enabled; 843 bool sprites_scaled; 844 }; 845 846 struct skl_wm_level { 847 u16 min_ddb_alloc; 848 u16 blocks; 849 u8 lines; 850 bool enable; 851 bool ignore_lines; 852 bool can_sagv; 853 }; 854 855 struct skl_plane_wm { 856 struct skl_wm_level wm[8]; 857 struct skl_wm_level uv_wm[8]; 858 struct skl_wm_level trans_wm; 859 struct { 860 struct skl_wm_level wm0; 861 struct skl_wm_level trans_wm; 862 } sagv; 863 bool is_planar; 864 }; 865 866 struct skl_pipe_wm { 867 struct skl_plane_wm planes[I915_MAX_PLANES]; 868 bool use_sagv_wm; 869 }; 870 871 enum vlv_wm_level { 872 VLV_WM_LEVEL_PM2, 873 VLV_WM_LEVEL_PM5, 874 VLV_WM_LEVEL_DDR_DVFS, 875 NUM_VLV_WM_LEVELS, 876 }; 877 878 struct vlv_wm_state { 879 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS]; 880 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS]; 881 u8 num_levels; 882 bool cxsr; 883 }; 884 885 struct vlv_fifo_state { 886 u16 plane[I915_MAX_PLANES]; 887 }; 888 889 enum g4x_wm_level { 890 G4X_WM_LEVEL_NORMAL, 891 G4X_WM_LEVEL_SR, 892 G4X_WM_LEVEL_HPLL, 893 NUM_G4X_WM_LEVELS, 894 }; 895 896 struct g4x_wm_state { 897 struct g4x_pipe_wm wm; 898 struct g4x_sr_wm sr; 899 struct g4x_sr_wm hpll; 900 bool cxsr; 901 bool hpll_en; 902 bool fbc_en; 903 }; 904 905 struct intel_crtc_wm_state { 906 union { 907 /* 908 * raw: 909 * The "raw" watermark values produced by the formula 910 * given the plane's current state. They do not consider 911 * how much FIFO is actually allocated for each plane. 912 * 913 * optimal: 914 * The "optimal" watermark values given the current 915 * state of the planes and the amount of FIFO 916 * allocated to each, ignoring any previous state 917 * of the planes. 918 * 919 * intermediate: 920 * The "intermediate" watermark values when transitioning 921 * between the old and new "optimal" values. Used when 922 * the watermark registers are single buffered and hence 923 * their state changes asynchronously with regards to the 924 * actual plane registers. These are essentially the 925 * worst case combination of the old and new "optimal" 926 * watermarks, which are therefore safe to use when the 927 * plane is in either its old or new state. 928 */ 929 struct { 930 struct intel_pipe_wm intermediate; 931 struct intel_pipe_wm optimal; 932 } ilk; 933 934 struct { 935 struct skl_pipe_wm raw; 936 /* gen9+ only needs 1-step wm programming */ 937 struct skl_pipe_wm optimal; 938 struct skl_ddb_entry ddb; 939 /* 940 * pre-icl: for packed/planar CbCr 941 * icl+: for everything 942 */ 943 struct skl_ddb_entry plane_ddb[I915_MAX_PLANES]; 944 /* pre-icl: for planar Y */ 945 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES]; 946 } skl; 947 948 struct { 949 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */ 950 struct vlv_wm_state intermediate; /* inverted */ 951 struct vlv_wm_state optimal; /* inverted */ 952 struct vlv_fifo_state fifo_state; 953 } vlv; 954 955 struct { 956 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS]; 957 struct g4x_wm_state intermediate; 958 struct g4x_wm_state optimal; 959 } g4x; 960 }; 961 962 /* 963 * Platforms with two-step watermark programming will need to 964 * update watermark programming post-vblank to switch from the 965 * safe intermediate watermarks to the optimal final 966 * watermarks. 967 */ 968 bool need_postvbl_update; 969 }; 970 971 enum intel_output_format { 972 INTEL_OUTPUT_FORMAT_RGB, 973 INTEL_OUTPUT_FORMAT_YCBCR420, 974 INTEL_OUTPUT_FORMAT_YCBCR444, 975 }; 976 977 struct intel_mpllb_state { 978 u32 clock; /* in KHz */ 979 u32 ref_control; 980 u32 mpllb_cp; 981 u32 mpllb_div; 982 u32 mpllb_div2; 983 u32 mpllb_fracn1; 984 u32 mpllb_fracn2; 985 u32 mpllb_sscen; 986 u32 mpllb_sscstep; 987 }; 988 989 /* Used by dp and fdi links */ 990 struct intel_link_m_n { 991 u32 tu; 992 u32 data_m; 993 u32 data_n; 994 u32 link_m; 995 u32 link_n; 996 }; 997 998 struct intel_csc_matrix { 999 u16 coeff[9]; 1000 u16 preoff[3]; 1001 u16 postoff[3]; 1002 }; 1003 1004 struct intel_c10pll_state { 1005 u32 clock; /* in KHz */ 1006 u8 tx; 1007 u8 cmn; 1008 u8 pll[20]; 1009 }; 1010 1011 struct intel_c20pll_state { 1012 u32 link_bit_rate; 1013 u32 clock; /* in kHz */ 1014 u16 tx[3]; 1015 u16 cmn[4]; 1016 union { 1017 u16 mplla[10]; 1018 u16 mpllb[11]; 1019 }; 1020 }; 1021 1022 struct intel_cx0pll_state { 1023 union { 1024 struct intel_c10pll_state c10; 1025 struct intel_c20pll_state c20; 1026 }; 1027 bool ssc_enabled; 1028 }; 1029 1030 struct intel_crtc_state { 1031 /* 1032 * uapi (drm) state. This is the software state shown to userspace. 1033 * In particular, the following members are used for bookkeeping: 1034 * - crtc 1035 * - state 1036 * - *_changed 1037 * - event 1038 * - commit 1039 * - mode_blob 1040 */ 1041 struct drm_crtc_state uapi; 1042 1043 /* 1044 * actual hardware state, the state we program to the hardware. 1045 * The following members are used to verify the hardware state: 1046 * - enable 1047 * - active 1048 * - mode / pipe_mode / adjusted_mode 1049 * - color property blobs. 1050 * 1051 * During initial hw readout, they need to be copied to uapi. 1052 * 1053 * Bigjoiner will allow a transcoder mode that spans 2 pipes; 1054 * Use the pipe_mode for calculations like watermarks, pipe 1055 * scaler, and bandwidth. 1056 * 1057 * Use adjusted_mode for things that need to know the full 1058 * mode on the transcoder, which spans all pipes. 1059 */ 1060 struct { 1061 bool active, enable; 1062 /* logical state of LUTs */ 1063 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; 1064 struct drm_display_mode mode, pipe_mode, adjusted_mode; 1065 enum drm_scaling_filter scaling_filter; 1066 } hw; 1067 1068 /* actual state of LUTs */ 1069 struct drm_property_blob *pre_csc_lut, *post_csc_lut; 1070 1071 struct intel_csc_matrix csc, output_csc; 1072 1073 /** 1074 * quirks - bitfield with hw state readout quirks 1075 * 1076 * For various reasons the hw state readout code might not be able to 1077 * completely faithfully read out the current state. These cases are 1078 * tracked with quirk flags so that fastboot and state checker can act 1079 * accordingly. 1080 */ 1081 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ 1082 unsigned long quirks; 1083 1084 unsigned fb_bits; /* framebuffers to flip */ 1085 bool update_pipe; /* can a fast modeset be performed? */ 1086 bool disable_cxsr; 1087 bool update_wm_pre, update_wm_post; /* watermarks are updated */ 1088 bool fifo_changed; /* FIFO split is changed */ 1089 bool preload_luts; 1090 bool inherited; /* state inherited from BIOS? */ 1091 1092 /* Ask the hardware to actually async flip? */ 1093 bool do_async_flip; 1094 1095 /* Pipe source size (ie. panel fitter input size) 1096 * All planes will be positioned inside this space, 1097 * and get clipped at the edges. */ 1098 struct drm_rect pipe_src; 1099 1100 /* 1101 * Pipe pixel rate, adjusted for 1102 * panel fitter/pipe scaler downscaling. 1103 */ 1104 unsigned int pixel_rate; 1105 1106 /* Whether to set up the PCH/FDI. Note that we never allow sharing 1107 * between pch encoders and cpu encoders. */ 1108 bool has_pch_encoder; 1109 1110 /* Are we sending infoframes on the attached port */ 1111 bool has_infoframe; 1112 1113 /* CPU Transcoder for the pipe. Currently this can only differ from the 1114 * pipe on Haswell and later (where we have a special eDP transcoder) 1115 * and Broxton (where we have special DSI transcoders). */ 1116 enum transcoder cpu_transcoder; 1117 1118 /* 1119 * Use reduced/limited/broadcast rbg range, compressing from the full 1120 * range fed into the crtcs. 1121 */ 1122 bool limited_color_range; 1123 1124 /* Bitmask of encoder types (enum intel_output_type) 1125 * driven by the pipe. 1126 */ 1127 unsigned int output_types; 1128 1129 /* Whether we should send NULL infoframes. Required for audio. */ 1130 bool has_hdmi_sink; 1131 1132 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or 1133 * has_dp_encoder is set. */ 1134 bool has_audio; 1135 1136 /* 1137 * Enable dithering, used when the selected pipe bpp doesn't match the 1138 * plane bpp. 1139 */ 1140 bool dither; 1141 1142 /* 1143 * Dither gets enabled for 18bpp which causes CRC mismatch errors for 1144 * compliance video pattern tests. 1145 * Disable dither only if it is a compliance test request for 1146 * 18bpp. 1147 */ 1148 bool dither_force_disable; 1149 1150 /* Controls for the clock computation, to override various stages. */ 1151 bool clock_set; 1152 1153 /* SDVO TV has a bunch of special case. To make multifunction encoders 1154 * work correctly, we need to track this at runtime.*/ 1155 bool sdvo_tv_clock; 1156 1157 /* 1158 * crtc bandwidth limit, don't increase pipe bpp or clock if not really 1159 * required. This is set in the 2nd loop of calling encoder's 1160 * ->compute_config if the first pick doesn't work out. 1161 */ 1162 bool bw_constrained; 1163 1164 /* Settings for the intel dpll used on pretty much everything but 1165 * haswell. */ 1166 struct dpll dpll; 1167 1168 /* Selected dpll when shared or NULL. */ 1169 struct intel_shared_dpll *shared_dpll; 1170 1171 /* Actual register state of the dpll, for shared dpll cross-checking. */ 1172 union { 1173 struct intel_dpll_hw_state dpll_hw_state; 1174 struct intel_mpllb_state mpllb_state; 1175 struct intel_cx0pll_state cx0pll_state; 1176 }; 1177 1178 /* 1179 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by 1180 * setting shared_dpll and dpll_hw_state to one of these reserved ones. 1181 */ 1182 struct icl_port_dpll { 1183 struct intel_shared_dpll *pll; 1184 struct intel_dpll_hw_state hw_state; 1185 } icl_port_dplls[ICL_PORT_DPLL_COUNT]; 1186 1187 /* DSI PLL registers */ 1188 struct { 1189 u32 ctrl, div; 1190 } dsi_pll; 1191 1192 int pipe_bpp; 1193 struct intel_link_m_n dp_m_n; 1194 1195 /* m2_n2 for eDP downclock */ 1196 struct intel_link_m_n dp_m2_n2; 1197 bool has_drrs; 1198 bool seamless_m_n; 1199 1200 /* PSR is supported but might not be enabled due the lack of enabled planes */ 1201 bool has_psr; 1202 bool has_psr2; 1203 bool enable_psr2_sel_fetch; 1204 bool req_psr2_sdp_prior_scanline; 1205 bool wm_level_disabled; 1206 u32 dc3co_exitline; 1207 u16 su_y_granularity; 1208 struct drm_dp_vsc_sdp psr_vsc; 1209 1210 /* 1211 * Frequence the dpll for the port should run at. Differs from the 1212 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also 1213 * already multiplied by pixel_multiplier. 1214 */ 1215 int port_clock; 1216 1217 /* Used by SDVO (and if we ever fix it, HDMI). */ 1218 unsigned pixel_multiplier; 1219 1220 /* I915_MODE_FLAG_* */ 1221 u8 mode_flags; 1222 1223 u8 lane_count; 1224 1225 /* 1226 * Used by platforms having DP/HDMI PHY with programmable lane 1227 * latency optimization. 1228 */ 1229 u8 lane_lat_optim_mask; 1230 1231 /* minimum acceptable voltage level */ 1232 u8 min_voltage_level; 1233 1234 /* Panel fitter controls for gen2-gen4 + VLV */ 1235 struct { 1236 u32 control; 1237 u32 pgm_ratios; 1238 u32 lvds_border_bits; 1239 } gmch_pfit; 1240 1241 /* Panel fitter placement and size for Ironlake+ */ 1242 struct { 1243 struct drm_rect dst; 1244 bool enabled; 1245 bool force_thru; 1246 } pch_pfit; 1247 1248 /* FDI configuration, only valid if has_pch_encoder is set. */ 1249 int fdi_lanes; 1250 struct intel_link_m_n fdi_m_n; 1251 1252 bool ips_enabled; 1253 1254 bool crc_enabled; 1255 1256 bool double_wide; 1257 1258 int pbn; 1259 1260 struct intel_crtc_scaler_state scaler_state; 1261 1262 /* w/a for waiting 2 vblanks during crtc enable */ 1263 enum pipe hsw_workaround_pipe; 1264 1265 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ 1266 bool disable_lp_wm; 1267 1268 struct intel_crtc_wm_state wm; 1269 1270 int min_cdclk[I915_MAX_PLANES]; 1271 1272 /* for packed/planar CbCr */ 1273 u32 data_rate[I915_MAX_PLANES]; 1274 /* for planar Y */ 1275 u32 data_rate_y[I915_MAX_PLANES]; 1276 1277 /* FIXME unify with data_rate[]? */ 1278 u64 rel_data_rate[I915_MAX_PLANES]; 1279 u64 rel_data_rate_y[I915_MAX_PLANES]; 1280 1281 /* Gamma mode programmed on the pipe */ 1282 u32 gamma_mode; 1283 1284 union { 1285 /* CSC mode programmed on the pipe */ 1286 u32 csc_mode; 1287 1288 /* CHV CGM mode */ 1289 u32 cgm_mode; 1290 }; 1291 1292 /* bitmask of logically enabled planes (enum plane_id) */ 1293 u8 enabled_planes; 1294 1295 /* bitmask of actually visible planes (enum plane_id) */ 1296 u8 active_planes; 1297 u8 scaled_planes; 1298 u8 nv12_planes; 1299 u8 c8_planes; 1300 1301 /* bitmask of planes that will be updated during the commit */ 1302 u8 update_planes; 1303 1304 /* bitmask of planes with async flip active */ 1305 u8 async_flip_planes; 1306 1307 u8 framestart_delay; /* 1-4 */ 1308 u8 msa_timing_delay; /* 0-3 */ 1309 1310 struct { 1311 u32 enable; 1312 u32 gcp; 1313 union hdmi_infoframe avi; 1314 union hdmi_infoframe spd; 1315 union hdmi_infoframe hdmi; 1316 union hdmi_infoframe drm; 1317 struct drm_dp_vsc_sdp vsc; 1318 } infoframes; 1319 1320 u8 eld[MAX_ELD_BYTES]; 1321 1322 /* HDMI scrambling status */ 1323 bool hdmi_scrambling; 1324 1325 /* HDMI High TMDS char rate ratio */ 1326 bool hdmi_high_tmds_clock_ratio; 1327 1328 /* 1329 * Output format RGB/YCBCR etc., that is coming out 1330 * at the end of the pipe. 1331 */ 1332 enum intel_output_format output_format; 1333 1334 /* 1335 * Sink output format RGB/YCBCR etc., that is going 1336 * into the sink. 1337 */ 1338 enum intel_output_format sink_format; 1339 1340 /* enable pipe gamma? */ 1341 bool gamma_enable; 1342 1343 /* enable pipe csc? */ 1344 bool csc_enable; 1345 1346 /* enable vlv/chv wgc csc? */ 1347 bool wgc_enable; 1348 1349 /* big joiner pipe bitmask */ 1350 u8 bigjoiner_pipes; 1351 1352 /* Display Stream compression state */ 1353 struct { 1354 bool compression_enable; 1355 bool dsc_split; 1356 u16 compressed_bpp; 1357 u8 slice_count; 1358 struct drm_dsc_config config; 1359 } dsc; 1360 1361 /* HSW+ linetime watermarks */ 1362 u16 linetime; 1363 u16 ips_linetime; 1364 1365 /* Forward Error correction State */ 1366 bool fec_enable; 1367 1368 bool sdp_split_enable; 1369 1370 /* Pointer to master transcoder in case of tiled displays */ 1371 enum transcoder master_transcoder; 1372 1373 /* Bitmask to indicate slaves attached */ 1374 u8 sync_mode_slaves_mask; 1375 1376 /* Only valid on TGL+ */ 1377 enum transcoder mst_master_transcoder; 1378 1379 /* For DSB related info */ 1380 struct intel_dsb *dsb; 1381 1382 u32 psr2_man_track_ctl; 1383 1384 /* Variable Refresh Rate state */ 1385 struct { 1386 bool enable; 1387 u8 pipeline_full; 1388 u16 flipline, vmin, vmax, guardband; 1389 } vrr; 1390 1391 /* Stream Splitter for eDP MSO */ 1392 struct { 1393 bool enable; 1394 u8 link_count; 1395 u8 pixel_overlap; 1396 } splitter; 1397 1398 /* for loading single buffered registers during vblank */ 1399 struct drm_vblank_work vblank_work; 1400 }; 1401 1402 enum intel_pipe_crc_source { 1403 INTEL_PIPE_CRC_SOURCE_NONE, 1404 INTEL_PIPE_CRC_SOURCE_PLANE1, 1405 INTEL_PIPE_CRC_SOURCE_PLANE2, 1406 INTEL_PIPE_CRC_SOURCE_PLANE3, 1407 INTEL_PIPE_CRC_SOURCE_PLANE4, 1408 INTEL_PIPE_CRC_SOURCE_PLANE5, 1409 INTEL_PIPE_CRC_SOURCE_PLANE6, 1410 INTEL_PIPE_CRC_SOURCE_PLANE7, 1411 INTEL_PIPE_CRC_SOURCE_PIPE, 1412 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1413 INTEL_PIPE_CRC_SOURCE_TV, 1414 INTEL_PIPE_CRC_SOURCE_DP_B, 1415 INTEL_PIPE_CRC_SOURCE_DP_C, 1416 INTEL_PIPE_CRC_SOURCE_DP_D, 1417 INTEL_PIPE_CRC_SOURCE_AUTO, 1418 INTEL_PIPE_CRC_SOURCE_MAX, 1419 }; 1420 1421 enum drrs_refresh_rate { 1422 DRRS_REFRESH_RATE_HIGH, 1423 DRRS_REFRESH_RATE_LOW, 1424 }; 1425 1426 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1427 struct intel_pipe_crc { 1428 spinlock_t lock; 1429 int skipped; 1430 enum intel_pipe_crc_source source; 1431 }; 1432 1433 struct intel_crtc { 1434 struct drm_crtc base; 1435 enum pipe pipe; 1436 /* 1437 * Whether the crtc and the connected output pipeline is active. Implies 1438 * that crtc->enabled is set, i.e. the current mode configuration has 1439 * some outputs connected to this crtc. 1440 */ 1441 bool active; 1442 u8 plane_ids_mask; 1443 1444 /* I915_MODE_FLAG_* */ 1445 u8 mode_flags; 1446 1447 u16 vmax_vblank_start; 1448 1449 struct intel_display_power_domain_set enabled_power_domains; 1450 struct intel_display_power_domain_set hw_readout_power_domains; 1451 struct intel_overlay *overlay; 1452 1453 struct intel_crtc_state *config; 1454 1455 /* Access to these should be protected by dev_priv->irq_lock. */ 1456 bool cpu_fifo_underrun_disabled; 1457 bool pch_fifo_underrun_disabled; 1458 1459 /* per-pipe watermark state */ 1460 struct { 1461 /* watermarks currently being used */ 1462 union { 1463 struct intel_pipe_wm ilk; 1464 struct vlv_wm_state vlv; 1465 struct g4x_wm_state g4x; 1466 } active; 1467 } wm; 1468 1469 struct { 1470 struct mutex mutex; 1471 struct delayed_work work; 1472 enum drrs_refresh_rate refresh_rate; 1473 unsigned int frontbuffer_bits; 1474 unsigned int busy_frontbuffer_bits; 1475 enum transcoder cpu_transcoder; 1476 struct intel_link_m_n m_n, m2_n2; 1477 } drrs; 1478 1479 int scanline_offset; 1480 1481 struct { 1482 unsigned start_vbl_count; 1483 ktime_t start_vbl_time; 1484 int min_vbl, max_vbl; 1485 int scanline_start; 1486 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE 1487 struct { 1488 u64 min; 1489 u64 max; 1490 u64 sum; 1491 unsigned int over; 1492 unsigned int times[17]; /* [1us, 16ms] */ 1493 } vbl; 1494 #endif 1495 } debug; 1496 1497 /* scalers available on this crtc */ 1498 int num_scalers; 1499 1500 /* for loading single buffered registers during vblank */ 1501 struct pm_qos_request vblank_pm_qos; 1502 1503 #ifdef CONFIG_DEBUG_FS 1504 struct intel_pipe_crc pipe_crc; 1505 #endif 1506 }; 1507 1508 struct intel_plane { 1509 struct drm_plane base; 1510 enum i9xx_plane_id i9xx_plane; 1511 enum plane_id id; 1512 enum pipe pipe; 1513 bool need_async_flip_disable_wa; 1514 u32 frontbuffer_bit; 1515 1516 struct { 1517 u32 base, cntl, size; 1518 } cursor; 1519 1520 struct intel_fbc *fbc; 1521 1522 /* 1523 * NOTE: Do not place new plane state fields here (e.g., when adding 1524 * new plane properties). New runtime state should now be placed in 1525 * the intel_plane_state structure and accessed via plane_state. 1526 */ 1527 1528 int (*min_width)(const struct drm_framebuffer *fb, 1529 int color_plane, 1530 unsigned int rotation); 1531 int (*max_width)(const struct drm_framebuffer *fb, 1532 int color_plane, 1533 unsigned int rotation); 1534 int (*max_height)(const struct drm_framebuffer *fb, 1535 int color_plane, 1536 unsigned int rotation); 1537 unsigned int (*max_stride)(struct intel_plane *plane, 1538 u32 pixel_format, u64 modifier, 1539 unsigned int rotation); 1540 /* Write all non-self arming plane registers */ 1541 void (*update_noarm)(struct intel_plane *plane, 1542 const struct intel_crtc_state *crtc_state, 1543 const struct intel_plane_state *plane_state); 1544 /* Write all self-arming plane registers */ 1545 void (*update_arm)(struct intel_plane *plane, 1546 const struct intel_crtc_state *crtc_state, 1547 const struct intel_plane_state *plane_state); 1548 /* Disable the plane, must arm */ 1549 void (*disable_arm)(struct intel_plane *plane, 1550 const struct intel_crtc_state *crtc_state); 1551 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe); 1552 int (*check_plane)(struct intel_crtc_state *crtc_state, 1553 struct intel_plane_state *plane_state); 1554 int (*min_cdclk)(const struct intel_crtc_state *crtc_state, 1555 const struct intel_plane_state *plane_state); 1556 void (*async_flip)(struct intel_plane *plane, 1557 const struct intel_crtc_state *crtc_state, 1558 const struct intel_plane_state *plane_state, 1559 bool async_flip); 1560 void (*enable_flip_done)(struct intel_plane *plane); 1561 void (*disable_flip_done)(struct intel_plane *plane); 1562 }; 1563 1564 struct intel_watermark_params { 1565 u16 fifo_size; 1566 u16 max_wm; 1567 u8 default_wm; 1568 u8 guard_size; 1569 u8 cacheline_size; 1570 }; 1571 1572 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) 1573 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 1574 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi) 1575 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 1576 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 1577 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 1578 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 1579 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi) 1580 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL) 1581 1582 struct intel_hdmi { 1583 i915_reg_t hdmi_reg; 1584 int ddc_bus; 1585 struct { 1586 enum drm_dp_dual_mode_type type; 1587 int max_tmds_clock; 1588 } dp_dual_mode; 1589 struct intel_connector *attached_connector; 1590 struct cec_notifier *cec_notifier; 1591 }; 1592 1593 struct intel_dp_mst_encoder; 1594 1595 struct intel_dp_compliance_data { 1596 unsigned long edid; 1597 u8 video_pattern; 1598 u16 hdisplay, vdisplay; 1599 u8 bpc; 1600 struct drm_dp_phy_test_params phytest; 1601 }; 1602 1603 struct intel_dp_compliance { 1604 unsigned long test_type; 1605 struct intel_dp_compliance_data test_data; 1606 bool test_active; 1607 int test_link_rate; 1608 u8 test_lane_count; 1609 }; 1610 1611 struct intel_dp_pcon_frl { 1612 bool is_trained; 1613 int trained_rate_gbps; 1614 }; 1615 1616 struct intel_pps { 1617 int panel_power_up_delay; 1618 int panel_power_down_delay; 1619 int panel_power_cycle_delay; 1620 int backlight_on_delay; 1621 int backlight_off_delay; 1622 struct delayed_work panel_vdd_work; 1623 bool want_panel_vdd; 1624 bool initializing; 1625 unsigned long last_power_on; 1626 unsigned long last_backlight_off; 1627 ktime_t panel_power_off_time; 1628 intel_wakeref_t vdd_wakeref; 1629 1630 union { 1631 /* 1632 * Pipe whose power sequencer is currently locked into 1633 * this port. Only relevant on VLV/CHV. 1634 */ 1635 enum pipe pps_pipe; 1636 1637 /* 1638 * Power sequencer index. Only relevant on BXT+. 1639 */ 1640 int pps_idx; 1641 }; 1642 1643 /* 1644 * Pipe currently driving the port. Used for preventing 1645 * the use of the PPS for any pipe currentrly driving 1646 * external DP as that will mess things up on VLV. 1647 */ 1648 enum pipe active_pipe; 1649 /* 1650 * Set if the sequencer may be reset due to a power transition, 1651 * requiring a reinitialization. Only relevant on BXT+. 1652 */ 1653 bool pps_reset; 1654 struct edp_power_seq pps_delays; 1655 struct edp_power_seq bios_pps_delays; 1656 }; 1657 1658 struct intel_psr { 1659 /* Mutex for PSR state of the transcoder */ 1660 struct mutex lock; 1661 1662 #define I915_PSR_DEBUG_MODE_MASK 0x0f 1663 #define I915_PSR_DEBUG_DEFAULT 0x00 1664 #define I915_PSR_DEBUG_DISABLE 0x01 1665 #define I915_PSR_DEBUG_ENABLE 0x02 1666 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 1667 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4 1668 #define I915_PSR_DEBUG_IRQ 0x10 1669 1670 u32 debug; 1671 bool sink_support; 1672 bool source_support; 1673 bool enabled; 1674 bool paused; 1675 enum pipe pipe; 1676 enum transcoder transcoder; 1677 bool active; 1678 struct work_struct work; 1679 unsigned int busy_frontbuffer_bits; 1680 bool sink_psr2_support; 1681 bool link_standby; 1682 bool colorimetry_support; 1683 bool psr2_enabled; 1684 bool psr2_sel_fetch_enabled; 1685 bool psr2_sel_fetch_cff_enabled; 1686 bool req_psr2_sdp_prior_scanline; 1687 u8 sink_sync_latency; 1688 u8 io_wake_lines; 1689 u8 fast_wake_lines; 1690 ktime_t last_entry_attempt; 1691 ktime_t last_exit; 1692 bool sink_not_reliable; 1693 bool irq_aux_error; 1694 u16 su_w_granularity; 1695 u16 su_y_granularity; 1696 u32 dc3co_exitline; 1697 u32 dc3co_exit_delay; 1698 struct delayed_work dc3co_work; 1699 }; 1700 1701 struct intel_dp { 1702 i915_reg_t output_reg; 1703 u32 DP; 1704 int link_rate; 1705 u8 lane_count; 1706 u8 sink_count; 1707 bool link_trained; 1708 bool reset_link_params; 1709 bool use_max_params; 1710 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 1711 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 1712 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 1713 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; 1714 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; 1715 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; 1716 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; 1717 u8 fec_capable; 1718 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]; 1719 /* source rates */ 1720 int num_source_rates; 1721 const int *source_rates; 1722 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */ 1723 int num_sink_rates; 1724 int sink_rates[DP_MAX_SUPPORTED_RATES]; 1725 bool use_rate_select; 1726 /* Max sink lane count as reported by DP_MAX_LANE_COUNT */ 1727 int max_sink_lane_count; 1728 /* intersection of source and sink rates */ 1729 int num_common_rates; 1730 int common_rates[DP_MAX_SUPPORTED_RATES]; 1731 /* Max lane count for the current link */ 1732 int max_link_lane_count; 1733 /* Max rate for the current link */ 1734 int max_link_rate; 1735 int mso_link_count; 1736 int mso_pixel_overlap; 1737 /* sink or branch descriptor */ 1738 struct drm_dp_desc desc; 1739 struct drm_dp_aux aux; 1740 u32 aux_busy_last_status; 1741 u8 train_set[4]; 1742 1743 struct intel_pps pps; 1744 1745 bool is_mst; 1746 int active_mst_links; 1747 1748 /* connector directly attached - won't be use for modeset in mst world */ 1749 struct intel_connector *attached_connector; 1750 1751 /* mst connector list */ 1752 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; 1753 struct drm_dp_mst_topology_mgr mst_mgr; 1754 1755 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index); 1756 /* 1757 * This function returns the value we have to program the AUX_CTL 1758 * register with to kick off an AUX transaction. 1759 */ 1760 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes, 1761 u32 aux_clock_divider); 1762 1763 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); 1764 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); 1765 1766 /* This is called before a link training is starterd */ 1767 void (*prepare_link_retrain)(struct intel_dp *intel_dp, 1768 const struct intel_crtc_state *crtc_state); 1769 void (*set_link_train)(struct intel_dp *intel_dp, 1770 const struct intel_crtc_state *crtc_state, 1771 u8 dp_train_pat); 1772 void (*set_idle_link_train)(struct intel_dp *intel_dp, 1773 const struct intel_crtc_state *crtc_state); 1774 1775 u8 (*preemph_max)(struct intel_dp *intel_dp); 1776 u8 (*voltage_max)(struct intel_dp *intel_dp, 1777 const struct intel_crtc_state *crtc_state); 1778 1779 /* Displayport compliance testing */ 1780 struct intel_dp_compliance compliance; 1781 1782 /* Downstream facing port caps */ 1783 struct { 1784 int min_tmds_clock, max_tmds_clock; 1785 int max_dotclock; 1786 int pcon_max_frl_bw; 1787 u8 max_bpc; 1788 bool ycbcr_444_to_420; 1789 bool ycbcr420_passthrough; 1790 bool rgb_to_ycbcr; 1791 } dfp; 1792 1793 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1794 struct pm_qos_request pm_qos; 1795 1796 /* Display stream compression testing */ 1797 bool force_dsc_en; 1798 int force_dsc_output_format; 1799 int force_dsc_bpc; 1800 1801 bool hobl_failed; 1802 bool hobl_active; 1803 1804 struct intel_dp_pcon_frl frl; 1805 1806 struct intel_psr psr; 1807 1808 /* When we last wrote the OUI for eDP */ 1809 unsigned long last_oui_write; 1810 }; 1811 1812 enum lspcon_vendor { 1813 LSPCON_VENDOR_MCA, 1814 LSPCON_VENDOR_PARADE 1815 }; 1816 1817 struct intel_lspcon { 1818 bool active; 1819 bool hdr_supported; 1820 enum drm_lspcon_mode mode; 1821 enum lspcon_vendor vendor; 1822 }; 1823 1824 struct intel_digital_port { 1825 struct intel_encoder base; 1826 u32 saved_port_bits; 1827 struct intel_dp dp; 1828 struct intel_hdmi hdmi; 1829 struct intel_lspcon lspcon; 1830 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); 1831 bool release_cl2_override; 1832 u8 max_lanes; 1833 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */ 1834 enum aux_ch aux_ch; 1835 enum intel_display_power_domain ddi_io_power_domain; 1836 intel_wakeref_t ddi_io_wakeref; 1837 intel_wakeref_t aux_wakeref; 1838 1839 struct intel_tc_port *tc; 1840 1841 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */ 1842 struct mutex hdcp_mutex; 1843 /* the number of pipes using HDCP signalling out of this port */ 1844 unsigned int num_hdcp_streams; 1845 /* port HDCP auth status */ 1846 bool hdcp_auth_status; 1847 /* HDCP port data need to pass to security f/w */ 1848 struct hdcp_port_data hdcp_port_data; 1849 /* Whether the MST topology supports HDCP Type 1 Content */ 1850 bool hdcp_mst_type1_capable; 1851 1852 void (*write_infoframe)(struct intel_encoder *encoder, 1853 const struct intel_crtc_state *crtc_state, 1854 unsigned int type, 1855 const void *frame, ssize_t len); 1856 void (*read_infoframe)(struct intel_encoder *encoder, 1857 const struct intel_crtc_state *crtc_state, 1858 unsigned int type, 1859 void *frame, ssize_t len); 1860 void (*set_infoframes)(struct intel_encoder *encoder, 1861 bool enable, 1862 const struct intel_crtc_state *crtc_state, 1863 const struct drm_connector_state *conn_state); 1864 u32 (*infoframes_enabled)(struct intel_encoder *encoder, 1865 const struct intel_crtc_state *pipe_config); 1866 bool (*connected)(struct intel_encoder *encoder); 1867 }; 1868 1869 struct intel_dp_mst_encoder { 1870 struct intel_encoder base; 1871 enum pipe pipe; 1872 struct intel_digital_port *primary; 1873 struct intel_connector *connector; 1874 }; 1875 1876 static inline struct intel_encoder * 1877 intel_attached_encoder(struct intel_connector *connector) 1878 { 1879 return connector->encoder; 1880 } 1881 1882 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder) 1883 { 1884 switch (encoder->type) { 1885 case INTEL_OUTPUT_DDI: 1886 case INTEL_OUTPUT_DP: 1887 case INTEL_OUTPUT_EDP: 1888 case INTEL_OUTPUT_HDMI: 1889 return true; 1890 default: 1891 return false; 1892 } 1893 } 1894 1895 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder) 1896 { 1897 return encoder->type == INTEL_OUTPUT_DP_MST; 1898 } 1899 1900 static inline struct intel_dp_mst_encoder * 1901 enc_to_mst(struct intel_encoder *encoder) 1902 { 1903 return container_of(&encoder->base, struct intel_dp_mst_encoder, 1904 base.base); 1905 } 1906 1907 static inline struct intel_digital_port * 1908 enc_to_dig_port(struct intel_encoder *encoder) 1909 { 1910 struct intel_encoder *intel_encoder = encoder; 1911 1912 if (intel_encoder_is_dig_port(intel_encoder)) 1913 return container_of(&encoder->base, struct intel_digital_port, 1914 base.base); 1915 else if (intel_encoder_is_mst(intel_encoder)) 1916 return enc_to_mst(encoder)->primary; 1917 else 1918 return NULL; 1919 } 1920 1921 static inline struct intel_digital_port * 1922 intel_attached_dig_port(struct intel_connector *connector) 1923 { 1924 return enc_to_dig_port(intel_attached_encoder(connector)); 1925 } 1926 1927 static inline struct intel_hdmi * 1928 enc_to_intel_hdmi(struct intel_encoder *encoder) 1929 { 1930 return &enc_to_dig_port(encoder)->hdmi; 1931 } 1932 1933 static inline struct intel_hdmi * 1934 intel_attached_hdmi(struct intel_connector *connector) 1935 { 1936 return enc_to_intel_hdmi(intel_attached_encoder(connector)); 1937 } 1938 1939 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder) 1940 { 1941 return &enc_to_dig_port(encoder)->dp; 1942 } 1943 1944 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector) 1945 { 1946 return enc_to_intel_dp(intel_attached_encoder(connector)); 1947 } 1948 1949 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) 1950 { 1951 switch (encoder->type) { 1952 case INTEL_OUTPUT_DP: 1953 case INTEL_OUTPUT_EDP: 1954 return true; 1955 case INTEL_OUTPUT_DDI: 1956 /* Skip pure HDMI/DVI DDI encoders */ 1957 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg); 1958 default: 1959 return false; 1960 } 1961 } 1962 1963 static inline struct intel_lspcon * 1964 enc_to_intel_lspcon(struct intel_encoder *encoder) 1965 { 1966 return &enc_to_dig_port(encoder)->lspcon; 1967 } 1968 1969 static inline struct intel_digital_port * 1970 dp_to_dig_port(struct intel_dp *intel_dp) 1971 { 1972 return container_of(intel_dp, struct intel_digital_port, dp); 1973 } 1974 1975 static inline struct intel_lspcon * 1976 dp_to_lspcon(struct intel_dp *intel_dp) 1977 { 1978 return &dp_to_dig_port(intel_dp)->lspcon; 1979 } 1980 1981 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev) 1982 1983 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ 1984 (intel_dp)->psr.source_support) 1985 1986 static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) 1987 { 1988 if (!intel_encoder_is_dp(encoder)) 1989 return false; 1990 1991 return CAN_PSR(enc_to_intel_dp(encoder)); 1992 } 1993 1994 static inline struct intel_digital_port * 1995 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 1996 { 1997 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 1998 } 1999 2000 static inline struct intel_plane_state * 2001 intel_atomic_get_plane_state(struct intel_atomic_state *state, 2002 struct intel_plane *plane) 2003 { 2004 struct drm_plane_state *ret = 2005 drm_atomic_get_plane_state(&state->base, &plane->base); 2006 2007 if (IS_ERR(ret)) 2008 return ERR_CAST(ret); 2009 2010 return to_intel_plane_state(ret); 2011 } 2012 2013 static inline struct intel_plane_state * 2014 intel_atomic_get_old_plane_state(struct intel_atomic_state *state, 2015 struct intel_plane *plane) 2016 { 2017 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base, 2018 &plane->base)); 2019 } 2020 2021 static inline struct intel_plane_state * 2022 intel_atomic_get_new_plane_state(struct intel_atomic_state *state, 2023 struct intel_plane *plane) 2024 { 2025 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base, 2026 &plane->base)); 2027 } 2028 2029 static inline struct intel_crtc_state * 2030 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state, 2031 struct intel_crtc *crtc) 2032 { 2033 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base, 2034 &crtc->base)); 2035 } 2036 2037 static inline struct intel_crtc_state * 2038 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state, 2039 struct intel_crtc *crtc) 2040 { 2041 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, 2042 &crtc->base)); 2043 } 2044 2045 static inline struct intel_digital_connector_state * 2046 intel_atomic_get_new_connector_state(struct intel_atomic_state *state, 2047 struct intel_connector *connector) 2048 { 2049 return to_intel_digital_connector_state( 2050 drm_atomic_get_new_connector_state(&state->base, 2051 &connector->base)); 2052 } 2053 2054 static inline struct intel_digital_connector_state * 2055 intel_atomic_get_old_connector_state(struct intel_atomic_state *state, 2056 struct intel_connector *connector) 2057 { 2058 return to_intel_digital_connector_state( 2059 drm_atomic_get_old_connector_state(&state->base, 2060 &connector->base)); 2061 } 2062 2063 /* intel_display.c */ 2064 static inline bool 2065 intel_crtc_has_type(const struct intel_crtc_state *crtc_state, 2066 enum intel_output_type type) 2067 { 2068 return crtc_state->output_types & BIT(type); 2069 } 2070 2071 static inline bool 2072 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) 2073 { 2074 return crtc_state->output_types & 2075 (BIT(INTEL_OUTPUT_DP) | 2076 BIT(INTEL_OUTPUT_DP_MST) | 2077 BIT(INTEL_OUTPUT_EDP)); 2078 } 2079 2080 static inline bool 2081 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state) 2082 { 2083 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi); 2084 } 2085 2086 static inline bool 2087 intel_crtc_needs_fastset(const struct intel_crtc_state *crtc_state) 2088 { 2089 return crtc_state->update_pipe; 2090 } 2091 2092 static inline bool 2093 intel_crtc_needs_color_update(const struct intel_crtc_state *crtc_state) 2094 { 2095 return crtc_state->uapi.color_mgmt_changed || 2096 intel_crtc_needs_fastset(crtc_state) || 2097 intel_crtc_needs_modeset(crtc_state); 2098 } 2099 2100 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state) 2101 { 2102 return i915_ggtt_offset(plane_state->ggtt_vma); 2103 } 2104 2105 static inline struct intel_frontbuffer * 2106 to_intel_frontbuffer(struct drm_framebuffer *fb) 2107 { 2108 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; 2109 } 2110 2111 #endif /* __INTEL_DISPLAY_TYPES_H__ */ 2112