1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25 26 #ifndef __INTEL_DISPLAY_TYPES_H__ 27 #define __INTEL_DISPLAY_TYPES_H__ 28 29 #include <linux/async.h> 30 #include <linux/i2c.h> 31 #include <linux/sched/clock.h> 32 33 #include <drm/drm_atomic.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_dp_dual_mode_helper.h> 36 #include <drm/drm_dp_mst_helper.h> 37 #include <drm/drm_encoder.h> 38 #include <drm/drm_fb_helper.h> 39 #include <drm/drm_probe_helper.h> 40 #include <drm/drm_rect.h> 41 #include <drm/drm_vblank.h> 42 #include <drm/i915_mei_hdcp_interface.h> 43 #include <media/cec-notifier.h> 44 45 #include "i915_drv.h" 46 #include "intel_de.h" 47 48 struct drm_printer; 49 struct __intel_global_objs_state; 50 51 /* 52 * Display related stuff 53 */ 54 55 /* these are outputs from the chip - integrated only 56 external chips are via DVO or SDVO output */ 57 enum intel_output_type { 58 INTEL_OUTPUT_UNUSED = 0, 59 INTEL_OUTPUT_ANALOG = 1, 60 INTEL_OUTPUT_DVO = 2, 61 INTEL_OUTPUT_SDVO = 3, 62 INTEL_OUTPUT_LVDS = 4, 63 INTEL_OUTPUT_TVOUT = 5, 64 INTEL_OUTPUT_HDMI = 6, 65 INTEL_OUTPUT_DP = 7, 66 INTEL_OUTPUT_EDP = 8, 67 INTEL_OUTPUT_DSI = 9, 68 INTEL_OUTPUT_DDI = 10, 69 INTEL_OUTPUT_DP_MST = 11, 70 }; 71 72 enum hdmi_force_audio { 73 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 74 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 75 HDMI_AUDIO_AUTO, /* trust EDID */ 76 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 77 }; 78 79 /* "Broadcast RGB" property */ 80 enum intel_broadcast_rgb { 81 INTEL_BROADCAST_RGB_AUTO, 82 INTEL_BROADCAST_RGB_FULL, 83 INTEL_BROADCAST_RGB_LIMITED, 84 }; 85 86 struct intel_framebuffer { 87 struct drm_framebuffer base; 88 struct intel_frontbuffer *frontbuffer; 89 struct intel_rotation_info rot_info; 90 91 /* for each plane in the normal GTT view */ 92 struct { 93 unsigned int x, y; 94 } normal[4]; 95 /* for each plane in the rotated GTT view for no-CCS formats */ 96 struct { 97 unsigned int x, y; 98 unsigned int pitch; /* pixels */ 99 } rotated[2]; 100 }; 101 102 struct intel_fbdev { 103 struct drm_fb_helper helper; 104 struct intel_framebuffer *fb; 105 struct i915_vma *vma; 106 unsigned long vma_flags; 107 async_cookie_t cookie; 108 int preferred_bpp; 109 110 /* Whether or not fbdev hpd processing is temporarily suspended */ 111 bool hpd_suspended : 1; 112 /* Set when a hotplug was received while HPD processing was 113 * suspended 114 */ 115 bool hpd_waiting : 1; 116 117 /* Protects hpd_suspended */ 118 struct mutex hpd_lock; 119 }; 120 121 enum intel_hotplug_state { 122 INTEL_HOTPLUG_UNCHANGED, 123 INTEL_HOTPLUG_CHANGED, 124 INTEL_HOTPLUG_RETRY, 125 }; 126 127 struct intel_encoder { 128 struct drm_encoder base; 129 130 enum intel_output_type type; 131 enum port port; 132 u16 cloneable; 133 u8 pipe_mask; 134 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder, 135 struct intel_connector *connector); 136 enum intel_output_type (*compute_output_type)(struct intel_encoder *, 137 struct intel_crtc_state *, 138 struct drm_connector_state *); 139 int (*compute_config)(struct intel_encoder *, 140 struct intel_crtc_state *, 141 struct drm_connector_state *); 142 int (*compute_config_late)(struct intel_encoder *, 143 struct intel_crtc_state *, 144 struct drm_connector_state *); 145 void (*update_prepare)(struct intel_atomic_state *, 146 struct intel_encoder *, 147 struct intel_crtc *); 148 void (*pre_pll_enable)(struct intel_atomic_state *, 149 struct intel_encoder *, 150 const struct intel_crtc_state *, 151 const struct drm_connector_state *); 152 void (*pre_enable)(struct intel_atomic_state *, 153 struct intel_encoder *, 154 const struct intel_crtc_state *, 155 const struct drm_connector_state *); 156 void (*enable)(struct intel_atomic_state *, 157 struct intel_encoder *, 158 const struct intel_crtc_state *, 159 const struct drm_connector_state *); 160 void (*update_complete)(struct intel_atomic_state *, 161 struct intel_encoder *, 162 struct intel_crtc *); 163 void (*disable)(struct intel_atomic_state *, 164 struct intel_encoder *, 165 const struct intel_crtc_state *, 166 const struct drm_connector_state *); 167 void (*post_disable)(struct intel_atomic_state *, 168 struct intel_encoder *, 169 const struct intel_crtc_state *, 170 const struct drm_connector_state *); 171 void (*post_pll_disable)(struct intel_atomic_state *, 172 struct intel_encoder *, 173 const struct intel_crtc_state *, 174 const struct drm_connector_state *); 175 void (*update_pipe)(struct intel_atomic_state *, 176 struct intel_encoder *, 177 const struct intel_crtc_state *, 178 const struct drm_connector_state *); 179 /* Read out the current hw state of this connector, returning true if 180 * the encoder is active. If the encoder is enabled it also set the pipe 181 * it is connected to in the pipe parameter. */ 182 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); 183 /* Reconstructs the equivalent mode flags for the current hardware 184 * state. This must be called _after_ display->get_pipe_config has 185 * pre-filled the pipe config. Note that intel_encoder->base.crtc must 186 * be set correctly before calling this function. */ 187 void (*get_config)(struct intel_encoder *, 188 struct intel_crtc_state *pipe_config); 189 /* 190 * Acquires the power domains needed for an active encoder during 191 * hardware state readout. 192 */ 193 void (*get_power_domains)(struct intel_encoder *encoder, 194 struct intel_crtc_state *crtc_state); 195 /* 196 * Called during system suspend after all pending requests for the 197 * encoder are flushed (for example for DP AUX transactions) and 198 * device interrupts are disabled. 199 */ 200 void (*suspend)(struct intel_encoder *); 201 enum hpd_pin hpd_pin; 202 enum intel_display_power_domain power_domain; 203 /* for communication with audio component; protected by av_mutex */ 204 const struct drm_connector *audio_connector; 205 }; 206 207 struct intel_panel { 208 struct drm_display_mode *fixed_mode; 209 struct drm_display_mode *downclock_mode; 210 211 /* backlight */ 212 struct { 213 bool present; 214 u32 level; 215 u32 min; 216 u32 max; 217 bool enabled; 218 bool combination_mode; /* gen 2/4 only */ 219 bool active_low_pwm; 220 bool alternate_pwm_increment; /* lpt+ */ 221 222 /* PWM chip */ 223 bool util_pin_active_low; /* bxt+ */ 224 u8 controller; /* bxt+ only */ 225 struct pwm_device *pwm; 226 227 /* DPCD backlight */ 228 u8 pwmgen_bit_count; 229 230 struct backlight_device *device; 231 232 /* Connector and platform specific backlight functions */ 233 int (*setup)(struct intel_connector *connector, enum pipe pipe); 234 u32 (*get)(struct intel_connector *connector); 235 void (*set)(const struct drm_connector_state *conn_state, u32 level); 236 void (*disable)(const struct drm_connector_state *conn_state); 237 void (*enable)(const struct intel_crtc_state *crtc_state, 238 const struct drm_connector_state *conn_state); 239 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz); 240 void (*power)(struct intel_connector *, bool enable); 241 } backlight; 242 }; 243 244 struct intel_digital_port; 245 246 enum check_link_response { 247 HDCP_LINK_PROTECTED = 0, 248 HDCP_TOPOLOGY_CHANGE, 249 HDCP_LINK_INTEGRITY_FAILURE, 250 HDCP_REAUTH_REQUEST 251 }; 252 253 /* 254 * This structure serves as a translation layer between the generic HDCP code 255 * and the bus-specific code. What that means is that HDCP over HDMI differs 256 * from HDCP over DP, so to account for these differences, we need to 257 * communicate with the receiver through this shim. 258 * 259 * For completeness, the 2 buses differ in the following ways: 260 * - DP AUX vs. DDC 261 * HDCP registers on the receiver are set via DP AUX for DP, and 262 * they are set via DDC for HDMI. 263 * - Receiver register offsets 264 * The offsets of the registers are different for DP vs. HDMI 265 * - Receiver register masks/offsets 266 * For instance, the ready bit for the KSV fifo is in a different 267 * place on DP vs HDMI 268 * - Receiver register names 269 * Seriously. In the DP spec, the 16-bit register containing 270 * downstream information is called BINFO, on HDMI it's called 271 * BSTATUS. To confuse matters further, DP has a BSTATUS register 272 * with a completely different definition. 273 * - KSV FIFO 274 * On HDMI, the ksv fifo is read all at once, whereas on DP it must 275 * be read 3 keys at a time 276 * - Aksv output 277 * Since Aksv is hidden in hardware, there's different procedures 278 * to send it over DP AUX vs DDC 279 */ 280 struct intel_hdcp_shim { 281 /* Outputs the transmitter's An and Aksv values to the receiver. */ 282 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an); 283 284 /* Reads the receiver's key selection vector */ 285 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv); 286 287 /* 288 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The 289 * definitions are the same in the respective specs, but the names are 290 * different. Call it BSTATUS since that's the name the HDMI spec 291 * uses and it was there first. 292 */ 293 int (*read_bstatus)(struct intel_digital_port *intel_dig_port, 294 u8 *bstatus); 295 296 /* Determines whether a repeater is present downstream */ 297 int (*repeater_present)(struct intel_digital_port *intel_dig_port, 298 bool *repeater_present); 299 300 /* Reads the receiver's Ri' value */ 301 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri); 302 303 /* Determines if the receiver's KSV FIFO is ready for consumption */ 304 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port, 305 bool *ksv_ready); 306 307 /* Reads the ksv fifo for num_downstream devices */ 308 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port, 309 int num_downstream, u8 *ksv_fifo); 310 311 /* Reads a 32-bit part of V' from the receiver */ 312 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port, 313 int i, u32 *part); 314 315 /* Enables HDCP signalling on the port */ 316 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port, 317 bool enable); 318 319 /* Ensures the link is still protected */ 320 bool (*check_link)(struct intel_digital_port *intel_dig_port); 321 322 /* Detects panel's hdcp capability. This is optional for HDMI. */ 323 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port, 324 bool *hdcp_capable); 325 326 /* HDCP adaptation(DP/HDMI) required on the port */ 327 enum hdcp_wired_protocol protocol; 328 329 /* Detects whether sink is HDCP2.2 capable */ 330 int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port, 331 bool *capable); 332 333 /* Write HDCP2.2 messages */ 334 int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port, 335 void *buf, size_t size); 336 337 /* Read HDCP2.2 messages */ 338 int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port, 339 u8 msg_id, void *buf, size_t size); 340 341 /* 342 * Implementation of DP HDCP2.2 Errata for the communication of stream 343 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to 344 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI. 345 */ 346 int (*config_stream_type)(struct intel_digital_port *intel_dig_port, 347 bool is_repeater, u8 type); 348 349 /* HDCP2.2 Link Integrity Check */ 350 int (*check_2_2_link)(struct intel_digital_port *intel_dig_port); 351 }; 352 353 struct intel_hdcp { 354 const struct intel_hdcp_shim *shim; 355 /* Mutex for hdcp state of the connector */ 356 struct mutex mutex; 357 u64 value; 358 struct delayed_work check_work; 359 struct work_struct prop_work; 360 361 /* HDCP1.4 Encryption status */ 362 bool hdcp_encrypted; 363 364 /* HDCP2.2 related definitions */ 365 /* Flag indicates whether this connector supports HDCP2.2 or not. */ 366 bool hdcp2_supported; 367 368 /* HDCP2.2 Encryption status */ 369 bool hdcp2_encrypted; 370 371 /* 372 * Content Stream Type defined by content owner. TYPE0(0x0) content can 373 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1) 374 * content can flow only through a link protected by HDCP2.2. 375 */ 376 u8 content_type; 377 struct hdcp_port_data port_data; 378 379 bool is_paired; 380 bool is_repeater; 381 382 /* 383 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT. 384 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List. 385 * When it rolls over re-auth has to be triggered. 386 */ 387 u32 seq_num_v; 388 389 /* 390 * Count of RepeaterAuth_Stream_Manage msg propagated. 391 * Initialized to 0 on AKE_INIT. Incremented after every successful 392 * transmission of RepeaterAuth_Stream_Manage message. When it rolls 393 * over re-Auth has to be triggered. 394 */ 395 u32 seq_num_m; 396 397 /* 398 * Work queue to signal the CP_IRQ. Used for the waiters to read the 399 * available information from HDCP DP sink. 400 */ 401 wait_queue_head_t cp_irq_queue; 402 atomic_t cp_irq_count; 403 int cp_irq_count_cached; 404 405 /* 406 * HDCP register access for gen12+ need the transcoder associated. 407 * Transcoder attached to the connector could be changed at modeset. 408 * Hence caching the transcoder here. 409 */ 410 enum transcoder cpu_transcoder; 411 }; 412 413 struct intel_connector { 414 struct drm_connector base; 415 /* 416 * The fixed encoder this connector is connected to. 417 */ 418 struct intel_encoder *encoder; 419 420 /* ACPI device id for ACPI and driver cooperation */ 421 u32 acpi_device_id; 422 423 /* Reads out the current hw, returning true if the connector is enabled 424 * and active (i.e. dpms ON state). */ 425 bool (*get_hw_state)(struct intel_connector *); 426 427 /* Panel info for eDP and LVDS */ 428 struct intel_panel panel; 429 430 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 431 struct edid *edid; 432 struct edid *detect_edid; 433 434 /* Number of times hotplug detection was tried after an HPD interrupt */ 435 int hotplug_retries; 436 437 /* since POLL and HPD connectors may use the same HPD line keep the native 438 state of connector->polled in case hotplug storm detection changes it */ 439 u8 polled; 440 441 struct drm_dp_mst_port *port; 442 443 struct intel_dp *mst_port; 444 445 /* Work struct to schedule a uevent on link train failure */ 446 struct work_struct modeset_retry_work; 447 448 struct intel_hdcp hdcp; 449 }; 450 451 struct intel_digital_connector_state { 452 struct drm_connector_state base; 453 454 enum hdmi_force_audio force_audio; 455 int broadcast_rgb; 456 }; 457 458 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base) 459 460 struct dpll { 461 /* given values */ 462 int n; 463 int m1, m2; 464 int p1, p2; 465 /* derived values */ 466 int dot; 467 int vco; 468 int m; 469 int p; 470 }; 471 472 struct intel_atomic_state { 473 struct drm_atomic_state base; 474 475 intel_wakeref_t wakeref; 476 477 struct __intel_global_objs_state *global_objs; 478 int num_global_objs; 479 480 bool dpll_set, modeset; 481 482 /* 483 * Does this transaction change the pipes that are active? This mask 484 * tracks which CRTC's have changed their active state at the end of 485 * the transaction (not counting the temporary disable during modesets). 486 * This mask should only be non-zero when intel_state->modeset is true, 487 * but the converse is not necessarily true; simply changing a mode may 488 * not flip the final active status of any CRTC's 489 */ 490 u8 active_pipe_changes; 491 492 u8 active_pipes; 493 494 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; 495 496 /* 497 * Current watermarks can't be trusted during hardware readout, so 498 * don't bother calculating intermediate watermarks. 499 */ 500 bool skip_intermediate_wm; 501 502 bool rps_interactive; 503 504 /* 505 * active_pipes 506 */ 507 bool global_state_changed; 508 509 /* Number of enabled DBuf slices */ 510 u8 enabled_dbuf_slices_mask; 511 512 struct i915_sw_fence commit_ready; 513 514 struct llist_node freed; 515 }; 516 517 struct intel_plane_state { 518 struct drm_plane_state uapi; 519 520 /* 521 * actual hardware state, the state we program to the hardware. 522 * The following members are used to verify the hardware state: 523 * During initial hw readout, they need to be copied from uapi. 524 */ 525 struct { 526 struct drm_crtc *crtc; 527 struct drm_framebuffer *fb; 528 529 u16 alpha; 530 uint16_t pixel_blend_mode; 531 unsigned int rotation; 532 enum drm_color_encoding color_encoding; 533 enum drm_color_range color_range; 534 } hw; 535 536 struct i915_ggtt_view view; 537 struct i915_vma *vma; 538 unsigned long flags; 539 #define PLANE_HAS_FENCE BIT(0) 540 541 struct { 542 u32 offset; 543 /* 544 * Plane stride in: 545 * bytes for 0/180 degree rotation 546 * pixels for 90/270 degree rotation 547 */ 548 u32 stride; 549 int x, y; 550 } color_plane[4]; 551 552 /* plane control register */ 553 u32 ctl; 554 555 /* plane color control register */ 556 u32 color_ctl; 557 558 /* chroma upsampler control register */ 559 u32 cus_ctl; 560 561 /* 562 * scaler_id 563 * = -1 : not using a scaler 564 * >= 0 : using a scalers 565 * 566 * plane requiring a scaler: 567 * - During check_plane, its bit is set in 568 * crtc_state->scaler_state.scaler_users by calling helper function 569 * update_scaler_plane. 570 * - scaler_id indicates the scaler it got assigned. 571 * 572 * plane doesn't require a scaler: 573 * - this can happen when scaling is no more required or plane simply 574 * got disabled. 575 * - During check_plane, corresponding bit is reset in 576 * crtc_state->scaler_state.scaler_users by calling helper function 577 * update_scaler_plane. 578 */ 579 int scaler_id; 580 581 /* 582 * planar_linked_plane: 583 * 584 * ICL planar formats require 2 planes that are updated as pairs. 585 * This member is used to make sure the other plane is also updated 586 * when required, and for update_slave() to find the correct 587 * plane_state to pass as argument. 588 */ 589 struct intel_plane *planar_linked_plane; 590 591 /* 592 * planar_slave: 593 * If set don't update use the linked plane's state for updating 594 * this plane during atomic commit with the update_slave() callback. 595 * 596 * It's also used by the watermark code to ignore wm calculations on 597 * this plane. They're calculated by the linked plane's wm code. 598 */ 599 u32 planar_slave; 600 601 struct drm_intel_sprite_colorkey ckey; 602 }; 603 604 struct intel_initial_plane_config { 605 struct intel_framebuffer *fb; 606 struct i915_vma *vma; 607 unsigned int tiling; 608 int size; 609 u32 base; 610 u8 rotation; 611 }; 612 613 struct intel_scaler { 614 int in_use; 615 u32 mode; 616 }; 617 618 struct intel_crtc_scaler_state { 619 #define SKL_NUM_SCALERS 2 620 struct intel_scaler scalers[SKL_NUM_SCALERS]; 621 622 /* 623 * scaler_users: keeps track of users requesting scalers on this crtc. 624 * 625 * If a bit is set, a user is using a scaler. 626 * Here user can be a plane or crtc as defined below: 627 * bits 0-30 - plane (bit position is index from drm_plane_index) 628 * bit 31 - crtc 629 * 630 * Instead of creating a new index to cover planes and crtc, using 631 * existing drm_plane_index for planes which is well less than 31 632 * planes and bit 31 for crtc. This should be fine to cover all 633 * our platforms. 634 * 635 * intel_atomic_setup_scalers will setup available scalers to users 636 * requesting scalers. It will gracefully fail if request exceeds 637 * avilability. 638 */ 639 #define SKL_CRTC_INDEX 31 640 unsigned scaler_users; 641 642 /* scaler used by crtc for panel fitting purpose */ 643 int scaler_id; 644 }; 645 646 /* drm_mode->private_flags */ 647 #define I915_MODE_FLAG_INHERITED (1<<0) 648 /* Flag to get scanline using frame time stamps */ 649 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1) 650 /* Flag to use the scanline counter instead of the pixel counter */ 651 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2) 652 /* 653 * TE0 or TE1 flag is set if the crtc has a DSI encoder which 654 * is operating in command mode. 655 * Flag to use TE from DSI0 instead of VBI in command mode 656 */ 657 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3) 658 /* Flag to use TE from DSI1 instead of VBI in command mode */ 659 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4) 660 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */ 661 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5) 662 663 struct intel_wm_level { 664 bool enable; 665 u32 pri_val; 666 u32 spr_val; 667 u32 cur_val; 668 u32 fbc_val; 669 }; 670 671 struct intel_pipe_wm { 672 struct intel_wm_level wm[5]; 673 bool fbc_wm_enabled; 674 bool pipe_enabled; 675 bool sprites_enabled; 676 bool sprites_scaled; 677 }; 678 679 struct skl_wm_level { 680 u16 min_ddb_alloc; 681 u16 plane_res_b; 682 u8 plane_res_l; 683 bool plane_en; 684 bool ignore_lines; 685 }; 686 687 struct skl_plane_wm { 688 struct skl_wm_level wm[8]; 689 struct skl_wm_level uv_wm[8]; 690 struct skl_wm_level trans_wm; 691 struct skl_wm_level sagv_wm0; 692 bool is_planar; 693 }; 694 695 struct skl_pipe_wm { 696 struct skl_plane_wm planes[I915_MAX_PLANES]; 697 bool use_sagv_wm; 698 }; 699 700 enum vlv_wm_level { 701 VLV_WM_LEVEL_PM2, 702 VLV_WM_LEVEL_PM5, 703 VLV_WM_LEVEL_DDR_DVFS, 704 NUM_VLV_WM_LEVELS, 705 }; 706 707 struct vlv_wm_state { 708 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS]; 709 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS]; 710 u8 num_levels; 711 bool cxsr; 712 }; 713 714 struct vlv_fifo_state { 715 u16 plane[I915_MAX_PLANES]; 716 }; 717 718 enum g4x_wm_level { 719 G4X_WM_LEVEL_NORMAL, 720 G4X_WM_LEVEL_SR, 721 G4X_WM_LEVEL_HPLL, 722 NUM_G4X_WM_LEVELS, 723 }; 724 725 struct g4x_wm_state { 726 struct g4x_pipe_wm wm; 727 struct g4x_sr_wm sr; 728 struct g4x_sr_wm hpll; 729 bool cxsr; 730 bool hpll_en; 731 bool fbc_en; 732 }; 733 734 struct intel_crtc_wm_state { 735 union { 736 struct { 737 /* 738 * Intermediate watermarks; these can be 739 * programmed immediately since they satisfy 740 * both the current configuration we're 741 * switching away from and the new 742 * configuration we're switching to. 743 */ 744 struct intel_pipe_wm intermediate; 745 746 /* 747 * Optimal watermarks, programmed post-vblank 748 * when this state is committed. 749 */ 750 struct intel_pipe_wm optimal; 751 } ilk; 752 753 struct { 754 /* gen9+ only needs 1-step wm programming */ 755 struct skl_pipe_wm optimal; 756 struct skl_ddb_entry ddb; 757 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES]; 758 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES]; 759 } skl; 760 761 struct { 762 /* "raw" watermarks (not inverted) */ 763 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; 764 /* intermediate watermarks (inverted) */ 765 struct vlv_wm_state intermediate; 766 /* optimal watermarks (inverted) */ 767 struct vlv_wm_state optimal; 768 /* display FIFO split */ 769 struct vlv_fifo_state fifo_state; 770 } vlv; 771 772 struct { 773 /* "raw" watermarks */ 774 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS]; 775 /* intermediate watermarks */ 776 struct g4x_wm_state intermediate; 777 /* optimal watermarks */ 778 struct g4x_wm_state optimal; 779 } g4x; 780 }; 781 782 /* 783 * Platforms with two-step watermark programming will need to 784 * update watermark programming post-vblank to switch from the 785 * safe intermediate watermarks to the optimal final 786 * watermarks. 787 */ 788 bool need_postvbl_update; 789 }; 790 791 enum intel_output_format { 792 INTEL_OUTPUT_FORMAT_INVALID, 793 INTEL_OUTPUT_FORMAT_RGB, 794 INTEL_OUTPUT_FORMAT_YCBCR420, 795 INTEL_OUTPUT_FORMAT_YCBCR444, 796 }; 797 798 struct intel_crtc_state { 799 /* 800 * uapi (drm) state. This is the software state shown to userspace. 801 * In particular, the following members are used for bookkeeping: 802 * - crtc 803 * - state 804 * - *_changed 805 * - event 806 * - commit 807 * - mode_blob 808 */ 809 struct drm_crtc_state uapi; 810 811 /* 812 * actual hardware state, the state we program to the hardware. 813 * The following members are used to verify the hardware state: 814 * - enable 815 * - active 816 * - mode / adjusted_mode 817 * - color property blobs. 818 * 819 * During initial hw readout, they need to be copied to uapi. 820 */ 821 struct { 822 bool active, enable; 823 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; 824 struct drm_display_mode mode, adjusted_mode; 825 } hw; 826 827 /** 828 * quirks - bitfield with hw state readout quirks 829 * 830 * For various reasons the hw state readout code might not be able to 831 * completely faithfully read out the current state. These cases are 832 * tracked with quirk flags so that fastboot and state checker can act 833 * accordingly. 834 */ 835 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ 836 unsigned long quirks; 837 838 unsigned fb_bits; /* framebuffers to flip */ 839 bool update_pipe; /* can a fast modeset be performed? */ 840 bool disable_cxsr; 841 bool update_wm_pre, update_wm_post; /* watermarks are updated */ 842 bool fifo_changed; /* FIFO split is changed */ 843 bool preload_luts; 844 845 /* Pipe source size (ie. panel fitter input size) 846 * All planes will be positioned inside this space, 847 * and get clipped at the edges. */ 848 int pipe_src_w, pipe_src_h; 849 850 /* 851 * Pipe pixel rate, adjusted for 852 * panel fitter/pipe scaler downscaling. 853 */ 854 unsigned int pixel_rate; 855 856 /* Whether to set up the PCH/FDI. Note that we never allow sharing 857 * between pch encoders and cpu encoders. */ 858 bool has_pch_encoder; 859 860 /* Are we sending infoframes on the attached port */ 861 bool has_infoframe; 862 863 /* CPU Transcoder for the pipe. Currently this can only differ from the 864 * pipe on Haswell and later (where we have a special eDP transcoder) 865 * and Broxton (where we have special DSI transcoders). */ 866 enum transcoder cpu_transcoder; 867 868 /* 869 * Use reduced/limited/broadcast rbg range, compressing from the full 870 * range fed into the crtcs. 871 */ 872 bool limited_color_range; 873 874 /* Bitmask of encoder types (enum intel_output_type) 875 * driven by the pipe. 876 */ 877 unsigned int output_types; 878 879 /* Whether we should send NULL infoframes. Required for audio. */ 880 bool has_hdmi_sink; 881 882 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or 883 * has_dp_encoder is set. */ 884 bool has_audio; 885 886 /* 887 * Enable dithering, used when the selected pipe bpp doesn't match the 888 * plane bpp. 889 */ 890 bool dither; 891 892 /* 893 * Dither gets enabled for 18bpp which causes CRC mismatch errors for 894 * compliance video pattern tests. 895 * Disable dither only if it is a compliance test request for 896 * 18bpp. 897 */ 898 bool dither_force_disable; 899 900 /* Controls for the clock computation, to override various stages. */ 901 bool clock_set; 902 903 /* SDVO TV has a bunch of special case. To make multifunction encoders 904 * work correctly, we need to track this at runtime.*/ 905 bool sdvo_tv_clock; 906 907 /* 908 * crtc bandwidth limit, don't increase pipe bpp or clock if not really 909 * required. This is set in the 2nd loop of calling encoder's 910 * ->compute_config if the first pick doesn't work out. 911 */ 912 bool bw_constrained; 913 914 /* Settings for the intel dpll used on pretty much everything but 915 * haswell. */ 916 struct dpll dpll; 917 918 /* Selected dpll when shared or NULL. */ 919 struct intel_shared_dpll *shared_dpll; 920 921 /* Actual register state of the dpll, for shared dpll cross-checking. */ 922 struct intel_dpll_hw_state dpll_hw_state; 923 924 /* 925 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by 926 * setting shared_dpll and dpll_hw_state to one of these reserved ones. 927 */ 928 struct icl_port_dpll { 929 struct intel_shared_dpll *pll; 930 struct intel_dpll_hw_state hw_state; 931 } icl_port_dplls[ICL_PORT_DPLL_COUNT]; 932 933 /* DSI PLL registers */ 934 struct { 935 u32 ctrl, div; 936 } dsi_pll; 937 938 int pipe_bpp; 939 struct intel_link_m_n dp_m_n; 940 941 /* m2_n2 for eDP downclock */ 942 struct intel_link_m_n dp_m2_n2; 943 bool has_drrs; 944 945 bool has_psr; 946 bool has_psr2; 947 u32 dc3co_exitline; 948 949 /* 950 * Frequence the dpll for the port should run at. Differs from the 951 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also 952 * already multiplied by pixel_multiplier. 953 */ 954 int port_clock; 955 956 /* Used by SDVO (and if we ever fix it, HDMI). */ 957 unsigned pixel_multiplier; 958 959 u8 lane_count; 960 961 /* 962 * Used by platforms having DP/HDMI PHY with programmable lane 963 * latency optimization. 964 */ 965 u8 lane_lat_optim_mask; 966 967 /* minimum acceptable voltage level */ 968 u8 min_voltage_level; 969 970 /* Panel fitter controls for gen2-gen4 + VLV */ 971 struct { 972 u32 control; 973 u32 pgm_ratios; 974 u32 lvds_border_bits; 975 } gmch_pfit; 976 977 /* Panel fitter placement and size for Ironlake+ */ 978 struct { 979 struct drm_rect dst; 980 bool enabled; 981 bool force_thru; 982 } pch_pfit; 983 984 /* FDI configuration, only valid if has_pch_encoder is set. */ 985 int fdi_lanes; 986 struct intel_link_m_n fdi_m_n; 987 988 bool ips_enabled; 989 990 bool crc_enabled; 991 992 bool enable_fbc; 993 994 bool double_wide; 995 996 int pbn; 997 998 struct intel_crtc_scaler_state scaler_state; 999 1000 /* w/a for waiting 2 vblanks during crtc enable */ 1001 enum pipe hsw_workaround_pipe; 1002 1003 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ 1004 bool disable_lp_wm; 1005 1006 struct intel_crtc_wm_state wm; 1007 1008 int min_cdclk[I915_MAX_PLANES]; 1009 1010 u32 data_rate[I915_MAX_PLANES]; 1011 1012 /* Gamma mode programmed on the pipe */ 1013 u32 gamma_mode; 1014 1015 union { 1016 /* CSC mode programmed on the pipe */ 1017 u32 csc_mode; 1018 1019 /* CHV CGM mode */ 1020 u32 cgm_mode; 1021 }; 1022 1023 /* bitmask of visible planes (enum plane_id) */ 1024 u8 active_planes; 1025 u8 nv12_planes; 1026 u8 c8_planes; 1027 1028 /* bitmask of planes that will be updated during the commit */ 1029 u8 update_planes; 1030 1031 struct { 1032 u32 enable; 1033 u32 gcp; 1034 union hdmi_infoframe avi; 1035 union hdmi_infoframe spd; 1036 union hdmi_infoframe hdmi; 1037 union hdmi_infoframe drm; 1038 struct drm_dp_vsc_sdp vsc; 1039 } infoframes; 1040 1041 /* HDMI scrambling status */ 1042 bool hdmi_scrambling; 1043 1044 /* HDMI High TMDS char rate ratio */ 1045 bool hdmi_high_tmds_clock_ratio; 1046 1047 /* Output format RGB/YCBCR etc */ 1048 enum intel_output_format output_format; 1049 1050 /* Output down scaling is done in LSPCON device */ 1051 bool lspcon_downsampling; 1052 1053 /* enable pipe gamma? */ 1054 bool gamma_enable; 1055 1056 /* enable pipe csc? */ 1057 bool csc_enable; 1058 1059 /* Display Stream compression state */ 1060 struct { 1061 bool compression_enable; 1062 bool dsc_split; 1063 u16 compressed_bpp; 1064 u8 slice_count; 1065 struct drm_dsc_config config; 1066 } dsc; 1067 1068 /* HSW+ linetime watermarks */ 1069 u16 linetime; 1070 u16 ips_linetime; 1071 1072 /* Forward Error correction State */ 1073 bool fec_enable; 1074 1075 /* Pointer to master transcoder in case of tiled displays */ 1076 enum transcoder master_transcoder; 1077 1078 /* Bitmask to indicate slaves attached */ 1079 u8 sync_mode_slaves_mask; 1080 1081 /* Only valid on TGL+ */ 1082 enum transcoder mst_master_transcoder; 1083 }; 1084 1085 enum intel_pipe_crc_source { 1086 INTEL_PIPE_CRC_SOURCE_NONE, 1087 INTEL_PIPE_CRC_SOURCE_PLANE1, 1088 INTEL_PIPE_CRC_SOURCE_PLANE2, 1089 INTEL_PIPE_CRC_SOURCE_PLANE3, 1090 INTEL_PIPE_CRC_SOURCE_PLANE4, 1091 INTEL_PIPE_CRC_SOURCE_PLANE5, 1092 INTEL_PIPE_CRC_SOURCE_PLANE6, 1093 INTEL_PIPE_CRC_SOURCE_PLANE7, 1094 INTEL_PIPE_CRC_SOURCE_PIPE, 1095 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1096 INTEL_PIPE_CRC_SOURCE_TV, 1097 INTEL_PIPE_CRC_SOURCE_DP_B, 1098 INTEL_PIPE_CRC_SOURCE_DP_C, 1099 INTEL_PIPE_CRC_SOURCE_DP_D, 1100 INTEL_PIPE_CRC_SOURCE_AUTO, 1101 INTEL_PIPE_CRC_SOURCE_MAX, 1102 }; 1103 1104 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1105 struct intel_pipe_crc { 1106 spinlock_t lock; 1107 int skipped; 1108 enum intel_pipe_crc_source source; 1109 }; 1110 1111 struct intel_crtc { 1112 struct drm_crtc base; 1113 enum pipe pipe; 1114 /* 1115 * Whether the crtc and the connected output pipeline is active. Implies 1116 * that crtc->enabled is set, i.e. the current mode configuration has 1117 * some outputs connected to this crtc. 1118 */ 1119 bool active; 1120 u8 plane_ids_mask; 1121 unsigned long long enabled_power_domains; 1122 struct intel_overlay *overlay; 1123 1124 struct intel_crtc_state *config; 1125 1126 /* Access to these should be protected by dev_priv->irq_lock. */ 1127 bool cpu_fifo_underrun_disabled; 1128 bool pch_fifo_underrun_disabled; 1129 1130 /* per-pipe watermark state */ 1131 struct { 1132 /* watermarks currently being used */ 1133 union { 1134 struct intel_pipe_wm ilk; 1135 struct vlv_wm_state vlv; 1136 struct g4x_wm_state g4x; 1137 } active; 1138 } wm; 1139 1140 int scanline_offset; 1141 1142 struct { 1143 unsigned start_vbl_count; 1144 ktime_t start_vbl_time; 1145 int min_vbl, max_vbl; 1146 int scanline_start; 1147 } debug; 1148 1149 /* scalers available on this crtc */ 1150 int num_scalers; 1151 1152 /* per pipe DSB related info */ 1153 struct intel_dsb dsb; 1154 1155 #ifdef CONFIG_DEBUG_FS 1156 struct intel_pipe_crc pipe_crc; 1157 #endif 1158 }; 1159 1160 struct intel_plane { 1161 struct drm_plane base; 1162 enum i9xx_plane_id i9xx_plane; 1163 enum plane_id id; 1164 enum pipe pipe; 1165 bool has_fbc; 1166 bool has_ccs; 1167 u32 frontbuffer_bit; 1168 1169 struct { 1170 u32 base, cntl, size; 1171 } cursor; 1172 1173 /* 1174 * NOTE: Do not place new plane state fields here (e.g., when adding 1175 * new plane properties). New runtime state should now be placed in 1176 * the intel_plane_state structure and accessed via plane_state. 1177 */ 1178 1179 unsigned int (*max_stride)(struct intel_plane *plane, 1180 u32 pixel_format, u64 modifier, 1181 unsigned int rotation); 1182 void (*update_plane)(struct intel_plane *plane, 1183 const struct intel_crtc_state *crtc_state, 1184 const struct intel_plane_state *plane_state); 1185 void (*disable_plane)(struct intel_plane *plane, 1186 const struct intel_crtc_state *crtc_state); 1187 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe); 1188 int (*check_plane)(struct intel_crtc_state *crtc_state, 1189 struct intel_plane_state *plane_state); 1190 int (*min_cdclk)(const struct intel_crtc_state *crtc_state, 1191 const struct intel_plane_state *plane_state); 1192 }; 1193 1194 struct intel_watermark_params { 1195 u16 fifo_size; 1196 u16 max_wm; 1197 u8 default_wm; 1198 u8 guard_size; 1199 u8 cacheline_size; 1200 }; 1201 1202 struct cxsr_latency { 1203 bool is_desktop : 1; 1204 bool is_ddr3 : 1; 1205 u16 fsb_freq; 1206 u16 mem_freq; 1207 u16 display_sr; 1208 u16 display_hpll_disable; 1209 u16 cursor_sr; 1210 u16 cursor_hpll_disable; 1211 }; 1212 1213 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) 1214 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 1215 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi) 1216 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 1217 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 1218 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 1219 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 1220 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi) 1221 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL) 1222 1223 struct intel_hdmi { 1224 i915_reg_t hdmi_reg; 1225 int ddc_bus; 1226 struct { 1227 enum drm_dp_dual_mode_type type; 1228 int max_tmds_clock; 1229 } dp_dual_mode; 1230 bool has_hdmi_sink; 1231 bool has_audio; 1232 struct intel_connector *attached_connector; 1233 struct cec_notifier *cec_notifier; 1234 }; 1235 1236 struct intel_dp_mst_encoder; 1237 /* 1238 * enum link_m_n_set: 1239 * When platform provides two set of M_N registers for dp, we can 1240 * program them and switch between them incase of DRRS. 1241 * But When only one such register is provided, we have to program the 1242 * required divider value on that registers itself based on the DRRS state. 1243 * 1244 * M1_N1 : Program dp_m_n on M1_N1 registers 1245 * dp_m2_n2 on M2_N2 registers (If supported) 1246 * 1247 * M2_N2 : Program dp_m2_n2 on M1_N1 registers 1248 * M2_N2 registers are not supported 1249 */ 1250 1251 enum link_m_n_set { 1252 /* Sets the m1_n1 and m2_n2 */ 1253 M1_N1 = 0, 1254 M2_N2 1255 }; 1256 1257 struct intel_dp_compliance_data { 1258 unsigned long edid; 1259 u8 video_pattern; 1260 u16 hdisplay, vdisplay; 1261 u8 bpc; 1262 struct drm_dp_phy_test_params phytest; 1263 }; 1264 1265 struct intel_dp_compliance { 1266 unsigned long test_type; 1267 struct intel_dp_compliance_data test_data; 1268 bool test_active; 1269 int test_link_rate; 1270 u8 test_lane_count; 1271 }; 1272 1273 struct intel_dp { 1274 i915_reg_t output_reg; 1275 u32 DP; 1276 int link_rate; 1277 u8 lane_count; 1278 u8 sink_count; 1279 bool link_mst; 1280 bool link_trained; 1281 bool has_audio; 1282 bool reset_link_params; 1283 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 1284 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 1285 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 1286 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; 1287 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; 1288 u8 fec_capable; 1289 /* source rates */ 1290 int num_source_rates; 1291 const int *source_rates; 1292 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */ 1293 int num_sink_rates; 1294 int sink_rates[DP_MAX_SUPPORTED_RATES]; 1295 bool use_rate_select; 1296 /* intersection of source and sink rates */ 1297 int num_common_rates; 1298 int common_rates[DP_MAX_SUPPORTED_RATES]; 1299 /* Max lane count for the current link */ 1300 int max_link_lane_count; 1301 /* Max rate for the current link */ 1302 int max_link_rate; 1303 /* sink or branch descriptor */ 1304 struct drm_dp_desc desc; 1305 u32 edid_quirks; 1306 struct drm_dp_aux aux; 1307 u32 aux_busy_last_status; 1308 u8 train_set[4]; 1309 int panel_power_up_delay; 1310 int panel_power_down_delay; 1311 int panel_power_cycle_delay; 1312 int backlight_on_delay; 1313 int backlight_off_delay; 1314 struct delayed_work panel_vdd_work; 1315 bool want_panel_vdd; 1316 unsigned long last_power_on; 1317 unsigned long last_backlight_off; 1318 ktime_t panel_power_off_time; 1319 1320 struct notifier_block edp_notifier; 1321 1322 /* 1323 * Pipe whose power sequencer is currently locked into 1324 * this port. Only relevant on VLV/CHV. 1325 */ 1326 enum pipe pps_pipe; 1327 /* 1328 * Pipe currently driving the port. Used for preventing 1329 * the use of the PPS for any pipe currentrly driving 1330 * external DP as that will mess things up on VLV. 1331 */ 1332 enum pipe active_pipe; 1333 /* 1334 * Set if the sequencer may be reset due to a power transition, 1335 * requiring a reinitialization. Only relevant on BXT. 1336 */ 1337 bool pps_reset; 1338 struct edp_power_seq pps_delays; 1339 1340 bool can_mst; /* this port supports mst */ 1341 bool is_mst; 1342 int active_mst_links; 1343 1344 /* 1345 * DP_TP_* registers may be either on port or transcoder register space. 1346 */ 1347 struct { 1348 i915_reg_t dp_tp_ctl; 1349 i915_reg_t dp_tp_status; 1350 } regs; 1351 1352 /* connector directly attached - won't be use for modeset in mst world */ 1353 struct intel_connector *attached_connector; 1354 1355 /* mst connector list */ 1356 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; 1357 struct drm_dp_mst_topology_mgr mst_mgr; 1358 1359 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index); 1360 /* 1361 * This function returns the value we have to program the AUX_CTL 1362 * register with to kick off an AUX transaction. 1363 */ 1364 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes, 1365 u32 aux_clock_divider); 1366 1367 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); 1368 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); 1369 1370 /* This is called before a link training is starterd */ 1371 void (*prepare_link_retrain)(struct intel_dp *intel_dp); 1372 void (*set_link_train)(struct intel_dp *intel_dp, u8 dp_train_pat); 1373 void (*set_idle_link_train)(struct intel_dp *intel_dp); 1374 void (*set_signal_levels)(struct intel_dp *intel_dp); 1375 1376 /* Displayport compliance testing */ 1377 struct intel_dp_compliance compliance; 1378 1379 /* Display stream compression testing */ 1380 bool force_dsc_en; 1381 }; 1382 1383 enum lspcon_vendor { 1384 LSPCON_VENDOR_MCA, 1385 LSPCON_VENDOR_PARADE 1386 }; 1387 1388 struct intel_lspcon { 1389 bool active; 1390 enum drm_lspcon_mode mode; 1391 enum lspcon_vendor vendor; 1392 }; 1393 1394 struct intel_digital_port { 1395 struct intel_encoder base; 1396 u32 saved_port_bits; 1397 struct intel_dp dp; 1398 struct intel_hdmi hdmi; 1399 struct intel_lspcon lspcon; 1400 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); 1401 bool release_cl2_override; 1402 u8 max_lanes; 1403 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */ 1404 enum aux_ch aux_ch; 1405 enum intel_display_power_domain ddi_io_power_domain; 1406 struct mutex tc_lock; /* protects the TypeC port mode */ 1407 intel_wakeref_t tc_lock_wakeref; 1408 int tc_link_refcount; 1409 bool tc_legacy_port:1; 1410 char tc_port_name[8]; 1411 enum tc_port_mode tc_mode; 1412 enum phy_fia tc_phy_fia; 1413 u8 tc_phy_fia_idx; 1414 1415 void (*write_infoframe)(struct intel_encoder *encoder, 1416 const struct intel_crtc_state *crtc_state, 1417 unsigned int type, 1418 const void *frame, ssize_t len); 1419 void (*read_infoframe)(struct intel_encoder *encoder, 1420 const struct intel_crtc_state *crtc_state, 1421 unsigned int type, 1422 void *frame, ssize_t len); 1423 void (*set_infoframes)(struct intel_encoder *encoder, 1424 bool enable, 1425 const struct intel_crtc_state *crtc_state, 1426 const struct drm_connector_state *conn_state); 1427 u32 (*infoframes_enabled)(struct intel_encoder *encoder, 1428 const struct intel_crtc_state *pipe_config); 1429 bool (*connected)(struct intel_encoder *encoder); 1430 }; 1431 1432 struct intel_dp_mst_encoder { 1433 struct intel_encoder base; 1434 enum pipe pipe; 1435 struct intel_digital_port *primary; 1436 struct intel_connector *connector; 1437 }; 1438 1439 static inline enum dpio_channel 1440 vlv_dport_to_channel(struct intel_digital_port *dport) 1441 { 1442 switch (dport->base.port) { 1443 case PORT_B: 1444 case PORT_D: 1445 return DPIO_CH0; 1446 case PORT_C: 1447 return DPIO_CH1; 1448 default: 1449 BUG(); 1450 } 1451 } 1452 1453 static inline enum dpio_phy 1454 vlv_dport_to_phy(struct intel_digital_port *dport) 1455 { 1456 switch (dport->base.port) { 1457 case PORT_B: 1458 case PORT_C: 1459 return DPIO_PHY0; 1460 case PORT_D: 1461 return DPIO_PHY1; 1462 default: 1463 BUG(); 1464 } 1465 } 1466 1467 static inline enum dpio_channel 1468 vlv_pipe_to_channel(enum pipe pipe) 1469 { 1470 switch (pipe) { 1471 case PIPE_A: 1472 case PIPE_C: 1473 return DPIO_CH0; 1474 case PIPE_B: 1475 return DPIO_CH1; 1476 default: 1477 BUG(); 1478 } 1479 } 1480 1481 static inline struct intel_crtc * 1482 intel_get_first_crtc(struct drm_i915_private *dev_priv) 1483 { 1484 return to_intel_crtc(drm_crtc_from_index(&dev_priv->drm, 0)); 1485 } 1486 1487 static inline struct intel_crtc * 1488 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 1489 { 1490 /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */ 1491 drm_WARN_ON(&dev_priv->drm, 1492 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe))); 1493 return dev_priv->pipe_to_crtc_mapping[pipe]; 1494 } 1495 1496 static inline struct intel_crtc * 1497 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane) 1498 { 1499 return dev_priv->plane_to_crtc_mapping[plane]; 1500 } 1501 1502 struct intel_load_detect_pipe { 1503 struct drm_atomic_state *restore_state; 1504 }; 1505 1506 static inline struct intel_encoder * 1507 intel_attached_encoder(struct intel_connector *connector) 1508 { 1509 return connector->encoder; 1510 } 1511 1512 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder) 1513 { 1514 switch (encoder->type) { 1515 case INTEL_OUTPUT_DDI: 1516 case INTEL_OUTPUT_DP: 1517 case INTEL_OUTPUT_EDP: 1518 case INTEL_OUTPUT_HDMI: 1519 return true; 1520 default: 1521 return false; 1522 } 1523 } 1524 1525 static inline struct intel_digital_port * 1526 enc_to_dig_port(struct intel_encoder *encoder) 1527 { 1528 struct intel_encoder *intel_encoder = encoder; 1529 1530 if (intel_encoder_is_dig_port(intel_encoder)) 1531 return container_of(&encoder->base, struct intel_digital_port, 1532 base.base); 1533 else 1534 return NULL; 1535 } 1536 1537 static inline struct intel_digital_port * 1538 intel_attached_dig_port(struct intel_connector *connector) 1539 { 1540 return enc_to_dig_port(intel_attached_encoder(connector)); 1541 } 1542 1543 static inline struct intel_dp_mst_encoder * 1544 enc_to_mst(struct intel_encoder *encoder) 1545 { 1546 return container_of(&encoder->base, struct intel_dp_mst_encoder, 1547 base.base); 1548 } 1549 1550 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder) 1551 { 1552 return &enc_to_dig_port(encoder)->dp; 1553 } 1554 1555 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector) 1556 { 1557 return enc_to_intel_dp(intel_attached_encoder(connector)); 1558 } 1559 1560 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) 1561 { 1562 switch (encoder->type) { 1563 case INTEL_OUTPUT_DP: 1564 case INTEL_OUTPUT_EDP: 1565 return true; 1566 case INTEL_OUTPUT_DDI: 1567 /* Skip pure HDMI/DVI DDI encoders */ 1568 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg); 1569 default: 1570 return false; 1571 } 1572 } 1573 1574 static inline struct intel_lspcon * 1575 enc_to_intel_lspcon(struct intel_encoder *encoder) 1576 { 1577 return &enc_to_dig_port(encoder)->lspcon; 1578 } 1579 1580 static inline struct intel_digital_port * 1581 dp_to_dig_port(struct intel_dp *intel_dp) 1582 { 1583 return container_of(intel_dp, struct intel_digital_port, dp); 1584 } 1585 1586 static inline struct intel_lspcon * 1587 dp_to_lspcon(struct intel_dp *intel_dp) 1588 { 1589 return &dp_to_dig_port(intel_dp)->lspcon; 1590 } 1591 1592 static inline struct drm_i915_private * 1593 dp_to_i915(struct intel_dp *intel_dp) 1594 { 1595 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 1596 } 1597 1598 static inline struct intel_digital_port * 1599 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 1600 { 1601 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 1602 } 1603 1604 static inline struct intel_plane_state * 1605 intel_atomic_get_plane_state(struct intel_atomic_state *state, 1606 struct intel_plane *plane) 1607 { 1608 struct drm_plane_state *ret = 1609 drm_atomic_get_plane_state(&state->base, &plane->base); 1610 1611 if (IS_ERR(ret)) 1612 return ERR_CAST(ret); 1613 1614 return to_intel_plane_state(ret); 1615 } 1616 1617 static inline struct intel_plane_state * 1618 intel_atomic_get_old_plane_state(struct intel_atomic_state *state, 1619 struct intel_plane *plane) 1620 { 1621 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base, 1622 &plane->base)); 1623 } 1624 1625 static inline struct intel_plane_state * 1626 intel_atomic_get_new_plane_state(struct intel_atomic_state *state, 1627 struct intel_plane *plane) 1628 { 1629 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base, 1630 &plane->base)); 1631 } 1632 1633 static inline struct intel_crtc_state * 1634 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state, 1635 struct intel_crtc *crtc) 1636 { 1637 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base, 1638 &crtc->base)); 1639 } 1640 1641 static inline struct intel_crtc_state * 1642 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state, 1643 struct intel_crtc *crtc) 1644 { 1645 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, 1646 &crtc->base)); 1647 } 1648 1649 static inline struct intel_digital_connector_state * 1650 intel_atomic_get_new_connector_state(struct intel_atomic_state *state, 1651 struct intel_connector *connector) 1652 { 1653 return to_intel_digital_connector_state( 1654 drm_atomic_get_new_connector_state(&state->base, 1655 &connector->base)); 1656 } 1657 1658 static inline struct intel_digital_connector_state * 1659 intel_atomic_get_old_connector_state(struct intel_atomic_state *state, 1660 struct intel_connector *connector) 1661 { 1662 return to_intel_digital_connector_state( 1663 drm_atomic_get_old_connector_state(&state->base, 1664 &connector->base)); 1665 } 1666 1667 /* intel_display.c */ 1668 static inline bool 1669 intel_crtc_has_type(const struct intel_crtc_state *crtc_state, 1670 enum intel_output_type type) 1671 { 1672 return crtc_state->output_types & (1 << type); 1673 } 1674 static inline bool 1675 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) 1676 { 1677 return crtc_state->output_types & 1678 ((1 << INTEL_OUTPUT_DP) | 1679 (1 << INTEL_OUTPUT_DP_MST) | 1680 (1 << INTEL_OUTPUT_EDP)); 1681 } 1682 1683 static inline void 1684 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) 1685 { 1686 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1687 1688 drm_crtc_wait_one_vblank(&crtc->base); 1689 } 1690 1691 static inline void 1692 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe) 1693 { 1694 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1695 1696 if (crtc->active) 1697 intel_wait_for_vblank(dev_priv, pipe); 1698 } 1699 1700 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state) 1701 { 1702 return i915_ggtt_offset(state->vma); 1703 } 1704 1705 #endif /* __INTEL_DISPLAY_TYPES_H__ */ 1706