1e563531aSJani Nikula /* SPDX-License-Identifier: MIT */ 2e563531aSJani Nikula /* 3e563531aSJani Nikula * Copyright © 2022 Intel Corporation 4e563531aSJani Nikula */ 5e563531aSJani Nikula 6e563531aSJani Nikula #ifndef __INTEL_DISPLAY_REG_DEFS_H__ 7e563531aSJani Nikula #define __INTEL_DISPLAY_REG_DEFS_H__ 8e563531aSJani Nikula 9e563531aSJani Nikula #include "i915_reg_defs.h" 10e563531aSJani Nikula 11*5af5169dSMatt Roper #define DISPLAY_MMIO_BASE(dev_priv) (DISPLAY_INFO(dev_priv)->mmio_offset) 12e563531aSJani Nikula 13e563531aSJani Nikula #define VLV_DISPLAY_BASE 0x180000 14e563531aSJani Nikula 15e563531aSJani Nikula /* 16f3783aa6SLucas De Marchi * Named helper wrappers around _PICK_EVEN() and _PICK_EVEN_2RANGES(). 17e563531aSJani Nikula */ 18e563531aSJani Nikula #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) 19e563531aSJani Nikula #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) 20e563531aSJani Nikula #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) 21e563531aSJani Nikula #define _PORT(port, a, b) _PICK_EVEN(port, a, b) 22e563531aSJani Nikula #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) 23e563531aSJani Nikula #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) 24e563531aSJani Nikula 25e563531aSJani Nikula #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 26e563531aSJani Nikula #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) 27e563531aSJani Nikula #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 28e563531aSJani Nikula #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 29e563531aSJani Nikula #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 30e563531aSJani Nikula #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) 31e563531aSJani Nikula 32f3783aa6SLucas De Marchi #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)) 33f3783aa6SLucas De Marchi #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)) 34e563531aSJani Nikula 35e563531aSJani Nikula /* 36e563531aSJani Nikula * Device info offset array based helpers for groups of registers with unevenly 37e563531aSJani Nikula * spaced base offsets. 38e563531aSJani Nikula */ 39*5af5169dSMatt Roper #define _MMIO_PIPE2(pipe, reg) _MMIO(DISPLAY_INFO(dev_priv)->pipe_offsets[(pipe)] - \ 40*5af5169dSMatt Roper DISPLAY_INFO(dev_priv)->pipe_offsets[PIPE_A] + \ 41e563531aSJani Nikula DISPLAY_MMIO_BASE(dev_priv) + (reg)) 42*5af5169dSMatt Roper #define _MMIO_TRANS2(tran, reg) _MMIO(DISPLAY_INFO(dev_priv)->trans_offsets[(tran)] - \ 43*5af5169dSMatt Roper DISPLAY_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + \ 44e563531aSJani Nikula DISPLAY_MMIO_BASE(dev_priv) + (reg)) 45*5af5169dSMatt Roper #define _MMIO_CURSOR2(pipe, reg) _MMIO(DISPLAY_INFO(dev_priv)->cursor_offsets[(pipe)] - \ 46*5af5169dSMatt Roper DISPLAY_INFO(dev_priv)->cursor_offsets[PIPE_A] + \ 47e563531aSJani Nikula DISPLAY_MMIO_BASE(dev_priv) + (reg)) 48e563531aSJani Nikula 49e563531aSJani Nikula #endif /* __INTEL_DISPLAY_REG_DEFS_H__ */ 50