1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 #ifndef __INTEL_DISPLAY_POWER_WELL_H__
6 #define __INTEL_DISPLAY_POWER_WELL_H__
7 
8 #include <linux/types.h>
9 
10 #include "intel_display.h"
11 
12 struct drm_i915_private;
13 struct i915_power_well;
14 
15 /*
16  * i915_power_well_id:
17  *
18  * IDs used to look up power wells. Power wells accessed directly bypassing
19  * the power domains framework must be assigned a unique ID. The rest of power
20  * wells must be assigned DISP_PW_ID_NONE.
21  */
22 enum i915_power_well_id {
23 	DISP_PW_ID_NONE,
24 
25 	VLV_DISP_PW_DISP2D,
26 	BXT_DISP_PW_DPIO_CMN_A,
27 	VLV_DISP_PW_DPIO_CMN_BC,
28 	GLK_DISP_PW_DPIO_CMN_C,
29 	CHV_DISP_PW_DPIO_CMN_D,
30 	HSW_DISP_PW_GLOBAL,
31 	SKL_DISP_PW_MISC_IO,
32 	SKL_DISP_PW_1,
33 	SKL_DISP_PW_2,
34 	ICL_DISP_PW_3,
35 	SKL_DISP_DC_OFF,
36 	TGL_DISP_PW_TC_COLD_OFF,
37 };
38 
39 struct i915_power_well_regs {
40 	i915_reg_t bios;
41 	i915_reg_t driver;
42 	i915_reg_t kvmr;
43 	i915_reg_t debug;
44 };
45 
46 struct i915_power_well_ops {
47 	const struct i915_power_well_regs *regs;
48 	/*
49 	 * Synchronize the well's hw state to match the current sw state, for
50 	 * example enable/disable it based on the current refcount. Called
51 	 * during driver init and resume time, possibly after first calling
52 	 * the enable/disable handlers.
53 	 */
54 	void (*sync_hw)(struct drm_i915_private *i915,
55 			struct i915_power_well *power_well);
56 	/*
57 	 * Enable the well and resources that depend on it (for example
58 	 * interrupts located on the well). Called after the 0->1 refcount
59 	 * transition.
60 	 */
61 	void (*enable)(struct drm_i915_private *i915,
62 		       struct i915_power_well *power_well);
63 	/*
64 	 * Disable the well and resources that depend on it. Called after
65 	 * the 1->0 refcount transition.
66 	 */
67 	void (*disable)(struct drm_i915_private *i915,
68 			struct i915_power_well *power_well);
69 	/* Returns the hw enabled state. */
70 	bool (*is_enabled)(struct drm_i915_private *i915,
71 			   struct i915_power_well *power_well);
72 };
73 
74 struct i915_power_well_desc {
75 	const char *name;
76 	bool always_on;
77 	u64 domains;
78 	/* unique identifier for this power well */
79 	enum i915_power_well_id id;
80 	/*
81 	 * Arbitraty data associated with this power well. Platform and power
82 	 * well specific.
83 	 */
84 	union {
85 		struct {
86 			/*
87 			 * request/status flag index in the PUNIT power well
88 			 * control/status registers.
89 			 */
90 			u8 idx;
91 		} vlv;
92 		struct {
93 			enum dpio_phy phy;
94 		} bxt;
95 		struct {
96 			/*
97 			 * request/status flag index in the power well
98 			 * constrol/status registers.
99 			 */
100 			u8 idx;
101 			/* Mask of pipes whose IRQ logic is backed by the pw */
102 			u8 irq_pipe_mask;
103 			/*
104 			 * Instead of waiting for the status bit to ack enables,
105 			 * just wait a specific amount of time and then consider
106 			 * the well enabled.
107 			 */
108 			u16 fixed_enable_delay;
109 			/* The pw is backing the VGA functionality */
110 			bool has_vga:1;
111 			bool has_fuses:1;
112 			/*
113 			 * The pw is for an ICL+ TypeC PHY port in
114 			 * Thunderbolt mode.
115 			 */
116 			bool is_tc_tbt:1;
117 		} hsw;
118 	};
119 	const struct i915_power_well_ops *ops;
120 };
121 
122 struct i915_power_well {
123 	const struct i915_power_well_desc *desc;
124 	/* power well enable/disable usage count */
125 	int count;
126 	/* cached hw enabled state */
127 	bool hw_enabled;
128 };
129 
130 struct i915_power_well *lookup_power_well(struct drm_i915_private *i915,
131 					  enum i915_power_well_id id);
132 
133 void intel_power_well_enable(struct drm_i915_private *i915,
134 			     struct i915_power_well *power_well);
135 void intel_power_well_disable(struct drm_i915_private *i915,
136 			      struct i915_power_well *power_well);
137 void intel_power_well_sync_hw(struct drm_i915_private *i915,
138 			      struct i915_power_well *power_well);
139 void intel_power_well_get(struct drm_i915_private *i915,
140 			  struct i915_power_well *power_well);
141 void intel_power_well_put(struct drm_i915_private *i915,
142 			  struct i915_power_well *power_well);
143 bool intel_power_well_is_enabled(struct drm_i915_private *i915,
144 				 struct i915_power_well *power_well);
145 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well);
146 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
147 					 enum i915_power_well_id power_well_id);
148 bool intel_power_well_is_always_on(struct i915_power_well *power_well);
149 const char *intel_power_well_name(struct i915_power_well *power_well);
150 u64 intel_power_well_domains(struct i915_power_well *power_well);
151 int intel_power_well_refcount(struct i915_power_well *power_well);
152 
153 #endif
154