1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_irq.h" 8 #include "intel_backlight_regs.h" 9 #include "intel_combo_phy.h" 10 #include "intel_combo_phy_regs.h" 11 #include "intel_crt.h" 12 #include "intel_de.h" 13 #include "intel_display_power_well.h" 14 #include "intel_display_types.h" 15 #include "intel_dkl_phy.h" 16 #include "intel_dkl_phy_regs.h" 17 #include "intel_dmc.h" 18 #include "intel_dpio_phy.h" 19 #include "intel_dpll.h" 20 #include "intel_hotplug.h" 21 #include "intel_pcode.h" 22 #include "intel_pps.h" 23 #include "intel_tc.h" 24 #include "intel_vga.h" 25 #include "skl_watermark.h" 26 #include "vlv_sideband.h" 27 #include "vlv_sideband_reg.h" 28 29 struct i915_power_well_regs { 30 i915_reg_t bios; 31 i915_reg_t driver; 32 i915_reg_t kvmr; 33 i915_reg_t debug; 34 }; 35 36 struct i915_power_well_ops { 37 const struct i915_power_well_regs *regs; 38 /* 39 * Synchronize the well's hw state to match the current sw state, for 40 * example enable/disable it based on the current refcount. Called 41 * during driver init and resume time, possibly after first calling 42 * the enable/disable handlers. 43 */ 44 void (*sync_hw)(struct drm_i915_private *i915, 45 struct i915_power_well *power_well); 46 /* 47 * Enable the well and resources that depend on it (for example 48 * interrupts located on the well). Called after the 0->1 refcount 49 * transition. 50 */ 51 void (*enable)(struct drm_i915_private *i915, 52 struct i915_power_well *power_well); 53 /* 54 * Disable the well and resources that depend on it. Called after 55 * the 1->0 refcount transition. 56 */ 57 void (*disable)(struct drm_i915_private *i915, 58 struct i915_power_well *power_well); 59 /* Returns the hw enabled state. */ 60 bool (*is_enabled)(struct drm_i915_private *i915, 61 struct i915_power_well *power_well); 62 }; 63 64 static const struct i915_power_well_instance * 65 i915_power_well_instance(const struct i915_power_well *power_well) 66 { 67 return &power_well->desc->instances->list[power_well->instance_idx]; 68 } 69 70 struct i915_power_well * 71 lookup_power_well(struct drm_i915_private *i915, 72 enum i915_power_well_id power_well_id) 73 { 74 struct i915_power_well *power_well; 75 76 for_each_power_well(i915, power_well) 77 if (i915_power_well_instance(power_well)->id == power_well_id) 78 return power_well; 79 80 /* 81 * It's not feasible to add error checking code to the callers since 82 * this condition really shouldn't happen and it doesn't even make sense 83 * to abort things like display initialization sequences. Just return 84 * the first power well and hope the WARN gets reported so we can fix 85 * our driver. 86 */ 87 drm_WARN(&i915->drm, 1, 88 "Power well %d not defined for this platform\n", 89 power_well_id); 90 return &i915->display.power.domains.power_wells[0]; 91 } 92 93 void intel_power_well_enable(struct drm_i915_private *i915, 94 struct i915_power_well *power_well) 95 { 96 drm_dbg_kms(&i915->drm, "enabling %s\n", intel_power_well_name(power_well)); 97 power_well->desc->ops->enable(i915, power_well); 98 power_well->hw_enabled = true; 99 } 100 101 void intel_power_well_disable(struct drm_i915_private *i915, 102 struct i915_power_well *power_well) 103 { 104 drm_dbg_kms(&i915->drm, "disabling %s\n", intel_power_well_name(power_well)); 105 power_well->hw_enabled = false; 106 power_well->desc->ops->disable(i915, power_well); 107 } 108 109 void intel_power_well_sync_hw(struct drm_i915_private *i915, 110 struct i915_power_well *power_well) 111 { 112 power_well->desc->ops->sync_hw(i915, power_well); 113 power_well->hw_enabled = 114 power_well->desc->ops->is_enabled(i915, power_well); 115 } 116 117 void intel_power_well_get(struct drm_i915_private *i915, 118 struct i915_power_well *power_well) 119 { 120 if (!power_well->count++) 121 intel_power_well_enable(i915, power_well); 122 } 123 124 void intel_power_well_put(struct drm_i915_private *i915, 125 struct i915_power_well *power_well) 126 { 127 drm_WARN(&i915->drm, !power_well->count, 128 "Use count on power well %s is already zero", 129 i915_power_well_instance(power_well)->name); 130 131 if (!--power_well->count) 132 intel_power_well_disable(i915, power_well); 133 } 134 135 bool intel_power_well_is_enabled(struct drm_i915_private *i915, 136 struct i915_power_well *power_well) 137 { 138 return power_well->desc->ops->is_enabled(i915, power_well); 139 } 140 141 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well) 142 { 143 return power_well->hw_enabled; 144 } 145 146 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 147 enum i915_power_well_id power_well_id) 148 { 149 struct i915_power_well *power_well; 150 151 power_well = lookup_power_well(dev_priv, power_well_id); 152 153 return intel_power_well_is_enabled(dev_priv, power_well); 154 } 155 156 bool intel_power_well_is_always_on(struct i915_power_well *power_well) 157 { 158 return power_well->desc->always_on; 159 } 160 161 const char *intel_power_well_name(struct i915_power_well *power_well) 162 { 163 return i915_power_well_instance(power_well)->name; 164 } 165 166 struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well) 167 { 168 return &power_well->domains; 169 } 170 171 int intel_power_well_refcount(struct i915_power_well *power_well) 172 { 173 return power_well->count; 174 } 175 176 /* 177 * Starting with Haswell, we have a "Power Down Well" that can be turned off 178 * when not needed anymore. We have 4 registers that can request the power well 179 * to be enabled, and it will only be disabled if none of the registers is 180 * requesting it to be enabled. 181 */ 182 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, 183 u8 irq_pipe_mask, bool has_vga) 184 { 185 if (has_vga) 186 intel_vga_reset_io_mem(dev_priv); 187 188 if (irq_pipe_mask) 189 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); 190 } 191 192 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, 193 u8 irq_pipe_mask) 194 { 195 if (irq_pipe_mask) 196 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); 197 } 198 199 #define ICL_AUX_PW_TO_CH(pw_idx) \ 200 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A) 201 202 #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \ 203 ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C) 204 205 static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well) 206 { 207 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 208 209 return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) : 210 ICL_AUX_PW_TO_CH(pw_idx); 211 } 212 213 static struct intel_digital_port * 214 aux_ch_to_digital_port(struct drm_i915_private *dev_priv, 215 enum aux_ch aux_ch) 216 { 217 struct intel_digital_port *dig_port = NULL; 218 struct intel_encoder *encoder; 219 220 for_each_intel_encoder(&dev_priv->drm, encoder) { 221 /* We'll check the MST primary port */ 222 if (encoder->type == INTEL_OUTPUT_DP_MST) 223 continue; 224 225 dig_port = enc_to_dig_port(encoder); 226 if (!dig_port) 227 continue; 228 229 if (dig_port->aux_ch != aux_ch) { 230 dig_port = NULL; 231 continue; 232 } 233 234 break; 235 } 236 237 return dig_port; 238 } 239 240 static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915, 241 const struct i915_power_well *power_well) 242 { 243 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 244 struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch); 245 246 return intel_port_to_phy(i915, dig_port->base.port); 247 } 248 249 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 250 struct i915_power_well *power_well, 251 bool timeout_expected) 252 { 253 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 254 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 255 256 /* 257 * For some power wells we're not supposed to watch the status bit for 258 * an ack, but rather just wait a fixed amount of time and then 259 * proceed. This is only used on DG2. 260 */ 261 if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) { 262 usleep_range(600, 1200); 263 return; 264 } 265 266 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 267 if (intel_de_wait_for_set(dev_priv, regs->driver, 268 HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) { 269 drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n", 270 intel_power_well_name(power_well)); 271 272 drm_WARN_ON(&dev_priv->drm, !timeout_expected); 273 274 } 275 } 276 277 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, 278 const struct i915_power_well_regs *regs, 279 int pw_idx) 280 { 281 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 282 u32 ret; 283 284 ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0; 285 ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0; 286 if (regs->kvmr.reg) 287 ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0; 288 ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0; 289 290 return ret; 291 } 292 293 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, 294 struct i915_power_well *power_well) 295 { 296 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 297 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 298 bool disabled; 299 u32 reqs; 300 301 /* 302 * Bspec doesn't require waiting for PWs to get disabled, but still do 303 * this for paranoia. The known cases where a PW will be forced on: 304 * - a KVMR request on any power well via the KVMR request register 305 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 306 * DEBUG request registers 307 * Skip the wait in case any of the request bits are set and print a 308 * diagnostic message. 309 */ 310 wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) & 311 HSW_PWR_WELL_CTL_STATE(pw_idx))) || 312 (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1); 313 if (disabled) 314 return; 315 316 drm_dbg_kms(&dev_priv->drm, 317 "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 318 intel_power_well_name(power_well), 319 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 320 } 321 322 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, 323 enum skl_power_gate pg) 324 { 325 /* Timeout 5us for PG#0, for other PGs 1us */ 326 drm_WARN_ON(&dev_priv->drm, 327 intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS, 328 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 329 } 330 331 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 332 struct i915_power_well *power_well) 333 { 334 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 335 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 336 u32 val; 337 338 if (power_well->desc->has_fuses) { 339 enum skl_power_gate pg; 340 341 pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 342 SKL_PW_CTL_IDX_TO_PG(pw_idx); 343 344 /* Wa_16013190616:adlp */ 345 if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1) 346 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); 347 348 /* 349 * For PW1 we have to wait both for the PW0/PG0 fuse state 350 * before enabling the power well and PW1/PG1's own fuse 351 * state after the enabling. For all other power wells with 352 * fuses we only have to wait for that PW/PG's fuse state 353 * after the enabling. 354 */ 355 if (pg == SKL_PG1) 356 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); 357 } 358 359 val = intel_de_read(dev_priv, regs->driver); 360 intel_de_write(dev_priv, regs->driver, 361 val | HSW_PWR_WELL_CTL_REQ(pw_idx)); 362 363 hsw_wait_for_power_well_enable(dev_priv, power_well, false); 364 365 if (power_well->desc->has_fuses) { 366 enum skl_power_gate pg; 367 368 pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 369 SKL_PW_CTL_IDX_TO_PG(pw_idx); 370 gen9_wait_for_power_well_fuses(dev_priv, pg); 371 } 372 373 hsw_power_well_post_enable(dev_priv, 374 power_well->desc->irq_pipe_mask, 375 power_well->desc->has_vga); 376 } 377 378 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 379 struct i915_power_well *power_well) 380 { 381 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 382 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 383 u32 val; 384 385 hsw_power_well_pre_disable(dev_priv, 386 power_well->desc->irq_pipe_mask); 387 388 val = intel_de_read(dev_priv, regs->driver); 389 intel_de_write(dev_priv, regs->driver, 390 val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); 391 hsw_wait_for_power_well_disable(dev_priv, power_well); 392 } 393 394 static void 395 icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, 396 struct i915_power_well *power_well) 397 { 398 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 399 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 400 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); 401 u32 val; 402 403 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); 404 405 val = intel_de_read(dev_priv, regs->driver); 406 intel_de_write(dev_priv, regs->driver, 407 val | HSW_PWR_WELL_CTL_REQ(pw_idx)); 408 409 if (DISPLAY_VER(dev_priv) < 12) { 410 val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy)); 411 intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy), 412 val | ICL_LANE_ENABLE_AUX); 413 } 414 415 hsw_wait_for_power_well_enable(dev_priv, power_well, false); 416 417 /* Display WA #1178: icl */ 418 if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && 419 !intel_bios_is_port_edp(dev_priv, (enum port)phy)) { 420 val = intel_de_read(dev_priv, ICL_AUX_ANAOVRD1(pw_idx)); 421 val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; 422 intel_de_write(dev_priv, ICL_AUX_ANAOVRD1(pw_idx), val); 423 } 424 } 425 426 static void 427 icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, 428 struct i915_power_well *power_well) 429 { 430 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 431 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 432 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); 433 u32 val; 434 435 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); 436 437 val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy)); 438 intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy), 439 val & ~ICL_LANE_ENABLE_AUX); 440 441 val = intel_de_read(dev_priv, regs->driver); 442 intel_de_write(dev_priv, regs->driver, 443 val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); 444 445 hsw_wait_for_power_well_disable(dev_priv, power_well); 446 } 447 448 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 449 450 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, 451 struct i915_power_well *power_well, 452 struct intel_digital_port *dig_port) 453 { 454 if (drm_WARN_ON(&dev_priv->drm, !dig_port)) 455 return; 456 457 if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 458 return; 459 460 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port)); 461 } 462 463 #else 464 465 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, 466 struct i915_power_well *power_well, 467 struct intel_digital_port *dig_port) 468 { 469 } 470 471 #endif 472 473 #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1) 474 475 static void icl_tc_cold_exit(struct drm_i915_private *i915) 476 { 477 int ret, tries = 0; 478 479 while (1) { 480 ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0, 481 250, 1); 482 if (ret != -EAGAIN || ++tries == 3) 483 break; 484 msleep(1); 485 } 486 487 /* Spec states that TC cold exit can take up to 1ms to complete */ 488 if (!ret) 489 msleep(1); 490 491 /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */ 492 drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" : 493 "succeeded"); 494 } 495 496 static void 497 icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, 498 struct i915_power_well *power_well) 499 { 500 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 501 struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch); 502 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 503 bool is_tbt = power_well->desc->is_tc_tbt; 504 bool timeout_expected; 505 u32 val; 506 507 icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port); 508 509 val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch)); 510 val &= ~DP_AUX_CH_CTL_TBT_IO; 511 if (is_tbt) 512 val |= DP_AUX_CH_CTL_TBT_IO; 513 intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val); 514 515 val = intel_de_read(dev_priv, regs->driver); 516 intel_de_write(dev_priv, regs->driver, 517 val | HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx)); 518 519 /* 520 * An AUX timeout is expected if the TBT DP tunnel is down, 521 * or need to enable AUX on a legacy TypeC port as part of the TC-cold 522 * exit sequence. 523 */ 524 timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port); 525 if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 526 icl_tc_cold_exit(dev_priv); 527 528 hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected); 529 530 if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) { 531 enum tc_port tc_port; 532 533 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); 534 535 if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) & 536 DKL_CMN_UC_DW27_UC_HEALTH, 1)) 537 drm_warn(&dev_priv->drm, 538 "Timeout waiting TC uC health\n"); 539 } 540 } 541 542 static void 543 icl_aux_power_well_enable(struct drm_i915_private *dev_priv, 544 struct i915_power_well *power_well) 545 { 546 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); 547 548 if (intel_phy_is_tc(dev_priv, phy)) 549 return icl_tc_phy_aux_power_well_enable(dev_priv, power_well); 550 else if (IS_ICELAKE(dev_priv)) 551 return icl_combo_phy_aux_power_well_enable(dev_priv, 552 power_well); 553 else 554 return hsw_power_well_enable(dev_priv, power_well); 555 } 556 557 static void 558 icl_aux_power_well_disable(struct drm_i915_private *dev_priv, 559 struct i915_power_well *power_well) 560 { 561 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); 562 563 if (intel_phy_is_tc(dev_priv, phy)) 564 return hsw_power_well_disable(dev_priv, power_well); 565 else if (IS_ICELAKE(dev_priv)) 566 return icl_combo_phy_aux_power_well_disable(dev_priv, 567 power_well); 568 else 569 return hsw_power_well_disable(dev_priv, power_well); 570 } 571 572 /* 573 * We should only use the power well if we explicitly asked the hardware to 574 * enable it, so check if it's enabled and also check if we've requested it to 575 * be enabled. 576 */ 577 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 578 struct i915_power_well *power_well) 579 { 580 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 581 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 582 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 583 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) | 584 HSW_PWR_WELL_CTL_STATE(pw_idx); 585 u32 val; 586 587 val = intel_de_read(dev_priv, regs->driver); 588 589 /* 590 * On GEN9 big core due to a DMC bug the driver's request bits for PW1 591 * and the MISC_IO PW will be not restored, so check instead for the 592 * BIOS's own request bits, which are forced-on for these power wells 593 * when exiting DC5/6. 594 */ 595 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && 596 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO)) 597 val |= intel_de_read(dev_priv, regs->bios); 598 599 return (val & mask) == mask; 600 } 601 602 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 603 { 604 drm_WARN_ONCE(&dev_priv->drm, 605 (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9), 606 "DC9 already programmed to be enabled.\n"); 607 drm_WARN_ONCE(&dev_priv->drm, 608 intel_de_read(dev_priv, DC_STATE_EN) & 609 DC_STATE_EN_UPTO_DC5, 610 "DC5 still not disabled to enable DC9.\n"); 611 drm_WARN_ONCE(&dev_priv->drm, 612 intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) & 613 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), 614 "Power well 2 on.\n"); 615 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), 616 "Interrupts not disabled yet.\n"); 617 618 /* 619 * TODO: check for the following to verify the conditions to enter DC9 620 * state are satisfied: 621 * 1] Check relevant display engine registers to verify if mode set 622 * disable sequence was followed. 623 * 2] Check if display uninitialize sequence is initialized. 624 */ 625 } 626 627 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 628 { 629 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), 630 "Interrupts not disabled yet.\n"); 631 drm_WARN_ONCE(&dev_priv->drm, 632 intel_de_read(dev_priv, DC_STATE_EN) & 633 DC_STATE_EN_UPTO_DC5, 634 "DC5 still not disabled.\n"); 635 636 /* 637 * TODO: check for the following to verify DC9 state was indeed 638 * entered before programming to disable it: 639 * 1] Check relevant display engine registers to verify if mode 640 * set disable sequence was followed. 641 * 2] Check if display uninitialize sequence is initialized. 642 */ 643 } 644 645 static void gen9_write_dc_state(struct drm_i915_private *dev_priv, 646 u32 state) 647 { 648 int rewrites = 0; 649 int rereads = 0; 650 u32 v; 651 652 intel_de_write(dev_priv, DC_STATE_EN, state); 653 654 /* It has been observed that disabling the dc6 state sometimes 655 * doesn't stick and dmc keeps returning old value. Make sure 656 * the write really sticks enough times and also force rewrite until 657 * we are confident that state is exactly what we want. 658 */ 659 do { 660 v = intel_de_read(dev_priv, DC_STATE_EN); 661 662 if (v != state) { 663 intel_de_write(dev_priv, DC_STATE_EN, state); 664 rewrites++; 665 rereads = 0; 666 } else if (rereads++ > 5) { 667 break; 668 } 669 670 } while (rewrites < 100); 671 672 if (v != state) 673 drm_err(&dev_priv->drm, 674 "Writing dc state to 0x%x failed, now 0x%x\n", 675 state, v); 676 677 /* Most of the times we need one retry, avoid spam */ 678 if (rewrites > 1) 679 drm_dbg_kms(&dev_priv->drm, 680 "Rewrote dc state to 0x%x %d times\n", 681 state, rewrites); 682 } 683 684 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) 685 { 686 u32 mask; 687 688 mask = DC_STATE_EN_UPTO_DC5; 689 690 if (DISPLAY_VER(dev_priv) >= 12) 691 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6 692 | DC_STATE_EN_DC9; 693 else if (DISPLAY_VER(dev_priv) == 11) 694 mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; 695 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 696 mask |= DC_STATE_EN_DC9; 697 else 698 mask |= DC_STATE_EN_UPTO_DC6; 699 700 return mask; 701 } 702 703 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) 704 { 705 u32 val; 706 707 if (!HAS_DISPLAY(dev_priv)) 708 return; 709 710 val = intel_de_read(dev_priv, DC_STATE_EN) & gen9_dc_mask(dev_priv); 711 712 drm_dbg_kms(&dev_priv->drm, 713 "Resetting DC state tracking from %02x to %02x\n", 714 dev_priv->display.dmc.dc_state, val); 715 dev_priv->display.dmc.dc_state = val; 716 } 717 718 /** 719 * gen9_set_dc_state - set target display C power state 720 * @dev_priv: i915 device instance 721 * @state: target DC power state 722 * - DC_STATE_DISABLE 723 * - DC_STATE_EN_UPTO_DC5 724 * - DC_STATE_EN_UPTO_DC6 725 * - DC_STATE_EN_DC9 726 * 727 * Signal to DMC firmware/HW the target DC power state passed in @state. 728 * DMC/HW can turn off individual display clocks and power rails when entering 729 * a deeper DC power state (higher in number) and turns these back when exiting 730 * that state to a shallower power state (lower in number). The HW will decide 731 * when to actually enter a given state on an on-demand basis, for instance 732 * depending on the active state of display pipes. The state of display 733 * registers backed by affected power rails are saved/restored as needed. 734 * 735 * Based on the above enabling a deeper DC power state is asynchronous wrt. 736 * enabling it. Disabling a deeper power state is synchronous: for instance 737 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned 738 * back on and register state is restored. This is guaranteed by the MMIO write 739 * to DC_STATE_EN blocking until the state is restored. 740 */ 741 void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) 742 { 743 u32 val; 744 u32 mask; 745 746 if (!HAS_DISPLAY(dev_priv)) 747 return; 748 749 if (drm_WARN_ON_ONCE(&dev_priv->drm, 750 state & ~dev_priv->display.dmc.allowed_dc_mask)) 751 state &= dev_priv->display.dmc.allowed_dc_mask; 752 753 val = intel_de_read(dev_priv, DC_STATE_EN); 754 mask = gen9_dc_mask(dev_priv); 755 drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n", 756 val & mask, state); 757 758 /* Check if DMC is ignoring our DC state requests */ 759 if ((val & mask) != dev_priv->display.dmc.dc_state) 760 drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n", 761 dev_priv->display.dmc.dc_state, val & mask); 762 763 val &= ~mask; 764 val |= state; 765 766 gen9_write_dc_state(dev_priv, val); 767 768 dev_priv->display.dmc.dc_state = val & mask; 769 } 770 771 static void tgl_enable_dc3co(struct drm_i915_private *dev_priv) 772 { 773 drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n"); 774 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO); 775 } 776 777 static void tgl_disable_dc3co(struct drm_i915_private *dev_priv) 778 { 779 u32 val; 780 781 drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n"); 782 val = intel_de_read(dev_priv, DC_STATE_EN); 783 val &= ~DC_STATE_DC3CO_STATUS; 784 intel_de_write(dev_priv, DC_STATE_EN, val); 785 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 786 /* 787 * Delay of 200us DC3CO Exit time B.Spec 49196 788 */ 789 usleep_range(200, 210); 790 } 791 792 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 793 { 794 enum i915_power_well_id high_pg; 795 796 /* Power wells at this level and above must be disabled for DC5 entry */ 797 if (DISPLAY_VER(dev_priv) == 12) 798 high_pg = ICL_DISP_PW_3; 799 else 800 high_pg = SKL_DISP_PW_2; 801 802 drm_WARN_ONCE(&dev_priv->drm, 803 intel_display_power_well_is_enabled(dev_priv, high_pg), 804 "Power wells above platform's DC5 limit still enabled.\n"); 805 806 drm_WARN_ONCE(&dev_priv->drm, 807 (intel_de_read(dev_priv, DC_STATE_EN) & 808 DC_STATE_EN_UPTO_DC5), 809 "DC5 already programmed to be enabled.\n"); 810 assert_rpm_wakelock_held(&dev_priv->runtime_pm); 811 812 assert_dmc_loaded(dev_priv); 813 } 814 815 void gen9_enable_dc5(struct drm_i915_private *dev_priv) 816 { 817 assert_can_enable_dc5(dev_priv); 818 819 drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n"); 820 821 /* Wa Display #1183: skl,kbl,cfl */ 822 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 823 intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1, 824 intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT); 825 826 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 827 } 828 829 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 830 { 831 drm_WARN_ONCE(&dev_priv->drm, 832 intel_de_read(dev_priv, UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 833 "Backlight is not disabled.\n"); 834 drm_WARN_ONCE(&dev_priv->drm, 835 (intel_de_read(dev_priv, DC_STATE_EN) & 836 DC_STATE_EN_UPTO_DC6), 837 "DC6 already programmed to be enabled.\n"); 838 839 assert_dmc_loaded(dev_priv); 840 } 841 842 void skl_enable_dc6(struct drm_i915_private *dev_priv) 843 { 844 assert_can_enable_dc6(dev_priv); 845 846 drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n"); 847 848 /* Wa Display #1183: skl,kbl,cfl */ 849 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 850 intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1, 851 intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT); 852 853 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 854 } 855 856 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 857 { 858 assert_can_enable_dc9(dev_priv); 859 860 drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n"); 861 /* 862 * Power sequencer reset is not needed on 863 * platforms with South Display Engine on PCH, 864 * because PPS registers are always on. 865 */ 866 if (!HAS_PCH_SPLIT(dev_priv)) 867 intel_pps_reset_all(dev_priv); 868 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); 869 } 870 871 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 872 { 873 assert_can_disable_dc9(dev_priv); 874 875 drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n"); 876 877 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 878 879 intel_pps_unlock_regs_wa(dev_priv); 880 } 881 882 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 883 struct i915_power_well *power_well) 884 { 885 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 886 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 887 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 888 u32 bios_req = intel_de_read(dev_priv, regs->bios); 889 890 /* Take over the request bit if set by BIOS. */ 891 if (bios_req & mask) { 892 u32 drv_req = intel_de_read(dev_priv, regs->driver); 893 894 if (!(drv_req & mask)) 895 intel_de_write(dev_priv, regs->driver, drv_req | mask); 896 intel_de_write(dev_priv, regs->bios, bios_req & ~mask); 897 } 898 } 899 900 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 901 struct i915_power_well *power_well) 902 { 903 bxt_ddi_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 904 } 905 906 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 907 struct i915_power_well *power_well) 908 { 909 bxt_ddi_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 910 } 911 912 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, 913 struct i915_power_well *power_well) 914 { 915 return bxt_ddi_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 916 } 917 918 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) 919 { 920 struct i915_power_well *power_well; 921 922 power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A); 923 if (intel_power_well_refcount(power_well) > 0) 924 bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 925 926 power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 927 if (intel_power_well_refcount(power_well) > 0) 928 bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 929 930 if (IS_GEMINILAKE(dev_priv)) { 931 power_well = lookup_power_well(dev_priv, 932 GLK_DISP_PW_DPIO_CMN_C); 933 if (intel_power_well_refcount(power_well) > 0) 934 bxt_ddi_phy_verify_state(dev_priv, 935 i915_power_well_instance(power_well)->bxt.phy); 936 } 937 } 938 939 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 940 struct i915_power_well *power_well) 941 { 942 return ((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && 943 (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); 944 } 945 946 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) 947 { 948 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv); 949 u8 enabled_dbuf_slices = dev_priv->display.dbuf.enabled_slices; 950 951 drm_WARN(&dev_priv->drm, 952 hw_enabled_dbuf_slices != enabled_dbuf_slices, 953 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", 954 hw_enabled_dbuf_slices, 955 enabled_dbuf_slices); 956 } 957 958 void gen9_disable_dc_states(struct drm_i915_private *dev_priv) 959 { 960 struct intel_cdclk_config cdclk_config = {}; 961 962 if (dev_priv->display.dmc.target_dc_state == DC_STATE_EN_DC3CO) { 963 tgl_disable_dc3co(dev_priv); 964 return; 965 } 966 967 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 968 969 if (!HAS_DISPLAY(dev_priv)) 970 return; 971 972 intel_cdclk_get_cdclk(dev_priv, &cdclk_config); 973 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 974 drm_WARN_ON(&dev_priv->drm, 975 intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw, 976 &cdclk_config)); 977 978 gen9_assert_dbuf_enabled(dev_priv); 979 980 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 981 bxt_verify_ddi_phy_power_wells(dev_priv); 982 983 if (DISPLAY_VER(dev_priv) >= 11) 984 /* 985 * DMC retains HW context only for port A, the other combo 986 * PHY's HW context for port B is lost after DC transitions, 987 * so we need to restore it manually. 988 */ 989 intel_combo_phy_init(dev_priv); 990 } 991 992 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 993 struct i915_power_well *power_well) 994 { 995 gen9_disable_dc_states(dev_priv); 996 } 997 998 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 999 struct i915_power_well *power_well) 1000 { 1001 if (!intel_dmc_has_payload(dev_priv)) 1002 return; 1003 1004 switch (dev_priv->display.dmc.target_dc_state) { 1005 case DC_STATE_EN_DC3CO: 1006 tgl_enable_dc3co(dev_priv); 1007 break; 1008 case DC_STATE_EN_UPTO_DC6: 1009 skl_enable_dc6(dev_priv); 1010 break; 1011 case DC_STATE_EN_UPTO_DC5: 1012 gen9_enable_dc5(dev_priv); 1013 break; 1014 } 1015 } 1016 1017 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, 1018 struct i915_power_well *power_well) 1019 { 1020 } 1021 1022 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 1023 struct i915_power_well *power_well) 1024 { 1025 } 1026 1027 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 1028 struct i915_power_well *power_well) 1029 { 1030 return true; 1031 } 1032 1033 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, 1034 struct i915_power_well *power_well) 1035 { 1036 if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) 1037 i830_enable_pipe(dev_priv, PIPE_A); 1038 if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) 1039 i830_enable_pipe(dev_priv, PIPE_B); 1040 } 1041 1042 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, 1043 struct i915_power_well *power_well) 1044 { 1045 i830_disable_pipe(dev_priv, PIPE_B); 1046 i830_disable_pipe(dev_priv, PIPE_A); 1047 } 1048 1049 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, 1050 struct i915_power_well *power_well) 1051 { 1052 return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE && 1053 intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; 1054 } 1055 1056 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, 1057 struct i915_power_well *power_well) 1058 { 1059 if (intel_power_well_refcount(power_well) > 0) 1060 i830_pipes_power_well_enable(dev_priv, power_well); 1061 else 1062 i830_pipes_power_well_disable(dev_priv, power_well); 1063 } 1064 1065 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 1066 struct i915_power_well *power_well, bool enable) 1067 { 1068 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1069 u32 mask; 1070 u32 state; 1071 u32 ctrl; 1072 1073 mask = PUNIT_PWRGT_MASK(pw_idx); 1074 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : 1075 PUNIT_PWRGT_PWR_GATE(pw_idx); 1076 1077 vlv_punit_get(dev_priv); 1078 1079 #define COND \ 1080 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 1081 1082 if (COND) 1083 goto out; 1084 1085 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 1086 ctrl &= ~mask; 1087 ctrl |= state; 1088 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 1089 1090 if (wait_for(COND, 100)) 1091 drm_err(&dev_priv->drm, 1092 "timeout setting power well state %08x (%08x)\n", 1093 state, 1094 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 1095 1096 #undef COND 1097 1098 out: 1099 vlv_punit_put(dev_priv); 1100 } 1101 1102 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 1103 struct i915_power_well *power_well) 1104 { 1105 vlv_set_power_well(dev_priv, power_well, true); 1106 } 1107 1108 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 1109 struct i915_power_well *power_well) 1110 { 1111 vlv_set_power_well(dev_priv, power_well, false); 1112 } 1113 1114 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 1115 struct i915_power_well *power_well) 1116 { 1117 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1118 bool enabled = false; 1119 u32 mask; 1120 u32 state; 1121 u32 ctrl; 1122 1123 mask = PUNIT_PWRGT_MASK(pw_idx); 1124 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); 1125 1126 vlv_punit_get(dev_priv); 1127 1128 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 1129 /* 1130 * We only ever set the power-on and power-gate states, anything 1131 * else is unexpected. 1132 */ 1133 drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && 1134 state != PUNIT_PWRGT_PWR_GATE(pw_idx)); 1135 if (state == ctrl) 1136 enabled = true; 1137 1138 /* 1139 * A transient state at this point would mean some unexpected party 1140 * is poking at the power controls too. 1141 */ 1142 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 1143 drm_WARN_ON(&dev_priv->drm, ctrl != state); 1144 1145 vlv_punit_put(dev_priv); 1146 1147 return enabled; 1148 } 1149 1150 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 1151 { 1152 u32 val; 1153 1154 /* 1155 * On driver load, a pipe may be active and driving a DSI display. 1156 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 1157 * (and never recovering) in this case. intel_dsi_post_disable() will 1158 * clear it when we turn off the display. 1159 */ 1160 val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv)); 1161 val &= DPOUNIT_CLOCK_GATE_DISABLE; 1162 val |= VRHUNIT_CLOCK_GATE_DISABLE; 1163 intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val); 1164 1165 /* 1166 * Disable trickle feed and enable pnd deadline calculation 1167 */ 1168 intel_de_write(dev_priv, MI_ARB_VLV, 1169 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 1170 intel_de_write(dev_priv, CBR1_VLV, 0); 1171 1172 drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0); 1173 intel_de_write(dev_priv, RAWCLK_FREQ_VLV, 1174 DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 1175 1000)); 1176 } 1177 1178 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 1179 { 1180 struct intel_encoder *encoder; 1181 enum pipe pipe; 1182 1183 /* 1184 * Enable the CRI clock source so we can get at the 1185 * display and the reference clock for VGA 1186 * hotplug / manual detection. Supposedly DSI also 1187 * needs the ref clock up and running. 1188 * 1189 * CHV DPLL B/C have some issues if VGA mode is enabled. 1190 */ 1191 for_each_pipe(dev_priv, pipe) { 1192 u32 val = intel_de_read(dev_priv, DPLL(pipe)); 1193 1194 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1195 if (pipe != PIPE_A) 1196 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1197 1198 intel_de_write(dev_priv, DPLL(pipe), val); 1199 } 1200 1201 vlv_init_display_clock_gating(dev_priv); 1202 1203 spin_lock_irq(&dev_priv->irq_lock); 1204 valleyview_enable_display_irqs(dev_priv); 1205 spin_unlock_irq(&dev_priv->irq_lock); 1206 1207 /* 1208 * During driver initialization/resume we can avoid restoring the 1209 * part of the HW/SW state that will be inited anyway explicitly. 1210 */ 1211 if (dev_priv->display.power.domains.initializing) 1212 return; 1213 1214 intel_hpd_init(dev_priv); 1215 intel_hpd_poll_disable(dev_priv); 1216 1217 /* Re-enable the ADPA, if we have one */ 1218 for_each_intel_encoder(&dev_priv->drm, encoder) { 1219 if (encoder->type == INTEL_OUTPUT_ANALOG) 1220 intel_crt_reset(&encoder->base); 1221 } 1222 1223 intel_vga_redisable_power_on(dev_priv); 1224 1225 intel_pps_unlock_regs_wa(dev_priv); 1226 } 1227 1228 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 1229 { 1230 spin_lock_irq(&dev_priv->irq_lock); 1231 valleyview_disable_display_irqs(dev_priv); 1232 spin_unlock_irq(&dev_priv->irq_lock); 1233 1234 /* make sure we're done processing display irqs */ 1235 intel_synchronize_irq(dev_priv); 1236 1237 intel_pps_reset_all(dev_priv); 1238 1239 /* Prevent us from re-enabling polling on accident in late suspend */ 1240 if (!dev_priv->drm.dev->power.is_suspended) 1241 intel_hpd_poll_enable(dev_priv); 1242 } 1243 1244 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 1245 struct i915_power_well *power_well) 1246 { 1247 vlv_set_power_well(dev_priv, power_well, true); 1248 1249 vlv_display_power_well_init(dev_priv); 1250 } 1251 1252 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 1253 struct i915_power_well *power_well) 1254 { 1255 vlv_display_power_well_deinit(dev_priv); 1256 1257 vlv_set_power_well(dev_priv, power_well, false); 1258 } 1259 1260 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1261 struct i915_power_well *power_well) 1262 { 1263 /* since ref/cri clock was enabled */ 1264 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1265 1266 vlv_set_power_well(dev_priv, power_well, true); 1267 1268 /* 1269 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1270 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1271 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1272 * b. The other bits such as sfr settings / modesel may all 1273 * be set to 0. 1274 * 1275 * This should only be done on init and resume from S3 with 1276 * both PLLs disabled, or we risk losing DPIO and PLL 1277 * synchronization. 1278 */ 1279 intel_de_write(dev_priv, DPIO_CTL, 1280 intel_de_read(dev_priv, DPIO_CTL) | DPIO_CMNRST); 1281 } 1282 1283 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1284 struct i915_power_well *power_well) 1285 { 1286 enum pipe pipe; 1287 1288 for_each_pipe(dev_priv, pipe) 1289 assert_pll_disabled(dev_priv, pipe); 1290 1291 /* Assert common reset */ 1292 intel_de_write(dev_priv, DPIO_CTL, 1293 intel_de_read(dev_priv, DPIO_CTL) & ~DPIO_CMNRST); 1294 1295 vlv_set_power_well(dev_priv, power_well, false); 1296 } 1297 1298 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1299 1300 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1301 { 1302 struct i915_power_well *cmn_bc = 1303 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 1304 struct i915_power_well *cmn_d = 1305 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D); 1306 u32 phy_control = dev_priv->display.power.chv_phy_control; 1307 u32 phy_status = 0; 1308 u32 phy_status_mask = 0xffffffff; 1309 1310 /* 1311 * The BIOS can leave the PHY is some weird state 1312 * where it doesn't fully power down some parts. 1313 * Disable the asserts until the PHY has been fully 1314 * reset (ie. the power well has been disabled at 1315 * least once). 1316 */ 1317 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0]) 1318 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1319 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1320 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1321 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1322 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1323 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1324 1325 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1]) 1326 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1327 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1328 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1329 1330 if (intel_power_well_is_enabled(dev_priv, cmn_bc)) { 1331 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1332 1333 /* this assumes override is only used to enable lanes */ 1334 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1335 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1336 1337 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1338 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1339 1340 /* CL1 is on whenever anything is on in either channel */ 1341 if (BITS_SET(phy_control, 1342 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1343 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1344 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1345 1346 /* 1347 * The DPLLB check accounts for the pipe B + port A usage 1348 * with CL2 powered up but all the lanes in the second channel 1349 * powered down. 1350 */ 1351 if (BITS_SET(phy_control, 1352 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1353 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1354 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1355 1356 if (BITS_SET(phy_control, 1357 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1358 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1359 if (BITS_SET(phy_control, 1360 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1361 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1362 1363 if (BITS_SET(phy_control, 1364 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1365 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1366 if (BITS_SET(phy_control, 1367 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1368 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1369 } 1370 1371 if (intel_power_well_is_enabled(dev_priv, cmn_d)) { 1372 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1373 1374 /* this assumes override is only used to enable lanes */ 1375 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1376 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1377 1378 if (BITS_SET(phy_control, 1379 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1380 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1381 1382 if (BITS_SET(phy_control, 1383 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1384 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1385 if (BITS_SET(phy_control, 1386 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1387 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1388 } 1389 1390 phy_status &= phy_status_mask; 1391 1392 /* 1393 * The PHY may be busy with some initial calibration and whatnot, 1394 * so the power state can take a while to actually change. 1395 */ 1396 if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS, 1397 phy_status_mask, phy_status, 10)) 1398 drm_err(&dev_priv->drm, 1399 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1400 intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask, 1401 phy_status, dev_priv->display.power.chv_phy_control); 1402 } 1403 1404 #undef BITS_SET 1405 1406 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1407 struct i915_power_well *power_well) 1408 { 1409 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1410 enum dpio_phy phy; 1411 enum pipe pipe; 1412 u32 tmp; 1413 1414 drm_WARN_ON_ONCE(&dev_priv->drm, 1415 id != VLV_DISP_PW_DPIO_CMN_BC && 1416 id != CHV_DISP_PW_DPIO_CMN_D); 1417 1418 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1419 pipe = PIPE_A; 1420 phy = DPIO_PHY0; 1421 } else { 1422 pipe = PIPE_C; 1423 phy = DPIO_PHY1; 1424 } 1425 1426 /* since ref/cri clock was enabled */ 1427 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1428 vlv_set_power_well(dev_priv, power_well, true); 1429 1430 /* Poll for phypwrgood signal */ 1431 if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS, 1432 PHY_POWERGOOD(phy), 1)) 1433 drm_err(&dev_priv->drm, "Display PHY %d is not power up\n", 1434 phy); 1435 1436 vlv_dpio_get(dev_priv); 1437 1438 /* Enable dynamic power down */ 1439 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1440 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1441 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1442 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1443 1444 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1445 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1446 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1447 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1448 } else { 1449 /* 1450 * Force the non-existing CL2 off. BXT does this 1451 * too, so maybe it saves some power even though 1452 * CL2 doesn't exist? 1453 */ 1454 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1455 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1456 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1457 } 1458 1459 vlv_dpio_put(dev_priv); 1460 1461 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1462 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1463 dev_priv->display.power.chv_phy_control); 1464 1465 drm_dbg_kms(&dev_priv->drm, 1466 "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1467 phy, dev_priv->display.power.chv_phy_control); 1468 1469 assert_chv_phy_status(dev_priv); 1470 } 1471 1472 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1473 struct i915_power_well *power_well) 1474 { 1475 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1476 enum dpio_phy phy; 1477 1478 drm_WARN_ON_ONCE(&dev_priv->drm, 1479 id != VLV_DISP_PW_DPIO_CMN_BC && 1480 id != CHV_DISP_PW_DPIO_CMN_D); 1481 1482 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1483 phy = DPIO_PHY0; 1484 assert_pll_disabled(dev_priv, PIPE_A); 1485 assert_pll_disabled(dev_priv, PIPE_B); 1486 } else { 1487 phy = DPIO_PHY1; 1488 assert_pll_disabled(dev_priv, PIPE_C); 1489 } 1490 1491 dev_priv->display.power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1492 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1493 dev_priv->display.power.chv_phy_control); 1494 1495 vlv_set_power_well(dev_priv, power_well, false); 1496 1497 drm_dbg_kms(&dev_priv->drm, 1498 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1499 phy, dev_priv->display.power.chv_phy_control); 1500 1501 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1502 dev_priv->display.power.chv_phy_assert[phy] = true; 1503 1504 assert_chv_phy_status(dev_priv); 1505 } 1506 1507 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1508 enum dpio_channel ch, bool override, unsigned int mask) 1509 { 1510 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1511 u32 reg, val, expected, actual; 1512 1513 /* 1514 * The BIOS can leave the PHY is some weird state 1515 * where it doesn't fully power down some parts. 1516 * Disable the asserts until the PHY has been fully 1517 * reset (ie. the power well has been disabled at 1518 * least once). 1519 */ 1520 if (!dev_priv->display.power.chv_phy_assert[phy]) 1521 return; 1522 1523 if (ch == DPIO_CH0) 1524 reg = _CHV_CMN_DW0_CH0; 1525 else 1526 reg = _CHV_CMN_DW6_CH1; 1527 1528 vlv_dpio_get(dev_priv); 1529 val = vlv_dpio_read(dev_priv, pipe, reg); 1530 vlv_dpio_put(dev_priv); 1531 1532 /* 1533 * This assumes !override is only used when the port is disabled. 1534 * All lanes should power down even without the override when 1535 * the port is disabled. 1536 */ 1537 if (!override || mask == 0xf) { 1538 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1539 /* 1540 * If CH1 common lane is not active anymore 1541 * (eg. for pipe B DPLL) the entire channel will 1542 * shut down, which causes the common lane registers 1543 * to read as 0. That means we can't actually check 1544 * the lane power down status bits, but as the entire 1545 * register reads as 0 it's a good indication that the 1546 * channel is indeed entirely powered down. 1547 */ 1548 if (ch == DPIO_CH1 && val == 0) 1549 expected = 0; 1550 } else if (mask != 0x0) { 1551 expected = DPIO_ANYDL_POWERDOWN; 1552 } else { 1553 expected = 0; 1554 } 1555 1556 if (ch == DPIO_CH0) 1557 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1558 else 1559 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1560 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1561 1562 drm_WARN(&dev_priv->drm, actual != expected, 1563 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1564 !!(actual & DPIO_ALLDL_POWERDOWN), 1565 !!(actual & DPIO_ANYDL_POWERDOWN), 1566 !!(expected & DPIO_ALLDL_POWERDOWN), 1567 !!(expected & DPIO_ANYDL_POWERDOWN), 1568 reg, val); 1569 } 1570 1571 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1572 enum dpio_channel ch, bool override) 1573 { 1574 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1575 bool was_override; 1576 1577 mutex_lock(&power_domains->lock); 1578 1579 was_override = dev_priv->display.power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1580 1581 if (override == was_override) 1582 goto out; 1583 1584 if (override) 1585 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1586 else 1587 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1588 1589 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1590 dev_priv->display.power.chv_phy_control); 1591 1592 drm_dbg_kms(&dev_priv->drm, 1593 "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1594 phy, ch, dev_priv->display.power.chv_phy_control); 1595 1596 assert_chv_phy_status(dev_priv); 1597 1598 out: 1599 mutex_unlock(&power_domains->lock); 1600 1601 return was_override; 1602 } 1603 1604 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1605 bool override, unsigned int mask) 1606 { 1607 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1608 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1609 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); 1610 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); 1611 1612 mutex_lock(&power_domains->lock); 1613 1614 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1615 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1616 1617 if (override) 1618 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1619 else 1620 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1621 1622 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1623 dev_priv->display.power.chv_phy_control); 1624 1625 drm_dbg_kms(&dev_priv->drm, 1626 "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1627 phy, ch, mask, dev_priv->display.power.chv_phy_control); 1628 1629 assert_chv_phy_status(dev_priv); 1630 1631 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1632 1633 mutex_unlock(&power_domains->lock); 1634 } 1635 1636 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1637 struct i915_power_well *power_well) 1638 { 1639 enum pipe pipe = PIPE_A; 1640 bool enabled; 1641 u32 state, ctrl; 1642 1643 vlv_punit_get(dev_priv); 1644 1645 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); 1646 /* 1647 * We only ever set the power-on and power-gate states, anything 1648 * else is unexpected. 1649 */ 1650 drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) && 1651 state != DP_SSS_PWR_GATE(pipe)); 1652 enabled = state == DP_SSS_PWR_ON(pipe); 1653 1654 /* 1655 * A transient state at this point would mean some unexpected party 1656 * is poking at the power controls too. 1657 */ 1658 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); 1659 drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state); 1660 1661 vlv_punit_put(dev_priv); 1662 1663 return enabled; 1664 } 1665 1666 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1667 struct i915_power_well *power_well, 1668 bool enable) 1669 { 1670 enum pipe pipe = PIPE_A; 1671 u32 state; 1672 u32 ctrl; 1673 1674 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1675 1676 vlv_punit_get(dev_priv); 1677 1678 #define COND \ 1679 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) 1680 1681 if (COND) 1682 goto out; 1683 1684 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 1685 ctrl &= ~DP_SSC_MASK(pipe); 1686 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1687 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl); 1688 1689 if (wait_for(COND, 100)) 1690 drm_err(&dev_priv->drm, 1691 "timeout setting power well state %08x (%08x)\n", 1692 state, 1693 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); 1694 1695 #undef COND 1696 1697 out: 1698 vlv_punit_put(dev_priv); 1699 } 1700 1701 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 1702 struct i915_power_well *power_well) 1703 { 1704 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1705 dev_priv->display.power.chv_phy_control); 1706 } 1707 1708 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1709 struct i915_power_well *power_well) 1710 { 1711 chv_set_pipe_power_well(dev_priv, power_well, true); 1712 1713 vlv_display_power_well_init(dev_priv); 1714 } 1715 1716 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1717 struct i915_power_well *power_well) 1718 { 1719 vlv_display_power_well_deinit(dev_priv); 1720 1721 chv_set_pipe_power_well(dev_priv, power_well, false); 1722 } 1723 1724 static void 1725 tgl_tc_cold_request(struct drm_i915_private *i915, bool block) 1726 { 1727 u8 tries = 0; 1728 int ret; 1729 1730 while (1) { 1731 u32 low_val; 1732 u32 high_val = 0; 1733 1734 if (block) 1735 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ; 1736 else 1737 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ; 1738 1739 /* 1740 * Spec states that we should timeout the request after 200us 1741 * but the function below will timeout after 500us 1742 */ 1743 ret = snb_pcode_read(&i915->uncore, TGL_PCODE_TCCOLD, &low_val, &high_val); 1744 if (ret == 0) { 1745 if (block && 1746 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED)) 1747 ret = -EIO; 1748 else 1749 break; 1750 } 1751 1752 if (++tries == 3) 1753 break; 1754 1755 msleep(1); 1756 } 1757 1758 if (ret) 1759 drm_err(&i915->drm, "TC cold %sblock failed\n", 1760 block ? "" : "un"); 1761 else 1762 drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n", 1763 block ? "" : "un"); 1764 } 1765 1766 static void 1767 tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915, 1768 struct i915_power_well *power_well) 1769 { 1770 tgl_tc_cold_request(i915, true); 1771 } 1772 1773 static void 1774 tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915, 1775 struct i915_power_well *power_well) 1776 { 1777 tgl_tc_cold_request(i915, false); 1778 } 1779 1780 static void 1781 tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915, 1782 struct i915_power_well *power_well) 1783 { 1784 if (intel_power_well_refcount(power_well) > 0) 1785 tgl_tc_cold_off_power_well_enable(i915, power_well); 1786 else 1787 tgl_tc_cold_off_power_well_disable(i915, power_well); 1788 } 1789 1790 static bool 1791 tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv, 1792 struct i915_power_well *power_well) 1793 { 1794 /* 1795 * Not the correctly implementation but there is no way to just read it 1796 * from PCODE, so returning count to avoid state mismatch errors 1797 */ 1798 return intel_power_well_refcount(power_well); 1799 } 1800 1801 static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv, 1802 struct i915_power_well *power_well) 1803 { 1804 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1805 1806 intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch), 1807 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1808 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); 1809 1810 /* 1811 * The power status flag cannot be used to determine whether aux 1812 * power wells have finished powering up. Instead we're 1813 * expected to just wait a fixed 600us after raising the request 1814 * bit. 1815 */ 1816 usleep_range(600, 1200); 1817 } 1818 1819 static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv, 1820 struct i915_power_well *power_well) 1821 { 1822 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1823 1824 intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch), 1825 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1826 0); 1827 usleep_range(10, 30); 1828 } 1829 1830 static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv, 1831 struct i915_power_well *power_well) 1832 { 1833 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1834 1835 return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) & 1836 XELPDP_DP_AUX_CH_CTL_POWER_STATUS; 1837 } 1838 1839 const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1840 .sync_hw = i9xx_power_well_sync_hw_noop, 1841 .enable = i9xx_always_on_power_well_noop, 1842 .disable = i9xx_always_on_power_well_noop, 1843 .is_enabled = i9xx_always_on_power_well_enabled, 1844 }; 1845 1846 const struct i915_power_well_ops chv_pipe_power_well_ops = { 1847 .sync_hw = chv_pipe_power_well_sync_hw, 1848 .enable = chv_pipe_power_well_enable, 1849 .disable = chv_pipe_power_well_disable, 1850 .is_enabled = chv_pipe_power_well_enabled, 1851 }; 1852 1853 const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1854 .sync_hw = i9xx_power_well_sync_hw_noop, 1855 .enable = chv_dpio_cmn_power_well_enable, 1856 .disable = chv_dpio_cmn_power_well_disable, 1857 .is_enabled = vlv_power_well_enabled, 1858 }; 1859 1860 const struct i915_power_well_ops i830_pipes_power_well_ops = { 1861 .sync_hw = i830_pipes_power_well_sync_hw, 1862 .enable = i830_pipes_power_well_enable, 1863 .disable = i830_pipes_power_well_disable, 1864 .is_enabled = i830_pipes_power_well_enabled, 1865 }; 1866 1867 static const struct i915_power_well_regs hsw_power_well_regs = { 1868 .bios = HSW_PWR_WELL_CTL1, 1869 .driver = HSW_PWR_WELL_CTL2, 1870 .kvmr = HSW_PWR_WELL_CTL3, 1871 .debug = HSW_PWR_WELL_CTL4, 1872 }; 1873 1874 const struct i915_power_well_ops hsw_power_well_ops = { 1875 .regs = &hsw_power_well_regs, 1876 .sync_hw = hsw_power_well_sync_hw, 1877 .enable = hsw_power_well_enable, 1878 .disable = hsw_power_well_disable, 1879 .is_enabled = hsw_power_well_enabled, 1880 }; 1881 1882 const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1883 .sync_hw = i9xx_power_well_sync_hw_noop, 1884 .enable = gen9_dc_off_power_well_enable, 1885 .disable = gen9_dc_off_power_well_disable, 1886 .is_enabled = gen9_dc_off_power_well_enabled, 1887 }; 1888 1889 const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 1890 .sync_hw = i9xx_power_well_sync_hw_noop, 1891 .enable = bxt_dpio_cmn_power_well_enable, 1892 .disable = bxt_dpio_cmn_power_well_disable, 1893 .is_enabled = bxt_dpio_cmn_power_well_enabled, 1894 }; 1895 1896 const struct i915_power_well_ops vlv_display_power_well_ops = { 1897 .sync_hw = i9xx_power_well_sync_hw_noop, 1898 .enable = vlv_display_power_well_enable, 1899 .disable = vlv_display_power_well_disable, 1900 .is_enabled = vlv_power_well_enabled, 1901 }; 1902 1903 const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1904 .sync_hw = i9xx_power_well_sync_hw_noop, 1905 .enable = vlv_dpio_cmn_power_well_enable, 1906 .disable = vlv_dpio_cmn_power_well_disable, 1907 .is_enabled = vlv_power_well_enabled, 1908 }; 1909 1910 const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1911 .sync_hw = i9xx_power_well_sync_hw_noop, 1912 .enable = vlv_power_well_enable, 1913 .disable = vlv_power_well_disable, 1914 .is_enabled = vlv_power_well_enabled, 1915 }; 1916 1917 static const struct i915_power_well_regs icl_aux_power_well_regs = { 1918 .bios = ICL_PWR_WELL_CTL_AUX1, 1919 .driver = ICL_PWR_WELL_CTL_AUX2, 1920 .debug = ICL_PWR_WELL_CTL_AUX4, 1921 }; 1922 1923 const struct i915_power_well_ops icl_aux_power_well_ops = { 1924 .regs = &icl_aux_power_well_regs, 1925 .sync_hw = hsw_power_well_sync_hw, 1926 .enable = icl_aux_power_well_enable, 1927 .disable = icl_aux_power_well_disable, 1928 .is_enabled = hsw_power_well_enabled, 1929 }; 1930 1931 static const struct i915_power_well_regs icl_ddi_power_well_regs = { 1932 .bios = ICL_PWR_WELL_CTL_DDI1, 1933 .driver = ICL_PWR_WELL_CTL_DDI2, 1934 .debug = ICL_PWR_WELL_CTL_DDI4, 1935 }; 1936 1937 const struct i915_power_well_ops icl_ddi_power_well_ops = { 1938 .regs = &icl_ddi_power_well_regs, 1939 .sync_hw = hsw_power_well_sync_hw, 1940 .enable = hsw_power_well_enable, 1941 .disable = hsw_power_well_disable, 1942 .is_enabled = hsw_power_well_enabled, 1943 }; 1944 1945 const struct i915_power_well_ops tgl_tc_cold_off_ops = { 1946 .sync_hw = tgl_tc_cold_off_power_well_sync_hw, 1947 .enable = tgl_tc_cold_off_power_well_enable, 1948 .disable = tgl_tc_cold_off_power_well_disable, 1949 .is_enabled = tgl_tc_cold_off_power_well_is_enabled, 1950 }; 1951 1952 const struct i915_power_well_ops xelpdp_aux_power_well_ops = { 1953 .sync_hw = i9xx_power_well_sync_hw_noop, 1954 .enable = xelpdp_aux_power_well_enable, 1955 .disable = xelpdp_aux_power_well_disable, 1956 .is_enabled = xelpdp_aux_power_well_enabled, 1957 }; 1958