1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_irq.h" 8 #include "intel_backlight_regs.h" 9 #include "intel_combo_phy.h" 10 #include "intel_combo_phy_regs.h" 11 #include "intel_crt.h" 12 #include "intel_de.h" 13 #include "intel_display_power_well.h" 14 #include "intel_display_types.h" 15 #include "intel_dkl_phy.h" 16 #include "intel_dkl_phy_regs.h" 17 #include "intel_dmc.h" 18 #include "intel_dpio_phy.h" 19 #include "intel_dpll.h" 20 #include "intel_hotplug.h" 21 #include "intel_pcode.h" 22 #include "intel_pps.h" 23 #include "intel_tc.h" 24 #include "intel_vga.h" 25 #include "skl_watermark.h" 26 #include "vlv_sideband.h" 27 #include "vlv_sideband_reg.h" 28 29 struct i915_power_well_regs { 30 i915_reg_t bios; 31 i915_reg_t driver; 32 i915_reg_t kvmr; 33 i915_reg_t debug; 34 }; 35 36 struct i915_power_well_ops { 37 const struct i915_power_well_regs *regs; 38 /* 39 * Synchronize the well's hw state to match the current sw state, for 40 * example enable/disable it based on the current refcount. Called 41 * during driver init and resume time, possibly after first calling 42 * the enable/disable handlers. 43 */ 44 void (*sync_hw)(struct drm_i915_private *i915, 45 struct i915_power_well *power_well); 46 /* 47 * Enable the well and resources that depend on it (for example 48 * interrupts located on the well). Called after the 0->1 refcount 49 * transition. 50 */ 51 void (*enable)(struct drm_i915_private *i915, 52 struct i915_power_well *power_well); 53 /* 54 * Disable the well and resources that depend on it. Called after 55 * the 1->0 refcount transition. 56 */ 57 void (*disable)(struct drm_i915_private *i915, 58 struct i915_power_well *power_well); 59 /* Returns the hw enabled state. */ 60 bool (*is_enabled)(struct drm_i915_private *i915, 61 struct i915_power_well *power_well); 62 }; 63 64 static const struct i915_power_well_instance * 65 i915_power_well_instance(const struct i915_power_well *power_well) 66 { 67 return &power_well->desc->instances->list[power_well->instance_idx]; 68 } 69 70 struct i915_power_well * 71 lookup_power_well(struct drm_i915_private *i915, 72 enum i915_power_well_id power_well_id) 73 { 74 struct i915_power_well *power_well; 75 76 for_each_power_well(i915, power_well) 77 if (i915_power_well_instance(power_well)->id == power_well_id) 78 return power_well; 79 80 /* 81 * It's not feasible to add error checking code to the callers since 82 * this condition really shouldn't happen and it doesn't even make sense 83 * to abort things like display initialization sequences. Just return 84 * the first power well and hope the WARN gets reported so we can fix 85 * our driver. 86 */ 87 drm_WARN(&i915->drm, 1, 88 "Power well %d not defined for this platform\n", 89 power_well_id); 90 return &i915->display.power.domains.power_wells[0]; 91 } 92 93 void intel_power_well_enable(struct drm_i915_private *i915, 94 struct i915_power_well *power_well) 95 { 96 drm_dbg_kms(&i915->drm, "enabling %s\n", intel_power_well_name(power_well)); 97 power_well->desc->ops->enable(i915, power_well); 98 power_well->hw_enabled = true; 99 } 100 101 void intel_power_well_disable(struct drm_i915_private *i915, 102 struct i915_power_well *power_well) 103 { 104 drm_dbg_kms(&i915->drm, "disabling %s\n", intel_power_well_name(power_well)); 105 power_well->hw_enabled = false; 106 power_well->desc->ops->disable(i915, power_well); 107 } 108 109 void intel_power_well_sync_hw(struct drm_i915_private *i915, 110 struct i915_power_well *power_well) 111 { 112 power_well->desc->ops->sync_hw(i915, power_well); 113 power_well->hw_enabled = 114 power_well->desc->ops->is_enabled(i915, power_well); 115 } 116 117 void intel_power_well_get(struct drm_i915_private *i915, 118 struct i915_power_well *power_well) 119 { 120 if (!power_well->count++) 121 intel_power_well_enable(i915, power_well); 122 } 123 124 void intel_power_well_put(struct drm_i915_private *i915, 125 struct i915_power_well *power_well) 126 { 127 drm_WARN(&i915->drm, !power_well->count, 128 "Use count on power well %s is already zero", 129 i915_power_well_instance(power_well)->name); 130 131 if (!--power_well->count) 132 intel_power_well_disable(i915, power_well); 133 } 134 135 bool intel_power_well_is_enabled(struct drm_i915_private *i915, 136 struct i915_power_well *power_well) 137 { 138 return power_well->desc->ops->is_enabled(i915, power_well); 139 } 140 141 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well) 142 { 143 return power_well->hw_enabled; 144 } 145 146 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 147 enum i915_power_well_id power_well_id) 148 { 149 struct i915_power_well *power_well; 150 151 power_well = lookup_power_well(dev_priv, power_well_id); 152 153 return intel_power_well_is_enabled(dev_priv, power_well); 154 } 155 156 bool intel_power_well_is_always_on(struct i915_power_well *power_well) 157 { 158 return power_well->desc->always_on; 159 } 160 161 const char *intel_power_well_name(struct i915_power_well *power_well) 162 { 163 return i915_power_well_instance(power_well)->name; 164 } 165 166 struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well) 167 { 168 return &power_well->domains; 169 } 170 171 int intel_power_well_refcount(struct i915_power_well *power_well) 172 { 173 return power_well->count; 174 } 175 176 /* 177 * Starting with Haswell, we have a "Power Down Well" that can be turned off 178 * when not needed anymore. We have 4 registers that can request the power well 179 * to be enabled, and it will only be disabled if none of the registers is 180 * requesting it to be enabled. 181 */ 182 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, 183 u8 irq_pipe_mask, bool has_vga) 184 { 185 if (has_vga) 186 intel_vga_reset_io_mem(dev_priv); 187 188 if (irq_pipe_mask) 189 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); 190 } 191 192 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, 193 u8 irq_pipe_mask) 194 { 195 if (irq_pipe_mask) 196 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); 197 } 198 199 #define ICL_AUX_PW_TO_CH(pw_idx) \ 200 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A) 201 202 #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \ 203 ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C) 204 205 static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well) 206 { 207 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 208 209 return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) : 210 ICL_AUX_PW_TO_CH(pw_idx); 211 } 212 213 static struct intel_digital_port * 214 aux_ch_to_digital_port(struct drm_i915_private *dev_priv, 215 enum aux_ch aux_ch) 216 { 217 struct intel_digital_port *dig_port = NULL; 218 struct intel_encoder *encoder; 219 220 for_each_intel_encoder(&dev_priv->drm, encoder) { 221 /* We'll check the MST primary port */ 222 if (encoder->type == INTEL_OUTPUT_DP_MST) 223 continue; 224 225 dig_port = enc_to_dig_port(encoder); 226 if (!dig_port) 227 continue; 228 229 if (dig_port->aux_ch != aux_ch) { 230 dig_port = NULL; 231 continue; 232 } 233 234 break; 235 } 236 237 return dig_port; 238 } 239 240 static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915, 241 const struct i915_power_well *power_well) 242 { 243 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 244 struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch); 245 246 return intel_port_to_phy(i915, dig_port->base.port); 247 } 248 249 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 250 struct i915_power_well *power_well, 251 bool timeout_expected) 252 { 253 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 254 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 255 256 /* 257 * For some power wells we're not supposed to watch the status bit for 258 * an ack, but rather just wait a fixed amount of time and then 259 * proceed. This is only used on DG2. 260 */ 261 if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) { 262 usleep_range(600, 1200); 263 return; 264 } 265 266 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 267 if (intel_de_wait_for_set(dev_priv, regs->driver, 268 HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) { 269 drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n", 270 intel_power_well_name(power_well)); 271 272 drm_WARN_ON(&dev_priv->drm, !timeout_expected); 273 274 } 275 } 276 277 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, 278 const struct i915_power_well_regs *regs, 279 int pw_idx) 280 { 281 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 282 u32 ret; 283 284 ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0; 285 ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0; 286 if (regs->kvmr.reg) 287 ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0; 288 ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0; 289 290 return ret; 291 } 292 293 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, 294 struct i915_power_well *power_well) 295 { 296 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 297 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 298 bool disabled; 299 u32 reqs; 300 301 /* 302 * Bspec doesn't require waiting for PWs to get disabled, but still do 303 * this for paranoia. The known cases where a PW will be forced on: 304 * - a KVMR request on any power well via the KVMR request register 305 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 306 * DEBUG request registers 307 * Skip the wait in case any of the request bits are set and print a 308 * diagnostic message. 309 */ 310 wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) & 311 HSW_PWR_WELL_CTL_STATE(pw_idx))) || 312 (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1); 313 if (disabled) 314 return; 315 316 drm_dbg_kms(&dev_priv->drm, 317 "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 318 intel_power_well_name(power_well), 319 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 320 } 321 322 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, 323 enum skl_power_gate pg) 324 { 325 /* Timeout 5us for PG#0, for other PGs 1us */ 326 drm_WARN_ON(&dev_priv->drm, 327 intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS, 328 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 329 } 330 331 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 332 struct i915_power_well *power_well) 333 { 334 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 335 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 336 337 if (power_well->desc->has_fuses) { 338 enum skl_power_gate pg; 339 340 pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 341 SKL_PW_CTL_IDX_TO_PG(pw_idx); 342 343 /* Wa_16013190616:adlp */ 344 if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1) 345 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); 346 347 /* 348 * For PW1 we have to wait both for the PW0/PG0 fuse state 349 * before enabling the power well and PW1/PG1's own fuse 350 * state after the enabling. For all other power wells with 351 * fuses we only have to wait for that PW/PG's fuse state 352 * after the enabling. 353 */ 354 if (pg == SKL_PG1) 355 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); 356 } 357 358 intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 359 360 hsw_wait_for_power_well_enable(dev_priv, power_well, false); 361 362 if (power_well->desc->has_fuses) { 363 enum skl_power_gate pg; 364 365 pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 366 SKL_PW_CTL_IDX_TO_PG(pw_idx); 367 gen9_wait_for_power_well_fuses(dev_priv, pg); 368 } 369 370 hsw_power_well_post_enable(dev_priv, 371 power_well->desc->irq_pipe_mask, 372 power_well->desc->has_vga); 373 } 374 375 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 376 struct i915_power_well *power_well) 377 { 378 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 379 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 380 381 hsw_power_well_pre_disable(dev_priv, 382 power_well->desc->irq_pipe_mask); 383 384 intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 385 hsw_wait_for_power_well_disable(dev_priv, power_well); 386 } 387 388 static bool intel_port_is_edp(struct drm_i915_private *i915, enum port port) 389 { 390 struct intel_encoder *encoder; 391 392 for_each_intel_encoder(&i915->drm, encoder) { 393 if (encoder->type == INTEL_OUTPUT_EDP && 394 encoder->port == port) 395 return true; 396 } 397 398 return false; 399 } 400 401 static void 402 icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, 403 struct i915_power_well *power_well) 404 { 405 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 406 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 407 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); 408 409 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); 410 411 intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 412 413 if (DISPLAY_VER(dev_priv) < 12) 414 intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(phy), 415 0, ICL_LANE_ENABLE_AUX); 416 417 hsw_wait_for_power_well_enable(dev_priv, power_well, false); 418 419 /* Display WA #1178: icl */ 420 if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && 421 !intel_port_is_edp(dev_priv, (enum port)phy)) 422 intel_de_rmw(dev_priv, ICL_AUX_ANAOVRD1(pw_idx), 423 0, ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS); 424 } 425 426 static void 427 icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, 428 struct i915_power_well *power_well) 429 { 430 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 431 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 432 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); 433 434 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); 435 436 intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(phy), ICL_LANE_ENABLE_AUX, 0); 437 438 intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 439 440 hsw_wait_for_power_well_disable(dev_priv, power_well); 441 } 442 443 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 444 445 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, 446 struct i915_power_well *power_well, 447 struct intel_digital_port *dig_port) 448 { 449 if (drm_WARN_ON(&dev_priv->drm, !dig_port)) 450 return; 451 452 if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 453 return; 454 455 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port)); 456 } 457 458 #else 459 460 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, 461 struct i915_power_well *power_well, 462 struct intel_digital_port *dig_port) 463 { 464 } 465 466 #endif 467 468 #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1) 469 470 static void icl_tc_cold_exit(struct drm_i915_private *i915) 471 { 472 int ret, tries = 0; 473 474 while (1) { 475 ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0, 476 250, 1); 477 if (ret != -EAGAIN || ++tries == 3) 478 break; 479 msleep(1); 480 } 481 482 /* Spec states that TC cold exit can take up to 1ms to complete */ 483 if (!ret) 484 msleep(1); 485 486 /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */ 487 drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" : 488 "succeeded"); 489 } 490 491 static void 492 icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, 493 struct i915_power_well *power_well) 494 { 495 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 496 struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch); 497 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 498 bool is_tbt = power_well->desc->is_tc_tbt; 499 bool timeout_expected; 500 501 icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port); 502 503 intel_de_rmw(dev_priv, DP_AUX_CH_CTL(aux_ch), 504 DP_AUX_CH_CTL_TBT_IO, is_tbt ? DP_AUX_CH_CTL_TBT_IO : 0); 505 506 intel_de_rmw(dev_priv, regs->driver, 507 0, 508 HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx)); 509 510 /* 511 * An AUX timeout is expected if the TBT DP tunnel is down, 512 * or need to enable AUX on a legacy TypeC port as part of the TC-cold 513 * exit sequence. 514 */ 515 timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port); 516 if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 517 icl_tc_cold_exit(dev_priv); 518 519 hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected); 520 521 if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) { 522 enum tc_port tc_port; 523 524 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); 525 526 if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) & 527 DKL_CMN_UC_DW27_UC_HEALTH, 1)) 528 drm_warn(&dev_priv->drm, 529 "Timeout waiting TC uC health\n"); 530 } 531 } 532 533 static void 534 icl_aux_power_well_enable(struct drm_i915_private *dev_priv, 535 struct i915_power_well *power_well) 536 { 537 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); 538 539 if (intel_phy_is_tc(dev_priv, phy)) 540 return icl_tc_phy_aux_power_well_enable(dev_priv, power_well); 541 else if (IS_ICELAKE(dev_priv)) 542 return icl_combo_phy_aux_power_well_enable(dev_priv, 543 power_well); 544 else 545 return hsw_power_well_enable(dev_priv, power_well); 546 } 547 548 static void 549 icl_aux_power_well_disable(struct drm_i915_private *dev_priv, 550 struct i915_power_well *power_well) 551 { 552 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); 553 554 if (intel_phy_is_tc(dev_priv, phy)) 555 return hsw_power_well_disable(dev_priv, power_well); 556 else if (IS_ICELAKE(dev_priv)) 557 return icl_combo_phy_aux_power_well_disable(dev_priv, 558 power_well); 559 else 560 return hsw_power_well_disable(dev_priv, power_well); 561 } 562 563 /* 564 * We should only use the power well if we explicitly asked the hardware to 565 * enable it, so check if it's enabled and also check if we've requested it to 566 * be enabled. 567 */ 568 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 569 struct i915_power_well *power_well) 570 { 571 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 572 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 573 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 574 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) | 575 HSW_PWR_WELL_CTL_STATE(pw_idx); 576 u32 val; 577 578 val = intel_de_read(dev_priv, regs->driver); 579 580 /* 581 * On GEN9 big core due to a DMC bug the driver's request bits for PW1 582 * and the MISC_IO PW will be not restored, so check instead for the 583 * BIOS's own request bits, which are forced-on for these power wells 584 * when exiting DC5/6. 585 */ 586 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && 587 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO)) 588 val |= intel_de_read(dev_priv, regs->bios); 589 590 return (val & mask) == mask; 591 } 592 593 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 594 { 595 drm_WARN_ONCE(&dev_priv->drm, 596 (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9), 597 "DC9 already programmed to be enabled.\n"); 598 drm_WARN_ONCE(&dev_priv->drm, 599 intel_de_read(dev_priv, DC_STATE_EN) & 600 DC_STATE_EN_UPTO_DC5, 601 "DC5 still not disabled to enable DC9.\n"); 602 drm_WARN_ONCE(&dev_priv->drm, 603 intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) & 604 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), 605 "Power well 2 on.\n"); 606 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), 607 "Interrupts not disabled yet.\n"); 608 609 /* 610 * TODO: check for the following to verify the conditions to enter DC9 611 * state are satisfied: 612 * 1] Check relevant display engine registers to verify if mode set 613 * disable sequence was followed. 614 * 2] Check if display uninitialize sequence is initialized. 615 */ 616 } 617 618 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 619 { 620 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), 621 "Interrupts not disabled yet.\n"); 622 drm_WARN_ONCE(&dev_priv->drm, 623 intel_de_read(dev_priv, DC_STATE_EN) & 624 DC_STATE_EN_UPTO_DC5, 625 "DC5 still not disabled.\n"); 626 627 /* 628 * TODO: check for the following to verify DC9 state was indeed 629 * entered before programming to disable it: 630 * 1] Check relevant display engine registers to verify if mode 631 * set disable sequence was followed. 632 * 2] Check if display uninitialize sequence is initialized. 633 */ 634 } 635 636 static void gen9_write_dc_state(struct drm_i915_private *dev_priv, 637 u32 state) 638 { 639 int rewrites = 0; 640 int rereads = 0; 641 u32 v; 642 643 intel_de_write(dev_priv, DC_STATE_EN, state); 644 645 /* It has been observed that disabling the dc6 state sometimes 646 * doesn't stick and dmc keeps returning old value. Make sure 647 * the write really sticks enough times and also force rewrite until 648 * we are confident that state is exactly what we want. 649 */ 650 do { 651 v = intel_de_read(dev_priv, DC_STATE_EN); 652 653 if (v != state) { 654 intel_de_write(dev_priv, DC_STATE_EN, state); 655 rewrites++; 656 rereads = 0; 657 } else if (rereads++ > 5) { 658 break; 659 } 660 661 } while (rewrites < 100); 662 663 if (v != state) 664 drm_err(&dev_priv->drm, 665 "Writing dc state to 0x%x failed, now 0x%x\n", 666 state, v); 667 668 /* Most of the times we need one retry, avoid spam */ 669 if (rewrites > 1) 670 drm_dbg_kms(&dev_priv->drm, 671 "Rewrote dc state to 0x%x %d times\n", 672 state, rewrites); 673 } 674 675 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) 676 { 677 u32 mask; 678 679 mask = DC_STATE_EN_UPTO_DC5; 680 681 if (DISPLAY_VER(dev_priv) >= 12) 682 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6 683 | DC_STATE_EN_DC9; 684 else if (DISPLAY_VER(dev_priv) == 11) 685 mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; 686 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 687 mask |= DC_STATE_EN_DC9; 688 else 689 mask |= DC_STATE_EN_UPTO_DC6; 690 691 return mask; 692 } 693 694 void gen9_sanitize_dc_state(struct drm_i915_private *i915) 695 { 696 struct i915_power_domains *power_domains = &i915->display.power.domains; 697 u32 val; 698 699 if (!HAS_DISPLAY(i915)) 700 return; 701 702 val = intel_de_read(i915, DC_STATE_EN) & gen9_dc_mask(i915); 703 704 drm_dbg_kms(&i915->drm, 705 "Resetting DC state tracking from %02x to %02x\n", 706 power_domains->dc_state, val); 707 power_domains->dc_state = val; 708 } 709 710 /** 711 * gen9_set_dc_state - set target display C power state 712 * @dev_priv: i915 device instance 713 * @state: target DC power state 714 * - DC_STATE_DISABLE 715 * - DC_STATE_EN_UPTO_DC5 716 * - DC_STATE_EN_UPTO_DC6 717 * - DC_STATE_EN_DC9 718 * 719 * Signal to DMC firmware/HW the target DC power state passed in @state. 720 * DMC/HW can turn off individual display clocks and power rails when entering 721 * a deeper DC power state (higher in number) and turns these back when exiting 722 * that state to a shallower power state (lower in number). The HW will decide 723 * when to actually enter a given state on an on-demand basis, for instance 724 * depending on the active state of display pipes. The state of display 725 * registers backed by affected power rails are saved/restored as needed. 726 * 727 * Based on the above enabling a deeper DC power state is asynchronous wrt. 728 * enabling it. Disabling a deeper power state is synchronous: for instance 729 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned 730 * back on and register state is restored. This is guaranteed by the MMIO write 731 * to DC_STATE_EN blocking until the state is restored. 732 */ 733 void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) 734 { 735 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 736 u32 val; 737 u32 mask; 738 739 if (!HAS_DISPLAY(dev_priv)) 740 return; 741 742 if (drm_WARN_ON_ONCE(&dev_priv->drm, 743 state & ~power_domains->allowed_dc_mask)) 744 state &= power_domains->allowed_dc_mask; 745 746 val = intel_de_read(dev_priv, DC_STATE_EN); 747 mask = gen9_dc_mask(dev_priv); 748 drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n", 749 val & mask, state); 750 751 /* Check if DMC is ignoring our DC state requests */ 752 if ((val & mask) != power_domains->dc_state) 753 drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n", 754 power_domains->dc_state, val & mask); 755 756 val &= ~mask; 757 val |= state; 758 759 gen9_write_dc_state(dev_priv, val); 760 761 power_domains->dc_state = val & mask; 762 } 763 764 static void tgl_enable_dc3co(struct drm_i915_private *dev_priv) 765 { 766 drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n"); 767 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO); 768 } 769 770 static void tgl_disable_dc3co(struct drm_i915_private *dev_priv) 771 { 772 drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n"); 773 intel_de_rmw(dev_priv, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); 774 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 775 /* 776 * Delay of 200us DC3CO Exit time B.Spec 49196 777 */ 778 usleep_range(200, 210); 779 } 780 781 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 782 { 783 enum i915_power_well_id high_pg; 784 785 /* Power wells at this level and above must be disabled for DC5 entry */ 786 if (DISPLAY_VER(dev_priv) == 12) 787 high_pg = ICL_DISP_PW_3; 788 else 789 high_pg = SKL_DISP_PW_2; 790 791 drm_WARN_ONCE(&dev_priv->drm, 792 intel_display_power_well_is_enabled(dev_priv, high_pg), 793 "Power wells above platform's DC5 limit still enabled.\n"); 794 795 drm_WARN_ONCE(&dev_priv->drm, 796 (intel_de_read(dev_priv, DC_STATE_EN) & 797 DC_STATE_EN_UPTO_DC5), 798 "DC5 already programmed to be enabled.\n"); 799 assert_rpm_wakelock_held(&dev_priv->runtime_pm); 800 801 assert_dmc_loaded(dev_priv); 802 } 803 804 void gen9_enable_dc5(struct drm_i915_private *dev_priv) 805 { 806 assert_can_enable_dc5(dev_priv); 807 808 drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n"); 809 810 /* Wa Display #1183: skl,kbl,cfl */ 811 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 812 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 813 0, SKL_SELECT_ALTERNATE_DC_EXIT); 814 815 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 816 } 817 818 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 819 { 820 drm_WARN_ONCE(&dev_priv->drm, 821 intel_de_read(dev_priv, UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 822 "Backlight is not disabled.\n"); 823 drm_WARN_ONCE(&dev_priv->drm, 824 (intel_de_read(dev_priv, DC_STATE_EN) & 825 DC_STATE_EN_UPTO_DC6), 826 "DC6 already programmed to be enabled.\n"); 827 828 assert_dmc_loaded(dev_priv); 829 } 830 831 void skl_enable_dc6(struct drm_i915_private *dev_priv) 832 { 833 assert_can_enable_dc6(dev_priv); 834 835 drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n"); 836 837 /* Wa Display #1183: skl,kbl,cfl */ 838 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 839 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 840 0, SKL_SELECT_ALTERNATE_DC_EXIT); 841 842 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 843 } 844 845 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 846 { 847 assert_can_enable_dc9(dev_priv); 848 849 drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n"); 850 /* 851 * Power sequencer reset is not needed on 852 * platforms with South Display Engine on PCH, 853 * because PPS registers are always on. 854 */ 855 if (!HAS_PCH_SPLIT(dev_priv)) 856 intel_pps_reset_all(dev_priv); 857 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); 858 } 859 860 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 861 { 862 assert_can_disable_dc9(dev_priv); 863 864 drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n"); 865 866 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 867 868 intel_pps_unlock_regs_wa(dev_priv); 869 } 870 871 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 872 struct i915_power_well *power_well) 873 { 874 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 875 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 876 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 877 u32 bios_req = intel_de_read(dev_priv, regs->bios); 878 879 /* Take over the request bit if set by BIOS. */ 880 if (bios_req & mask) { 881 u32 drv_req = intel_de_read(dev_priv, regs->driver); 882 883 if (!(drv_req & mask)) 884 intel_de_write(dev_priv, regs->driver, drv_req | mask); 885 intel_de_write(dev_priv, regs->bios, bios_req & ~mask); 886 } 887 } 888 889 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 890 struct i915_power_well *power_well) 891 { 892 bxt_ddi_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 893 } 894 895 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 896 struct i915_power_well *power_well) 897 { 898 bxt_ddi_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 899 } 900 901 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, 902 struct i915_power_well *power_well) 903 { 904 return bxt_ddi_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 905 } 906 907 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) 908 { 909 struct i915_power_well *power_well; 910 911 power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A); 912 if (intel_power_well_refcount(power_well) > 0) 913 bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 914 915 power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 916 if (intel_power_well_refcount(power_well) > 0) 917 bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 918 919 if (IS_GEMINILAKE(dev_priv)) { 920 power_well = lookup_power_well(dev_priv, 921 GLK_DISP_PW_DPIO_CMN_C); 922 if (intel_power_well_refcount(power_well) > 0) 923 bxt_ddi_phy_verify_state(dev_priv, 924 i915_power_well_instance(power_well)->bxt.phy); 925 } 926 } 927 928 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 929 struct i915_power_well *power_well) 930 { 931 return ((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && 932 (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); 933 } 934 935 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) 936 { 937 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv); 938 u8 enabled_dbuf_slices = dev_priv->display.dbuf.enabled_slices; 939 940 drm_WARN(&dev_priv->drm, 941 hw_enabled_dbuf_slices != enabled_dbuf_slices, 942 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", 943 hw_enabled_dbuf_slices, 944 enabled_dbuf_slices); 945 } 946 947 void gen9_disable_dc_states(struct drm_i915_private *dev_priv) 948 { 949 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 950 struct intel_cdclk_config cdclk_config = {}; 951 952 if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) { 953 tgl_disable_dc3co(dev_priv); 954 return; 955 } 956 957 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 958 959 if (!HAS_DISPLAY(dev_priv)) 960 return; 961 962 intel_cdclk_get_cdclk(dev_priv, &cdclk_config); 963 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 964 drm_WARN_ON(&dev_priv->drm, 965 intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw, 966 &cdclk_config)); 967 968 gen9_assert_dbuf_enabled(dev_priv); 969 970 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 971 bxt_verify_ddi_phy_power_wells(dev_priv); 972 973 if (DISPLAY_VER(dev_priv) >= 11) 974 /* 975 * DMC retains HW context only for port A, the other combo 976 * PHY's HW context for port B is lost after DC transitions, 977 * so we need to restore it manually. 978 */ 979 intel_combo_phy_init(dev_priv); 980 } 981 982 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 983 struct i915_power_well *power_well) 984 { 985 gen9_disable_dc_states(dev_priv); 986 } 987 988 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 989 struct i915_power_well *power_well) 990 { 991 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 992 993 if (!intel_dmc_has_payload(dev_priv)) 994 return; 995 996 switch (power_domains->target_dc_state) { 997 case DC_STATE_EN_DC3CO: 998 tgl_enable_dc3co(dev_priv); 999 break; 1000 case DC_STATE_EN_UPTO_DC6: 1001 skl_enable_dc6(dev_priv); 1002 break; 1003 case DC_STATE_EN_UPTO_DC5: 1004 gen9_enable_dc5(dev_priv); 1005 break; 1006 } 1007 } 1008 1009 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, 1010 struct i915_power_well *power_well) 1011 { 1012 } 1013 1014 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 1015 struct i915_power_well *power_well) 1016 { 1017 } 1018 1019 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 1020 struct i915_power_well *power_well) 1021 { 1022 return true; 1023 } 1024 1025 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, 1026 struct i915_power_well *power_well) 1027 { 1028 if ((intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE) == 0) 1029 i830_enable_pipe(dev_priv, PIPE_A); 1030 if ((intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE) == 0) 1031 i830_enable_pipe(dev_priv, PIPE_B); 1032 } 1033 1034 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, 1035 struct i915_power_well *power_well) 1036 { 1037 i830_disable_pipe(dev_priv, PIPE_B); 1038 i830_disable_pipe(dev_priv, PIPE_A); 1039 } 1040 1041 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, 1042 struct i915_power_well *power_well) 1043 { 1044 return intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE && 1045 intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; 1046 } 1047 1048 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, 1049 struct i915_power_well *power_well) 1050 { 1051 if (intel_power_well_refcount(power_well) > 0) 1052 i830_pipes_power_well_enable(dev_priv, power_well); 1053 else 1054 i830_pipes_power_well_disable(dev_priv, power_well); 1055 } 1056 1057 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 1058 struct i915_power_well *power_well, bool enable) 1059 { 1060 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1061 u32 mask; 1062 u32 state; 1063 u32 ctrl; 1064 1065 mask = PUNIT_PWRGT_MASK(pw_idx); 1066 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : 1067 PUNIT_PWRGT_PWR_GATE(pw_idx); 1068 1069 vlv_punit_get(dev_priv); 1070 1071 #define COND \ 1072 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 1073 1074 if (COND) 1075 goto out; 1076 1077 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 1078 ctrl &= ~mask; 1079 ctrl |= state; 1080 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 1081 1082 if (wait_for(COND, 100)) 1083 drm_err(&dev_priv->drm, 1084 "timeout setting power well state %08x (%08x)\n", 1085 state, 1086 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 1087 1088 #undef COND 1089 1090 out: 1091 vlv_punit_put(dev_priv); 1092 } 1093 1094 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 1095 struct i915_power_well *power_well) 1096 { 1097 vlv_set_power_well(dev_priv, power_well, true); 1098 } 1099 1100 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 1101 struct i915_power_well *power_well) 1102 { 1103 vlv_set_power_well(dev_priv, power_well, false); 1104 } 1105 1106 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 1107 struct i915_power_well *power_well) 1108 { 1109 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1110 bool enabled = false; 1111 u32 mask; 1112 u32 state; 1113 u32 ctrl; 1114 1115 mask = PUNIT_PWRGT_MASK(pw_idx); 1116 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); 1117 1118 vlv_punit_get(dev_priv); 1119 1120 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 1121 /* 1122 * We only ever set the power-on and power-gate states, anything 1123 * else is unexpected. 1124 */ 1125 drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && 1126 state != PUNIT_PWRGT_PWR_GATE(pw_idx)); 1127 if (state == ctrl) 1128 enabled = true; 1129 1130 /* 1131 * A transient state at this point would mean some unexpected party 1132 * is poking at the power controls too. 1133 */ 1134 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 1135 drm_WARN_ON(&dev_priv->drm, ctrl != state); 1136 1137 vlv_punit_put(dev_priv); 1138 1139 return enabled; 1140 } 1141 1142 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 1143 { 1144 /* 1145 * On driver load, a pipe may be active and driving a DSI display. 1146 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 1147 * (and never recovering) in this case. intel_dsi_post_disable() will 1148 * clear it when we turn off the display. 1149 */ 1150 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), 1151 ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE); 1152 1153 /* 1154 * Disable trickle feed and enable pnd deadline calculation 1155 */ 1156 intel_de_write(dev_priv, MI_ARB_VLV, 1157 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 1158 intel_de_write(dev_priv, CBR1_VLV, 0); 1159 1160 drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0); 1161 intel_de_write(dev_priv, RAWCLK_FREQ_VLV, 1162 DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 1163 1000)); 1164 } 1165 1166 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 1167 { 1168 struct intel_encoder *encoder; 1169 enum pipe pipe; 1170 1171 /* 1172 * Enable the CRI clock source so we can get at the 1173 * display and the reference clock for VGA 1174 * hotplug / manual detection. Supposedly DSI also 1175 * needs the ref clock up and running. 1176 * 1177 * CHV DPLL B/C have some issues if VGA mode is enabled. 1178 */ 1179 for_each_pipe(dev_priv, pipe) { 1180 u32 val = intel_de_read(dev_priv, DPLL(pipe)); 1181 1182 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1183 if (pipe != PIPE_A) 1184 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1185 1186 intel_de_write(dev_priv, DPLL(pipe), val); 1187 } 1188 1189 vlv_init_display_clock_gating(dev_priv); 1190 1191 spin_lock_irq(&dev_priv->irq_lock); 1192 valleyview_enable_display_irqs(dev_priv); 1193 spin_unlock_irq(&dev_priv->irq_lock); 1194 1195 /* 1196 * During driver initialization/resume we can avoid restoring the 1197 * part of the HW/SW state that will be inited anyway explicitly. 1198 */ 1199 if (dev_priv->display.power.domains.initializing) 1200 return; 1201 1202 intel_hpd_init(dev_priv); 1203 intel_hpd_poll_disable(dev_priv); 1204 1205 /* Re-enable the ADPA, if we have one */ 1206 for_each_intel_encoder(&dev_priv->drm, encoder) { 1207 if (encoder->type == INTEL_OUTPUT_ANALOG) 1208 intel_crt_reset(&encoder->base); 1209 } 1210 1211 intel_vga_redisable_power_on(dev_priv); 1212 1213 intel_pps_unlock_regs_wa(dev_priv); 1214 } 1215 1216 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 1217 { 1218 spin_lock_irq(&dev_priv->irq_lock); 1219 valleyview_disable_display_irqs(dev_priv); 1220 spin_unlock_irq(&dev_priv->irq_lock); 1221 1222 /* make sure we're done processing display irqs */ 1223 intel_synchronize_irq(dev_priv); 1224 1225 intel_pps_reset_all(dev_priv); 1226 1227 /* Prevent us from re-enabling polling on accident in late suspend */ 1228 if (!dev_priv->drm.dev->power.is_suspended) 1229 intel_hpd_poll_enable(dev_priv); 1230 } 1231 1232 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 1233 struct i915_power_well *power_well) 1234 { 1235 vlv_set_power_well(dev_priv, power_well, true); 1236 1237 vlv_display_power_well_init(dev_priv); 1238 } 1239 1240 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 1241 struct i915_power_well *power_well) 1242 { 1243 vlv_display_power_well_deinit(dev_priv); 1244 1245 vlv_set_power_well(dev_priv, power_well, false); 1246 } 1247 1248 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1249 struct i915_power_well *power_well) 1250 { 1251 /* since ref/cri clock was enabled */ 1252 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1253 1254 vlv_set_power_well(dev_priv, power_well, true); 1255 1256 /* 1257 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1258 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1259 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1260 * b. The other bits such as sfr settings / modesel may all 1261 * be set to 0. 1262 * 1263 * This should only be done on init and resume from S3 with 1264 * both PLLs disabled, or we risk losing DPIO and PLL 1265 * synchronization. 1266 */ 1267 intel_de_rmw(dev_priv, DPIO_CTL, 0, DPIO_CMNRST); 1268 } 1269 1270 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1271 struct i915_power_well *power_well) 1272 { 1273 enum pipe pipe; 1274 1275 for_each_pipe(dev_priv, pipe) 1276 assert_pll_disabled(dev_priv, pipe); 1277 1278 /* Assert common reset */ 1279 intel_de_rmw(dev_priv, DPIO_CTL, DPIO_CMNRST, 0); 1280 1281 vlv_set_power_well(dev_priv, power_well, false); 1282 } 1283 1284 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1285 1286 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1287 { 1288 struct i915_power_well *cmn_bc = 1289 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 1290 struct i915_power_well *cmn_d = 1291 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D); 1292 u32 phy_control = dev_priv->display.power.chv_phy_control; 1293 u32 phy_status = 0; 1294 u32 phy_status_mask = 0xffffffff; 1295 1296 /* 1297 * The BIOS can leave the PHY is some weird state 1298 * where it doesn't fully power down some parts. 1299 * Disable the asserts until the PHY has been fully 1300 * reset (ie. the power well has been disabled at 1301 * least once). 1302 */ 1303 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0]) 1304 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1305 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1306 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1307 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1308 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1309 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1310 1311 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1]) 1312 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1313 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1314 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1315 1316 if (intel_power_well_is_enabled(dev_priv, cmn_bc)) { 1317 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1318 1319 /* this assumes override is only used to enable lanes */ 1320 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1321 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1322 1323 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1324 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1325 1326 /* CL1 is on whenever anything is on in either channel */ 1327 if (BITS_SET(phy_control, 1328 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1329 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1330 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1331 1332 /* 1333 * The DPLLB check accounts for the pipe B + port A usage 1334 * with CL2 powered up but all the lanes in the second channel 1335 * powered down. 1336 */ 1337 if (BITS_SET(phy_control, 1338 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1339 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1340 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1341 1342 if (BITS_SET(phy_control, 1343 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1344 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1345 if (BITS_SET(phy_control, 1346 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1347 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1348 1349 if (BITS_SET(phy_control, 1350 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1351 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1352 if (BITS_SET(phy_control, 1353 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1354 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1355 } 1356 1357 if (intel_power_well_is_enabled(dev_priv, cmn_d)) { 1358 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1359 1360 /* this assumes override is only used to enable lanes */ 1361 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1362 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1363 1364 if (BITS_SET(phy_control, 1365 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1366 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1367 1368 if (BITS_SET(phy_control, 1369 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1370 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1371 if (BITS_SET(phy_control, 1372 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1373 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1374 } 1375 1376 phy_status &= phy_status_mask; 1377 1378 /* 1379 * The PHY may be busy with some initial calibration and whatnot, 1380 * so the power state can take a while to actually change. 1381 */ 1382 if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS, 1383 phy_status_mask, phy_status, 10)) 1384 drm_err(&dev_priv->drm, 1385 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1386 intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask, 1387 phy_status, dev_priv->display.power.chv_phy_control); 1388 } 1389 1390 #undef BITS_SET 1391 1392 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1393 struct i915_power_well *power_well) 1394 { 1395 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1396 enum dpio_phy phy; 1397 enum pipe pipe; 1398 u32 tmp; 1399 1400 drm_WARN_ON_ONCE(&dev_priv->drm, 1401 id != VLV_DISP_PW_DPIO_CMN_BC && 1402 id != CHV_DISP_PW_DPIO_CMN_D); 1403 1404 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1405 pipe = PIPE_A; 1406 phy = DPIO_PHY0; 1407 } else { 1408 pipe = PIPE_C; 1409 phy = DPIO_PHY1; 1410 } 1411 1412 /* since ref/cri clock was enabled */ 1413 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1414 vlv_set_power_well(dev_priv, power_well, true); 1415 1416 /* Poll for phypwrgood signal */ 1417 if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS, 1418 PHY_POWERGOOD(phy), 1)) 1419 drm_err(&dev_priv->drm, "Display PHY %d is not power up\n", 1420 phy); 1421 1422 vlv_dpio_get(dev_priv); 1423 1424 /* Enable dynamic power down */ 1425 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1426 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1427 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1428 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1429 1430 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1431 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1432 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1433 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1434 } else { 1435 /* 1436 * Force the non-existing CL2 off. BXT does this 1437 * too, so maybe it saves some power even though 1438 * CL2 doesn't exist? 1439 */ 1440 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1441 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1442 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1443 } 1444 1445 vlv_dpio_put(dev_priv); 1446 1447 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1448 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1449 dev_priv->display.power.chv_phy_control); 1450 1451 drm_dbg_kms(&dev_priv->drm, 1452 "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1453 phy, dev_priv->display.power.chv_phy_control); 1454 1455 assert_chv_phy_status(dev_priv); 1456 } 1457 1458 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1459 struct i915_power_well *power_well) 1460 { 1461 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1462 enum dpio_phy phy; 1463 1464 drm_WARN_ON_ONCE(&dev_priv->drm, 1465 id != VLV_DISP_PW_DPIO_CMN_BC && 1466 id != CHV_DISP_PW_DPIO_CMN_D); 1467 1468 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1469 phy = DPIO_PHY0; 1470 assert_pll_disabled(dev_priv, PIPE_A); 1471 assert_pll_disabled(dev_priv, PIPE_B); 1472 } else { 1473 phy = DPIO_PHY1; 1474 assert_pll_disabled(dev_priv, PIPE_C); 1475 } 1476 1477 dev_priv->display.power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1478 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1479 dev_priv->display.power.chv_phy_control); 1480 1481 vlv_set_power_well(dev_priv, power_well, false); 1482 1483 drm_dbg_kms(&dev_priv->drm, 1484 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1485 phy, dev_priv->display.power.chv_phy_control); 1486 1487 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1488 dev_priv->display.power.chv_phy_assert[phy] = true; 1489 1490 assert_chv_phy_status(dev_priv); 1491 } 1492 1493 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1494 enum dpio_channel ch, bool override, unsigned int mask) 1495 { 1496 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1497 u32 reg, val, expected, actual; 1498 1499 /* 1500 * The BIOS can leave the PHY is some weird state 1501 * where it doesn't fully power down some parts. 1502 * Disable the asserts until the PHY has been fully 1503 * reset (ie. the power well has been disabled at 1504 * least once). 1505 */ 1506 if (!dev_priv->display.power.chv_phy_assert[phy]) 1507 return; 1508 1509 if (ch == DPIO_CH0) 1510 reg = _CHV_CMN_DW0_CH0; 1511 else 1512 reg = _CHV_CMN_DW6_CH1; 1513 1514 vlv_dpio_get(dev_priv); 1515 val = vlv_dpio_read(dev_priv, pipe, reg); 1516 vlv_dpio_put(dev_priv); 1517 1518 /* 1519 * This assumes !override is only used when the port is disabled. 1520 * All lanes should power down even without the override when 1521 * the port is disabled. 1522 */ 1523 if (!override || mask == 0xf) { 1524 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1525 /* 1526 * If CH1 common lane is not active anymore 1527 * (eg. for pipe B DPLL) the entire channel will 1528 * shut down, which causes the common lane registers 1529 * to read as 0. That means we can't actually check 1530 * the lane power down status bits, but as the entire 1531 * register reads as 0 it's a good indication that the 1532 * channel is indeed entirely powered down. 1533 */ 1534 if (ch == DPIO_CH1 && val == 0) 1535 expected = 0; 1536 } else if (mask != 0x0) { 1537 expected = DPIO_ANYDL_POWERDOWN; 1538 } else { 1539 expected = 0; 1540 } 1541 1542 if (ch == DPIO_CH0) 1543 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1544 else 1545 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1546 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1547 1548 drm_WARN(&dev_priv->drm, actual != expected, 1549 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1550 !!(actual & DPIO_ALLDL_POWERDOWN), 1551 !!(actual & DPIO_ANYDL_POWERDOWN), 1552 !!(expected & DPIO_ALLDL_POWERDOWN), 1553 !!(expected & DPIO_ANYDL_POWERDOWN), 1554 reg, val); 1555 } 1556 1557 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1558 enum dpio_channel ch, bool override) 1559 { 1560 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1561 bool was_override; 1562 1563 mutex_lock(&power_domains->lock); 1564 1565 was_override = dev_priv->display.power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1566 1567 if (override == was_override) 1568 goto out; 1569 1570 if (override) 1571 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1572 else 1573 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1574 1575 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1576 dev_priv->display.power.chv_phy_control); 1577 1578 drm_dbg_kms(&dev_priv->drm, 1579 "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1580 phy, ch, dev_priv->display.power.chv_phy_control); 1581 1582 assert_chv_phy_status(dev_priv); 1583 1584 out: 1585 mutex_unlock(&power_domains->lock); 1586 1587 return was_override; 1588 } 1589 1590 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1591 bool override, unsigned int mask) 1592 { 1593 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1594 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1595 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); 1596 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); 1597 1598 mutex_lock(&power_domains->lock); 1599 1600 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1601 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1602 1603 if (override) 1604 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1605 else 1606 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1607 1608 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1609 dev_priv->display.power.chv_phy_control); 1610 1611 drm_dbg_kms(&dev_priv->drm, 1612 "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1613 phy, ch, mask, dev_priv->display.power.chv_phy_control); 1614 1615 assert_chv_phy_status(dev_priv); 1616 1617 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1618 1619 mutex_unlock(&power_domains->lock); 1620 } 1621 1622 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1623 struct i915_power_well *power_well) 1624 { 1625 enum pipe pipe = PIPE_A; 1626 bool enabled; 1627 u32 state, ctrl; 1628 1629 vlv_punit_get(dev_priv); 1630 1631 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); 1632 /* 1633 * We only ever set the power-on and power-gate states, anything 1634 * else is unexpected. 1635 */ 1636 drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) && 1637 state != DP_SSS_PWR_GATE(pipe)); 1638 enabled = state == DP_SSS_PWR_ON(pipe); 1639 1640 /* 1641 * A transient state at this point would mean some unexpected party 1642 * is poking at the power controls too. 1643 */ 1644 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); 1645 drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state); 1646 1647 vlv_punit_put(dev_priv); 1648 1649 return enabled; 1650 } 1651 1652 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1653 struct i915_power_well *power_well, 1654 bool enable) 1655 { 1656 enum pipe pipe = PIPE_A; 1657 u32 state; 1658 u32 ctrl; 1659 1660 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1661 1662 vlv_punit_get(dev_priv); 1663 1664 #define COND \ 1665 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) 1666 1667 if (COND) 1668 goto out; 1669 1670 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 1671 ctrl &= ~DP_SSC_MASK(pipe); 1672 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1673 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl); 1674 1675 if (wait_for(COND, 100)) 1676 drm_err(&dev_priv->drm, 1677 "timeout setting power well state %08x (%08x)\n", 1678 state, 1679 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); 1680 1681 #undef COND 1682 1683 out: 1684 vlv_punit_put(dev_priv); 1685 } 1686 1687 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 1688 struct i915_power_well *power_well) 1689 { 1690 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1691 dev_priv->display.power.chv_phy_control); 1692 } 1693 1694 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1695 struct i915_power_well *power_well) 1696 { 1697 chv_set_pipe_power_well(dev_priv, power_well, true); 1698 1699 vlv_display_power_well_init(dev_priv); 1700 } 1701 1702 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1703 struct i915_power_well *power_well) 1704 { 1705 vlv_display_power_well_deinit(dev_priv); 1706 1707 chv_set_pipe_power_well(dev_priv, power_well, false); 1708 } 1709 1710 static void 1711 tgl_tc_cold_request(struct drm_i915_private *i915, bool block) 1712 { 1713 u8 tries = 0; 1714 int ret; 1715 1716 while (1) { 1717 u32 low_val; 1718 u32 high_val = 0; 1719 1720 if (block) 1721 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ; 1722 else 1723 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ; 1724 1725 /* 1726 * Spec states that we should timeout the request after 200us 1727 * but the function below will timeout after 500us 1728 */ 1729 ret = snb_pcode_read(&i915->uncore, TGL_PCODE_TCCOLD, &low_val, &high_val); 1730 if (ret == 0) { 1731 if (block && 1732 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED)) 1733 ret = -EIO; 1734 else 1735 break; 1736 } 1737 1738 if (++tries == 3) 1739 break; 1740 1741 msleep(1); 1742 } 1743 1744 if (ret) 1745 drm_err(&i915->drm, "TC cold %sblock failed\n", 1746 block ? "" : "un"); 1747 else 1748 drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n", 1749 block ? "" : "un"); 1750 } 1751 1752 static void 1753 tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915, 1754 struct i915_power_well *power_well) 1755 { 1756 tgl_tc_cold_request(i915, true); 1757 } 1758 1759 static void 1760 tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915, 1761 struct i915_power_well *power_well) 1762 { 1763 tgl_tc_cold_request(i915, false); 1764 } 1765 1766 static void 1767 tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915, 1768 struct i915_power_well *power_well) 1769 { 1770 if (intel_power_well_refcount(power_well) > 0) 1771 tgl_tc_cold_off_power_well_enable(i915, power_well); 1772 else 1773 tgl_tc_cold_off_power_well_disable(i915, power_well); 1774 } 1775 1776 static bool 1777 tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv, 1778 struct i915_power_well *power_well) 1779 { 1780 /* 1781 * Not the correctly implementation but there is no way to just read it 1782 * from PCODE, so returning count to avoid state mismatch errors 1783 */ 1784 return intel_power_well_refcount(power_well); 1785 } 1786 1787 static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv, 1788 struct i915_power_well *power_well) 1789 { 1790 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1791 1792 intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch), 1793 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1794 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); 1795 1796 /* 1797 * The power status flag cannot be used to determine whether aux 1798 * power wells have finished powering up. Instead we're 1799 * expected to just wait a fixed 600us after raising the request 1800 * bit. 1801 */ 1802 usleep_range(600, 1200); 1803 } 1804 1805 static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv, 1806 struct i915_power_well *power_well) 1807 { 1808 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1809 1810 intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch), 1811 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1812 0); 1813 usleep_range(10, 30); 1814 } 1815 1816 static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv, 1817 struct i915_power_well *power_well) 1818 { 1819 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1820 1821 return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) & 1822 XELPDP_DP_AUX_CH_CTL_POWER_STATUS; 1823 } 1824 1825 const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1826 .sync_hw = i9xx_power_well_sync_hw_noop, 1827 .enable = i9xx_always_on_power_well_noop, 1828 .disable = i9xx_always_on_power_well_noop, 1829 .is_enabled = i9xx_always_on_power_well_enabled, 1830 }; 1831 1832 const struct i915_power_well_ops chv_pipe_power_well_ops = { 1833 .sync_hw = chv_pipe_power_well_sync_hw, 1834 .enable = chv_pipe_power_well_enable, 1835 .disable = chv_pipe_power_well_disable, 1836 .is_enabled = chv_pipe_power_well_enabled, 1837 }; 1838 1839 const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1840 .sync_hw = i9xx_power_well_sync_hw_noop, 1841 .enable = chv_dpio_cmn_power_well_enable, 1842 .disable = chv_dpio_cmn_power_well_disable, 1843 .is_enabled = vlv_power_well_enabled, 1844 }; 1845 1846 const struct i915_power_well_ops i830_pipes_power_well_ops = { 1847 .sync_hw = i830_pipes_power_well_sync_hw, 1848 .enable = i830_pipes_power_well_enable, 1849 .disable = i830_pipes_power_well_disable, 1850 .is_enabled = i830_pipes_power_well_enabled, 1851 }; 1852 1853 static const struct i915_power_well_regs hsw_power_well_regs = { 1854 .bios = HSW_PWR_WELL_CTL1, 1855 .driver = HSW_PWR_WELL_CTL2, 1856 .kvmr = HSW_PWR_WELL_CTL3, 1857 .debug = HSW_PWR_WELL_CTL4, 1858 }; 1859 1860 const struct i915_power_well_ops hsw_power_well_ops = { 1861 .regs = &hsw_power_well_regs, 1862 .sync_hw = hsw_power_well_sync_hw, 1863 .enable = hsw_power_well_enable, 1864 .disable = hsw_power_well_disable, 1865 .is_enabled = hsw_power_well_enabled, 1866 }; 1867 1868 const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1869 .sync_hw = i9xx_power_well_sync_hw_noop, 1870 .enable = gen9_dc_off_power_well_enable, 1871 .disable = gen9_dc_off_power_well_disable, 1872 .is_enabled = gen9_dc_off_power_well_enabled, 1873 }; 1874 1875 const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 1876 .sync_hw = i9xx_power_well_sync_hw_noop, 1877 .enable = bxt_dpio_cmn_power_well_enable, 1878 .disable = bxt_dpio_cmn_power_well_disable, 1879 .is_enabled = bxt_dpio_cmn_power_well_enabled, 1880 }; 1881 1882 const struct i915_power_well_ops vlv_display_power_well_ops = { 1883 .sync_hw = i9xx_power_well_sync_hw_noop, 1884 .enable = vlv_display_power_well_enable, 1885 .disable = vlv_display_power_well_disable, 1886 .is_enabled = vlv_power_well_enabled, 1887 }; 1888 1889 const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1890 .sync_hw = i9xx_power_well_sync_hw_noop, 1891 .enable = vlv_dpio_cmn_power_well_enable, 1892 .disable = vlv_dpio_cmn_power_well_disable, 1893 .is_enabled = vlv_power_well_enabled, 1894 }; 1895 1896 const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1897 .sync_hw = i9xx_power_well_sync_hw_noop, 1898 .enable = vlv_power_well_enable, 1899 .disable = vlv_power_well_disable, 1900 .is_enabled = vlv_power_well_enabled, 1901 }; 1902 1903 static const struct i915_power_well_regs icl_aux_power_well_regs = { 1904 .bios = ICL_PWR_WELL_CTL_AUX1, 1905 .driver = ICL_PWR_WELL_CTL_AUX2, 1906 .debug = ICL_PWR_WELL_CTL_AUX4, 1907 }; 1908 1909 const struct i915_power_well_ops icl_aux_power_well_ops = { 1910 .regs = &icl_aux_power_well_regs, 1911 .sync_hw = hsw_power_well_sync_hw, 1912 .enable = icl_aux_power_well_enable, 1913 .disable = icl_aux_power_well_disable, 1914 .is_enabled = hsw_power_well_enabled, 1915 }; 1916 1917 static const struct i915_power_well_regs icl_ddi_power_well_regs = { 1918 .bios = ICL_PWR_WELL_CTL_DDI1, 1919 .driver = ICL_PWR_WELL_CTL_DDI2, 1920 .debug = ICL_PWR_WELL_CTL_DDI4, 1921 }; 1922 1923 const struct i915_power_well_ops icl_ddi_power_well_ops = { 1924 .regs = &icl_ddi_power_well_regs, 1925 .sync_hw = hsw_power_well_sync_hw, 1926 .enable = hsw_power_well_enable, 1927 .disable = hsw_power_well_disable, 1928 .is_enabled = hsw_power_well_enabled, 1929 }; 1930 1931 const struct i915_power_well_ops tgl_tc_cold_off_ops = { 1932 .sync_hw = tgl_tc_cold_off_power_well_sync_hw, 1933 .enable = tgl_tc_cold_off_power_well_enable, 1934 .disable = tgl_tc_cold_off_power_well_disable, 1935 .is_enabled = tgl_tc_cold_off_power_well_is_enabled, 1936 }; 1937 1938 const struct i915_power_well_ops xelpdp_aux_power_well_ops = { 1939 .sync_hw = i9xx_power_well_sync_hw_noop, 1940 .enable = xelpdp_aux_power_well_enable, 1941 .disable = xelpdp_aux_power_well_disable, 1942 .is_enabled = xelpdp_aux_power_well_enabled, 1943 }; 1944