1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 9 #include "vlv_sideband_reg.h" 10 11 #include "intel_display_power_map.h" 12 #include "intel_display_power_well.h" 13 14 #define __LIST_INLINE_ELEMS(__elem_type, ...) \ 15 ((__elem_type[]) { __VA_ARGS__ }) 16 17 #define __LIST(__elems) { \ 18 .list = __elems, \ 19 .count = ARRAY_SIZE(__elems), \ 20 } 21 22 #define I915_PW_DOMAINS(...) \ 23 (const struct i915_power_domain_list) \ 24 __LIST(__LIST_INLINE_ELEMS(const enum intel_display_power_domain, __VA_ARGS__)) 25 26 #define I915_DECL_PW_DOMAINS(__name, ...) \ 27 static const struct i915_power_domain_list __name = I915_PW_DOMAINS(__VA_ARGS__) 28 29 /* Zero-length list assigns all power domains, a NULL list assigns none. */ 30 #define I915_PW_DOMAINS_NONE NULL 31 #define I915_PW_DOMAINS_ALL /* zero-length list */ 32 33 #define I915_PW_INSTANCES(...) \ 34 (const struct i915_power_well_instance_list) \ 35 __LIST(__LIST_INLINE_ELEMS(const struct i915_power_well_instance, __VA_ARGS__)) 36 37 #define I915_PW(_name, _domain_list, ...) \ 38 { .name = _name, .domain_list = _domain_list, ## __VA_ARGS__ } 39 40 41 struct i915_power_well_desc_list { 42 const struct i915_power_well_desc *list; 43 u8 count; 44 }; 45 46 #define I915_PW_DESCRIPTORS(x) __LIST(x) 47 48 49 I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL); 50 51 static const struct i915_power_well_desc i9xx_power_wells_always_on[] = { 52 { 53 .instances = &I915_PW_INSTANCES( 54 I915_PW("always-on", &i9xx_pwdoms_always_on), 55 ), 56 .ops = &i9xx_always_on_power_well_ops, 57 .always_on = true, 58 }, 59 }; 60 61 static const struct i915_power_well_desc_list i9xx_power_wells[] = { 62 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 63 }; 64 65 I915_DECL_PW_DOMAINS(i830_pwdoms_pipes, 66 POWER_DOMAIN_PIPE_A, 67 POWER_DOMAIN_PIPE_B, 68 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 69 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 70 POWER_DOMAIN_TRANSCODER_A, 71 POWER_DOMAIN_TRANSCODER_B, 72 POWER_DOMAIN_INIT); 73 74 static const struct i915_power_well_desc i830_power_wells_main[] = { 75 { 76 .instances = &I915_PW_INSTANCES( 77 I915_PW("pipes", &i830_pwdoms_pipes), 78 ), 79 .ops = &i830_pipes_power_well_ops, 80 }, 81 }; 82 83 static const struct i915_power_well_desc_list i830_power_wells[] = { 84 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 85 I915_PW_DESCRIPTORS(i830_power_wells_main), 86 }; 87 88 I915_DECL_PW_DOMAINS(hsw_pwdoms_display, 89 POWER_DOMAIN_PIPE_B, 90 POWER_DOMAIN_PIPE_C, 91 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 92 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 93 POWER_DOMAIN_PIPE_PANEL_FITTER_C, 94 POWER_DOMAIN_TRANSCODER_A, 95 POWER_DOMAIN_TRANSCODER_B, 96 POWER_DOMAIN_TRANSCODER_C, 97 POWER_DOMAIN_PORT_DDI_LANES_B, 98 POWER_DOMAIN_PORT_DDI_LANES_C, 99 POWER_DOMAIN_PORT_DDI_LANES_D, 100 POWER_DOMAIN_PORT_CRT, /* DDI E */ 101 POWER_DOMAIN_VGA, 102 POWER_DOMAIN_AUDIO_MMIO, 103 POWER_DOMAIN_AUDIO_PLAYBACK, 104 POWER_DOMAIN_INIT); 105 106 static const struct i915_power_well_desc hsw_power_wells_main[] = { 107 { 108 .instances = &I915_PW_INSTANCES( 109 I915_PW("display", &hsw_pwdoms_display, 110 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, 111 .id = HSW_DISP_PW_GLOBAL), 112 ), 113 .ops = &hsw_power_well_ops, 114 .has_vga = true, 115 }, 116 }; 117 118 static const struct i915_power_well_desc_list hsw_power_wells[] = { 119 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 120 I915_PW_DESCRIPTORS(hsw_power_wells_main), 121 }; 122 123 I915_DECL_PW_DOMAINS(bdw_pwdoms_display, 124 POWER_DOMAIN_PIPE_B, 125 POWER_DOMAIN_PIPE_C, 126 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 127 POWER_DOMAIN_PIPE_PANEL_FITTER_C, 128 POWER_DOMAIN_TRANSCODER_A, 129 POWER_DOMAIN_TRANSCODER_B, 130 POWER_DOMAIN_TRANSCODER_C, 131 POWER_DOMAIN_PORT_DDI_LANES_B, 132 POWER_DOMAIN_PORT_DDI_LANES_C, 133 POWER_DOMAIN_PORT_DDI_LANES_D, 134 POWER_DOMAIN_PORT_CRT, /* DDI E */ 135 POWER_DOMAIN_VGA, 136 POWER_DOMAIN_AUDIO_MMIO, 137 POWER_DOMAIN_AUDIO_PLAYBACK, 138 POWER_DOMAIN_INIT); 139 140 static const struct i915_power_well_desc bdw_power_wells_main[] = { 141 { 142 .instances = &I915_PW_INSTANCES( 143 I915_PW("display", &bdw_pwdoms_display, 144 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, 145 .id = HSW_DISP_PW_GLOBAL), 146 ), 147 .ops = &hsw_power_well_ops, 148 .has_vga = true, 149 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 150 }, 151 }; 152 153 static const struct i915_power_well_desc_list bdw_power_wells[] = { 154 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 155 I915_PW_DESCRIPTORS(bdw_power_wells_main), 156 }; 157 158 I915_DECL_PW_DOMAINS(vlv_pwdoms_display, 159 POWER_DOMAIN_DISPLAY_CORE, 160 POWER_DOMAIN_PIPE_A, 161 POWER_DOMAIN_PIPE_B, 162 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 163 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 164 POWER_DOMAIN_TRANSCODER_A, 165 POWER_DOMAIN_TRANSCODER_B, 166 POWER_DOMAIN_PORT_DDI_LANES_B, 167 POWER_DOMAIN_PORT_DDI_LANES_C, 168 POWER_DOMAIN_PORT_DSI, 169 POWER_DOMAIN_PORT_CRT, 170 POWER_DOMAIN_VGA, 171 POWER_DOMAIN_AUDIO_MMIO, 172 POWER_DOMAIN_AUDIO_PLAYBACK, 173 POWER_DOMAIN_AUX_IO_B, 174 POWER_DOMAIN_AUX_IO_C, 175 POWER_DOMAIN_AUX_B, 176 POWER_DOMAIN_AUX_C, 177 POWER_DOMAIN_GMBUS, 178 POWER_DOMAIN_INIT); 179 180 I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc, 181 POWER_DOMAIN_PORT_DDI_LANES_B, 182 POWER_DOMAIN_PORT_DDI_LANES_C, 183 POWER_DOMAIN_PORT_CRT, 184 POWER_DOMAIN_AUX_IO_B, 185 POWER_DOMAIN_AUX_IO_C, 186 POWER_DOMAIN_AUX_B, 187 POWER_DOMAIN_AUX_C, 188 POWER_DOMAIN_INIT); 189 190 I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes, 191 POWER_DOMAIN_PORT_DDI_LANES_B, 192 POWER_DOMAIN_PORT_DDI_LANES_C, 193 POWER_DOMAIN_AUX_IO_B, 194 POWER_DOMAIN_AUX_IO_C, 195 POWER_DOMAIN_AUX_B, 196 POWER_DOMAIN_AUX_C, 197 POWER_DOMAIN_INIT); 198 199 static const struct i915_power_well_desc vlv_power_wells_main[] = { 200 { 201 .instances = &I915_PW_INSTANCES( 202 I915_PW("display", &vlv_pwdoms_display, 203 .vlv.idx = PUNIT_PWGT_IDX_DISP2D, 204 .id = VLV_DISP_PW_DISP2D), 205 ), 206 .ops = &vlv_display_power_well_ops, 207 }, { 208 .instances = &I915_PW_INSTANCES( 209 I915_PW("dpio-tx-b-01", &vlv_pwdoms_dpio_tx_bc_lanes, 210 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01), 211 I915_PW("dpio-tx-b-23", &vlv_pwdoms_dpio_tx_bc_lanes, 212 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23), 213 I915_PW("dpio-tx-c-01", &vlv_pwdoms_dpio_tx_bc_lanes, 214 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01), 215 I915_PW("dpio-tx-c-23", &vlv_pwdoms_dpio_tx_bc_lanes, 216 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23), 217 ), 218 .ops = &vlv_dpio_power_well_ops, 219 }, { 220 .instances = &I915_PW_INSTANCES( 221 I915_PW("dpio-common", &vlv_pwdoms_dpio_cmn_bc, 222 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, 223 .id = VLV_DISP_PW_DPIO_CMN_BC), 224 ), 225 .ops = &vlv_dpio_cmn_power_well_ops, 226 }, 227 }; 228 229 static const struct i915_power_well_desc_list vlv_power_wells[] = { 230 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 231 I915_PW_DESCRIPTORS(vlv_power_wells_main), 232 }; 233 234 I915_DECL_PW_DOMAINS(chv_pwdoms_display, 235 POWER_DOMAIN_DISPLAY_CORE, 236 POWER_DOMAIN_PIPE_A, 237 POWER_DOMAIN_PIPE_B, 238 POWER_DOMAIN_PIPE_C, 239 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 240 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 241 POWER_DOMAIN_PIPE_PANEL_FITTER_C, 242 POWER_DOMAIN_TRANSCODER_A, 243 POWER_DOMAIN_TRANSCODER_B, 244 POWER_DOMAIN_TRANSCODER_C, 245 POWER_DOMAIN_PORT_DDI_LANES_B, 246 POWER_DOMAIN_PORT_DDI_LANES_C, 247 POWER_DOMAIN_PORT_DDI_LANES_D, 248 POWER_DOMAIN_PORT_DSI, 249 POWER_DOMAIN_VGA, 250 POWER_DOMAIN_AUDIO_MMIO, 251 POWER_DOMAIN_AUDIO_PLAYBACK, 252 POWER_DOMAIN_AUX_IO_B, 253 POWER_DOMAIN_AUX_IO_C, 254 POWER_DOMAIN_AUX_IO_D, 255 POWER_DOMAIN_AUX_B, 256 POWER_DOMAIN_AUX_C, 257 POWER_DOMAIN_AUX_D, 258 POWER_DOMAIN_GMBUS, 259 POWER_DOMAIN_INIT); 260 261 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc, 262 POWER_DOMAIN_PORT_DDI_LANES_B, 263 POWER_DOMAIN_PORT_DDI_LANES_C, 264 POWER_DOMAIN_AUX_IO_B, 265 POWER_DOMAIN_AUX_IO_C, 266 POWER_DOMAIN_AUX_B, 267 POWER_DOMAIN_AUX_C, 268 POWER_DOMAIN_INIT); 269 270 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d, 271 POWER_DOMAIN_PORT_DDI_LANES_D, 272 POWER_DOMAIN_AUX_IO_D, 273 POWER_DOMAIN_AUX_D, 274 POWER_DOMAIN_INIT); 275 276 static const struct i915_power_well_desc chv_power_wells_main[] = { 277 { 278 /* 279 * Pipe A power well is the new disp2d well. Pipe B and C 280 * power wells don't actually exist. Pipe A power well is 281 * required for any pipe to work. 282 */ 283 .instances = &I915_PW_INSTANCES( 284 I915_PW("display", &chv_pwdoms_display), 285 ), 286 .ops = &chv_pipe_power_well_ops, 287 }, { 288 .instances = &I915_PW_INSTANCES( 289 I915_PW("dpio-common-bc", &chv_pwdoms_dpio_cmn_bc, 290 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, 291 .id = VLV_DISP_PW_DPIO_CMN_BC), 292 I915_PW("dpio-common-d", &chv_pwdoms_dpio_cmn_d, 293 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D, 294 .id = CHV_DISP_PW_DPIO_CMN_D), 295 ), 296 .ops = &chv_dpio_cmn_power_well_ops, 297 }, 298 }; 299 300 static const struct i915_power_well_desc_list chv_power_wells[] = { 301 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 302 I915_PW_DESCRIPTORS(chv_power_wells_main), 303 }; 304 305 #define SKL_PW_2_POWER_DOMAINS \ 306 POWER_DOMAIN_PIPE_B, \ 307 POWER_DOMAIN_PIPE_C, \ 308 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 309 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 310 POWER_DOMAIN_TRANSCODER_A, \ 311 POWER_DOMAIN_TRANSCODER_B, \ 312 POWER_DOMAIN_TRANSCODER_C, \ 313 POWER_DOMAIN_PORT_DDI_LANES_B, \ 314 POWER_DOMAIN_PORT_DDI_LANES_C, \ 315 POWER_DOMAIN_PORT_DDI_LANES_D, \ 316 POWER_DOMAIN_PORT_DDI_LANES_E, \ 317 POWER_DOMAIN_VGA, \ 318 POWER_DOMAIN_AUDIO_MMIO, \ 319 POWER_DOMAIN_AUDIO_PLAYBACK, \ 320 POWER_DOMAIN_AUX_IO_B, \ 321 POWER_DOMAIN_AUX_IO_C, \ 322 POWER_DOMAIN_AUX_IO_D, \ 323 POWER_DOMAIN_AUX_B, \ 324 POWER_DOMAIN_AUX_C, \ 325 POWER_DOMAIN_AUX_D 326 327 I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2, 328 SKL_PW_2_POWER_DOMAINS, 329 POWER_DOMAIN_INIT); 330 331 I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off, 332 SKL_PW_2_POWER_DOMAINS, 333 POWER_DOMAIN_AUX_A, 334 POWER_DOMAIN_MODESET, 335 POWER_DOMAIN_GT_IRQ, 336 POWER_DOMAIN_DC_OFF, 337 POWER_DOMAIN_INIT); 338 339 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e, 340 POWER_DOMAIN_PORT_DDI_IO_A, 341 POWER_DOMAIN_PORT_DDI_IO_E, 342 POWER_DOMAIN_INIT); 343 344 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_b, 345 POWER_DOMAIN_PORT_DDI_IO_B, 346 POWER_DOMAIN_INIT); 347 348 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_c, 349 POWER_DOMAIN_PORT_DDI_IO_C, 350 POWER_DOMAIN_INIT); 351 352 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d, 353 POWER_DOMAIN_PORT_DDI_IO_D, 354 POWER_DOMAIN_INIT); 355 356 static const struct i915_power_well_desc skl_power_wells_pw_1[] = { 357 { 358 /* Handled by the DMC firmware */ 359 .instances = &I915_PW_INSTANCES( 360 I915_PW("PW_1", I915_PW_DOMAINS_NONE, 361 .hsw.idx = SKL_PW_CTL_IDX_PW_1, 362 .id = SKL_DISP_PW_1), 363 ), 364 .ops = &hsw_power_well_ops, 365 .always_on = true, 366 .has_fuses = true, 367 }, 368 }; 369 370 static const struct i915_power_well_desc skl_power_wells_main[] = { 371 { 372 /* Handled by the DMC firmware */ 373 .instances = &I915_PW_INSTANCES( 374 I915_PW("MISC_IO", I915_PW_DOMAINS_NONE, 375 .hsw.idx = SKL_PW_CTL_IDX_MISC_IO, 376 .id = SKL_DISP_PW_MISC_IO), 377 ), 378 .ops = &hsw_power_well_ops, 379 .always_on = true, 380 }, { 381 .instances = &I915_PW_INSTANCES( 382 I915_PW("DC_off", &skl_pwdoms_dc_off, 383 .id = SKL_DISP_DC_OFF), 384 ), 385 .ops = &gen9_dc_off_power_well_ops, 386 }, { 387 .instances = &I915_PW_INSTANCES( 388 I915_PW("PW_2", &skl_pwdoms_pw_2, 389 .hsw.idx = SKL_PW_CTL_IDX_PW_2, 390 .id = SKL_DISP_PW_2), 391 ), 392 .ops = &hsw_power_well_ops, 393 .has_vga = true, 394 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 395 .has_fuses = true, 396 }, { 397 .instances = &I915_PW_INSTANCES( 398 I915_PW("DDI_IO_A_E", &skl_pwdoms_ddi_io_a_e, .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E), 399 I915_PW("DDI_IO_B", &skl_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B), 400 I915_PW("DDI_IO_C", &skl_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C), 401 I915_PW("DDI_IO_D", &skl_pwdoms_ddi_io_d, .hsw.idx = SKL_PW_CTL_IDX_DDI_D), 402 ), 403 .ops = &hsw_power_well_ops, 404 }, 405 }; 406 407 static const struct i915_power_well_desc_list skl_power_wells[] = { 408 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 409 I915_PW_DESCRIPTORS(skl_power_wells_pw_1), 410 I915_PW_DESCRIPTORS(skl_power_wells_main), 411 }; 412 413 #define BXT_PW_2_POWER_DOMAINS \ 414 POWER_DOMAIN_PIPE_B, \ 415 POWER_DOMAIN_PIPE_C, \ 416 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 417 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 418 POWER_DOMAIN_TRANSCODER_A, \ 419 POWER_DOMAIN_TRANSCODER_B, \ 420 POWER_DOMAIN_TRANSCODER_C, \ 421 POWER_DOMAIN_PORT_DDI_LANES_B, \ 422 POWER_DOMAIN_PORT_DDI_LANES_C, \ 423 POWER_DOMAIN_VGA, \ 424 POWER_DOMAIN_AUDIO_MMIO, \ 425 POWER_DOMAIN_AUDIO_PLAYBACK, \ 426 POWER_DOMAIN_AUX_IO_B, \ 427 POWER_DOMAIN_AUX_IO_C, \ 428 POWER_DOMAIN_AUX_B, \ 429 POWER_DOMAIN_AUX_C 430 431 I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2, 432 BXT_PW_2_POWER_DOMAINS, 433 POWER_DOMAIN_INIT); 434 435 I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off, 436 BXT_PW_2_POWER_DOMAINS, 437 POWER_DOMAIN_AUX_A, 438 POWER_DOMAIN_GMBUS, 439 POWER_DOMAIN_MODESET, 440 POWER_DOMAIN_GT_IRQ, 441 POWER_DOMAIN_DC_OFF, 442 POWER_DOMAIN_INIT); 443 444 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a, 445 POWER_DOMAIN_PORT_DDI_LANES_A, 446 POWER_DOMAIN_AUX_IO_A, 447 POWER_DOMAIN_AUX_A, 448 POWER_DOMAIN_INIT); 449 450 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc, 451 POWER_DOMAIN_PORT_DDI_LANES_B, 452 POWER_DOMAIN_PORT_DDI_LANES_C, 453 POWER_DOMAIN_AUX_IO_B, 454 POWER_DOMAIN_AUX_IO_C, 455 POWER_DOMAIN_AUX_B, 456 POWER_DOMAIN_AUX_C, 457 POWER_DOMAIN_INIT); 458 459 static const struct i915_power_well_desc bxt_power_wells_main[] = { 460 { 461 .instances = &I915_PW_INSTANCES( 462 I915_PW("DC_off", &bxt_pwdoms_dc_off, 463 .id = SKL_DISP_DC_OFF), 464 ), 465 .ops = &gen9_dc_off_power_well_ops, 466 }, { 467 .instances = &I915_PW_INSTANCES( 468 I915_PW("PW_2", &bxt_pwdoms_pw_2, 469 .hsw.idx = SKL_PW_CTL_IDX_PW_2, 470 .id = SKL_DISP_PW_2), 471 ), 472 .ops = &hsw_power_well_ops, 473 .has_vga = true, 474 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 475 .has_fuses = true, 476 }, { 477 .instances = &I915_PW_INSTANCES( 478 I915_PW("dpio-common-a", &bxt_pwdoms_dpio_cmn_a, 479 .bxt.phy = DPIO_PHY1, 480 .id = BXT_DISP_PW_DPIO_CMN_A), 481 I915_PW("dpio-common-bc", &bxt_pwdoms_dpio_cmn_bc, 482 .bxt.phy = DPIO_PHY0, 483 .id = VLV_DISP_PW_DPIO_CMN_BC), 484 ), 485 .ops = &bxt_dpio_cmn_power_well_ops, 486 }, 487 }; 488 489 static const struct i915_power_well_desc_list bxt_power_wells[] = { 490 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 491 I915_PW_DESCRIPTORS(skl_power_wells_pw_1), 492 I915_PW_DESCRIPTORS(bxt_power_wells_main), 493 }; 494 495 #define GLK_PW_2_POWER_DOMAINS \ 496 POWER_DOMAIN_PIPE_B, \ 497 POWER_DOMAIN_PIPE_C, \ 498 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 499 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 500 POWER_DOMAIN_TRANSCODER_A, \ 501 POWER_DOMAIN_TRANSCODER_B, \ 502 POWER_DOMAIN_TRANSCODER_C, \ 503 POWER_DOMAIN_PORT_DDI_LANES_B, \ 504 POWER_DOMAIN_PORT_DDI_LANES_C, \ 505 POWER_DOMAIN_VGA, \ 506 POWER_DOMAIN_AUDIO_MMIO, \ 507 POWER_DOMAIN_AUDIO_PLAYBACK, \ 508 POWER_DOMAIN_AUX_IO_B, \ 509 POWER_DOMAIN_AUX_IO_C, \ 510 POWER_DOMAIN_AUX_B, \ 511 POWER_DOMAIN_AUX_C 512 513 I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2, 514 GLK_PW_2_POWER_DOMAINS, 515 POWER_DOMAIN_INIT); 516 517 I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off, 518 GLK_PW_2_POWER_DOMAINS, 519 POWER_DOMAIN_AUX_A, 520 POWER_DOMAIN_GMBUS, 521 POWER_DOMAIN_MODESET, 522 POWER_DOMAIN_GT_IRQ, 523 POWER_DOMAIN_DC_OFF, 524 POWER_DOMAIN_INIT); 525 526 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A); 527 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B); 528 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C); 529 530 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a, 531 POWER_DOMAIN_PORT_DDI_LANES_A, 532 POWER_DOMAIN_AUX_IO_A, 533 POWER_DOMAIN_AUX_A, 534 POWER_DOMAIN_INIT); 535 536 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b, 537 POWER_DOMAIN_PORT_DDI_LANES_B, 538 POWER_DOMAIN_AUX_IO_B, 539 POWER_DOMAIN_AUX_B, 540 POWER_DOMAIN_INIT); 541 542 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c, 543 POWER_DOMAIN_PORT_DDI_LANES_C, 544 POWER_DOMAIN_AUX_IO_C, 545 POWER_DOMAIN_AUX_C, 546 POWER_DOMAIN_INIT); 547 548 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a, 549 POWER_DOMAIN_AUX_IO_A, 550 POWER_DOMAIN_AUX_A, 551 POWER_DOMAIN_INIT); 552 553 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b, 554 POWER_DOMAIN_AUX_IO_B, 555 POWER_DOMAIN_AUX_B, 556 POWER_DOMAIN_INIT); 557 558 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c, 559 POWER_DOMAIN_AUX_IO_C, 560 POWER_DOMAIN_AUX_C, 561 POWER_DOMAIN_INIT); 562 563 static const struct i915_power_well_desc glk_power_wells_main[] = { 564 { 565 .instances = &I915_PW_INSTANCES( 566 I915_PW("DC_off", &glk_pwdoms_dc_off, 567 .id = SKL_DISP_DC_OFF), 568 ), 569 .ops = &gen9_dc_off_power_well_ops, 570 }, { 571 .instances = &I915_PW_INSTANCES( 572 I915_PW("PW_2", &glk_pwdoms_pw_2, 573 .hsw.idx = SKL_PW_CTL_IDX_PW_2, 574 .id = SKL_DISP_PW_2), 575 ), 576 .ops = &hsw_power_well_ops, 577 .has_vga = true, 578 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 579 .has_fuses = true, 580 }, { 581 .instances = &I915_PW_INSTANCES( 582 I915_PW("dpio-common-a", &glk_pwdoms_dpio_cmn_a, 583 .bxt.phy = DPIO_PHY1, 584 .id = BXT_DISP_PW_DPIO_CMN_A), 585 I915_PW("dpio-common-b", &glk_pwdoms_dpio_cmn_b, 586 .bxt.phy = DPIO_PHY0, 587 .id = VLV_DISP_PW_DPIO_CMN_BC), 588 I915_PW("dpio-common-c", &glk_pwdoms_dpio_cmn_c, 589 .bxt.phy = DPIO_PHY2, 590 .id = GLK_DISP_PW_DPIO_CMN_C), 591 ), 592 .ops = &bxt_dpio_cmn_power_well_ops, 593 }, { 594 .instances = &I915_PW_INSTANCES( 595 I915_PW("AUX_A", &glk_pwdoms_aux_a, .hsw.idx = GLK_PW_CTL_IDX_AUX_A), 596 I915_PW("AUX_B", &glk_pwdoms_aux_b, .hsw.idx = GLK_PW_CTL_IDX_AUX_B), 597 I915_PW("AUX_C", &glk_pwdoms_aux_c, .hsw.idx = GLK_PW_CTL_IDX_AUX_C), 598 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = GLK_PW_CTL_IDX_DDI_A), 599 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B), 600 I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C), 601 ), 602 .ops = &hsw_power_well_ops, 603 }, 604 }; 605 606 static const struct i915_power_well_desc_list glk_power_wells[] = { 607 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 608 I915_PW_DESCRIPTORS(skl_power_wells_pw_1), 609 I915_PW_DESCRIPTORS(glk_power_wells_main), 610 }; 611 612 /* 613 * ICL PW_0/PG_0 domains (HW/DMC control): 614 * - PCI 615 * - clocks except port PLL 616 * - central power except FBC 617 * - shared functions except pipe interrupts, pipe MBUS, DBUF registers 618 * ICL PW_1/PG_1 domains (HW/DMC control): 619 * - DBUF function 620 * - PIPE_A and its planes, except VGA 621 * - transcoder EDP + PSR 622 * - transcoder DSI 623 * - DDI_A 624 * - FBC 625 */ 626 #define ICL_PW_4_POWER_DOMAINS \ 627 POWER_DOMAIN_PIPE_C, \ 628 POWER_DOMAIN_PIPE_PANEL_FITTER_C 629 630 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4, 631 ICL_PW_4_POWER_DOMAINS, 632 POWER_DOMAIN_INIT); 633 /* VDSC/joining */ 634 635 #define ICL_PW_3_POWER_DOMAINS \ 636 ICL_PW_4_POWER_DOMAINS, \ 637 POWER_DOMAIN_PIPE_B, \ 638 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 639 POWER_DOMAIN_TRANSCODER_A, \ 640 POWER_DOMAIN_TRANSCODER_B, \ 641 POWER_DOMAIN_TRANSCODER_C, \ 642 POWER_DOMAIN_PORT_DDI_LANES_B, \ 643 POWER_DOMAIN_PORT_DDI_LANES_C, \ 644 POWER_DOMAIN_PORT_DDI_LANES_D, \ 645 POWER_DOMAIN_PORT_DDI_LANES_E, \ 646 POWER_DOMAIN_PORT_DDI_LANES_F, \ 647 POWER_DOMAIN_VGA, \ 648 POWER_DOMAIN_AUDIO_MMIO, \ 649 POWER_DOMAIN_AUDIO_PLAYBACK, \ 650 POWER_DOMAIN_AUX_IO_B, \ 651 POWER_DOMAIN_AUX_IO_C, \ 652 POWER_DOMAIN_AUX_IO_D, \ 653 POWER_DOMAIN_AUX_IO_E, \ 654 POWER_DOMAIN_AUX_IO_F, \ 655 POWER_DOMAIN_AUX_B, \ 656 POWER_DOMAIN_AUX_C, \ 657 POWER_DOMAIN_AUX_D, \ 658 POWER_DOMAIN_AUX_E, \ 659 POWER_DOMAIN_AUX_F, \ 660 POWER_DOMAIN_AUX_TBT1, \ 661 POWER_DOMAIN_AUX_TBT2, \ 662 POWER_DOMAIN_AUX_TBT3, \ 663 POWER_DOMAIN_AUX_TBT4 664 665 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3, 666 ICL_PW_3_POWER_DOMAINS, 667 POWER_DOMAIN_INIT); 668 /* 669 * - transcoder WD 670 * - KVMR (HW control) 671 */ 672 673 #define ICL_PW_2_POWER_DOMAINS \ 674 ICL_PW_3_POWER_DOMAINS, \ 675 POWER_DOMAIN_TRANSCODER_VDSC_PW2 676 677 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2, 678 ICL_PW_2_POWER_DOMAINS, 679 POWER_DOMAIN_INIT); 680 /* 681 * - KVMR (HW control) 682 */ 683 684 I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off, 685 ICL_PW_2_POWER_DOMAINS, 686 POWER_DOMAIN_AUX_A, 687 POWER_DOMAIN_MODESET, 688 POWER_DOMAIN_DC_OFF, 689 POWER_DOMAIN_INIT); 690 691 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d, POWER_DOMAIN_PORT_DDI_IO_D); 692 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e, POWER_DOMAIN_PORT_DDI_IO_E); 693 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f, POWER_DOMAIN_PORT_DDI_IO_F); 694 695 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a, 696 POWER_DOMAIN_AUX_IO_A, 697 POWER_DOMAIN_AUX_A); 698 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b, 699 POWER_DOMAIN_AUX_IO_B, 700 POWER_DOMAIN_AUX_B); 701 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c, 702 POWER_DOMAIN_AUX_IO_C, 703 POWER_DOMAIN_AUX_C); 704 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, 705 POWER_DOMAIN_AUX_IO_D, 706 POWER_DOMAIN_AUX_D); 707 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, 708 POWER_DOMAIN_AUX_IO_E, 709 POWER_DOMAIN_AUX_E); 710 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, 711 POWER_DOMAIN_AUX_IO_F, 712 POWER_DOMAIN_AUX_F); 713 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1); 714 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2); 715 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3); 716 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4); 717 718 static const struct i915_power_well_desc icl_power_wells_pw_1[] = { 719 { 720 /* Handled by the DMC firmware */ 721 .instances = &I915_PW_INSTANCES( 722 I915_PW("PW_1", I915_PW_DOMAINS_NONE, 723 .hsw.idx = ICL_PW_CTL_IDX_PW_1, 724 .id = SKL_DISP_PW_1), 725 ), 726 .ops = &hsw_power_well_ops, 727 .always_on = true, 728 .has_fuses = true, 729 }, 730 }; 731 732 static const struct i915_power_well_desc icl_power_wells_main[] = { 733 { 734 .instances = &I915_PW_INSTANCES( 735 I915_PW("DC_off", &icl_pwdoms_dc_off, 736 .id = SKL_DISP_DC_OFF), 737 ), 738 .ops = &gen9_dc_off_power_well_ops, 739 }, { 740 .instances = &I915_PW_INSTANCES( 741 I915_PW("PW_2", &icl_pwdoms_pw_2, 742 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 743 .id = SKL_DISP_PW_2), 744 ), 745 .ops = &hsw_power_well_ops, 746 .has_fuses = true, 747 }, { 748 .instances = &I915_PW_INSTANCES( 749 I915_PW("PW_3", &icl_pwdoms_pw_3, 750 .hsw.idx = ICL_PW_CTL_IDX_PW_3, 751 .id = ICL_DISP_PW_3), 752 ), 753 .ops = &hsw_power_well_ops, 754 .has_vga = true, 755 .irq_pipe_mask = BIT(PIPE_B), 756 .has_fuses = true, 757 }, { 758 .instances = &I915_PW_INSTANCES( 759 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), 760 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), 761 I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C), 762 I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = ICL_PW_CTL_IDX_DDI_D), 763 I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = ICL_PW_CTL_IDX_DDI_E), 764 I915_PW("DDI_IO_F", &icl_pwdoms_ddi_io_f, .hsw.idx = ICL_PW_CTL_IDX_DDI_F), 765 ), 766 .ops = &icl_ddi_power_well_ops, 767 }, { 768 .instances = &I915_PW_INSTANCES( 769 I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), 770 I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), 771 I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C), 772 I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = ICL_PW_CTL_IDX_AUX_D), 773 I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = ICL_PW_CTL_IDX_AUX_E), 774 I915_PW("AUX_F", &icl_pwdoms_aux_f, .hsw.idx = ICL_PW_CTL_IDX_AUX_F), 775 ), 776 .ops = &icl_aux_power_well_ops, 777 }, { 778 .instances = &I915_PW_INSTANCES( 779 I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1), 780 I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2), 781 I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3), 782 I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4), 783 ), 784 .ops = &icl_aux_power_well_ops, 785 .is_tc_tbt = true, 786 }, { 787 .instances = &I915_PW_INSTANCES( 788 I915_PW("PW_4", &icl_pwdoms_pw_4, 789 .hsw.idx = ICL_PW_CTL_IDX_PW_4), 790 ), 791 .ops = &hsw_power_well_ops, 792 .irq_pipe_mask = BIT(PIPE_C), 793 .has_fuses = true, 794 }, 795 }; 796 797 static const struct i915_power_well_desc_list icl_power_wells[] = { 798 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 799 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 800 I915_PW_DESCRIPTORS(icl_power_wells_main), 801 }; 802 803 #define TGL_PW_5_POWER_DOMAINS \ 804 POWER_DOMAIN_PIPE_D, \ 805 POWER_DOMAIN_PIPE_PANEL_FITTER_D, \ 806 POWER_DOMAIN_TRANSCODER_D 807 808 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_5, 809 TGL_PW_5_POWER_DOMAINS, 810 POWER_DOMAIN_INIT); 811 812 #define TGL_PW_4_POWER_DOMAINS \ 813 TGL_PW_5_POWER_DOMAINS, \ 814 POWER_DOMAIN_PIPE_C, \ 815 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 816 POWER_DOMAIN_TRANSCODER_C 817 818 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_4, 819 TGL_PW_4_POWER_DOMAINS, 820 POWER_DOMAIN_INIT); 821 822 #define TGL_PW_3_POWER_DOMAINS \ 823 TGL_PW_4_POWER_DOMAINS, \ 824 POWER_DOMAIN_PIPE_B, \ 825 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 826 POWER_DOMAIN_TRANSCODER_B, \ 827 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 828 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 829 POWER_DOMAIN_PORT_DDI_LANES_TC3, \ 830 POWER_DOMAIN_PORT_DDI_LANES_TC4, \ 831 POWER_DOMAIN_PORT_DDI_LANES_TC5, \ 832 POWER_DOMAIN_PORT_DDI_LANES_TC6, \ 833 POWER_DOMAIN_VGA, \ 834 POWER_DOMAIN_AUDIO_MMIO, \ 835 POWER_DOMAIN_AUDIO_PLAYBACK, \ 836 POWER_DOMAIN_AUX_USBC1, \ 837 POWER_DOMAIN_AUX_USBC2, \ 838 POWER_DOMAIN_AUX_USBC3, \ 839 POWER_DOMAIN_AUX_USBC4, \ 840 POWER_DOMAIN_AUX_USBC5, \ 841 POWER_DOMAIN_AUX_USBC6, \ 842 POWER_DOMAIN_AUX_TBT1, \ 843 POWER_DOMAIN_AUX_TBT2, \ 844 POWER_DOMAIN_AUX_TBT3, \ 845 POWER_DOMAIN_AUX_TBT4, \ 846 POWER_DOMAIN_AUX_TBT5, \ 847 POWER_DOMAIN_AUX_TBT6 848 849 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_3, 850 TGL_PW_3_POWER_DOMAINS, 851 POWER_DOMAIN_INIT); 852 853 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2, 854 TGL_PW_3_POWER_DOMAINS, 855 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 856 POWER_DOMAIN_INIT); 857 858 I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off, 859 TGL_PW_3_POWER_DOMAINS, 860 POWER_DOMAIN_AUX_A, 861 POWER_DOMAIN_AUX_B, 862 POWER_DOMAIN_AUX_C, 863 POWER_DOMAIN_MODESET, 864 POWER_DOMAIN_DC_OFF, 865 POWER_DOMAIN_INIT); 866 867 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1); 868 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2); 869 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3); 870 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4); 871 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5, POWER_DOMAIN_PORT_DDI_IO_TC5); 872 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6, POWER_DOMAIN_PORT_DDI_IO_TC6); 873 874 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1); 875 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2); 876 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3); 877 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4); 878 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5, POWER_DOMAIN_AUX_USBC5); 879 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6, POWER_DOMAIN_AUX_USBC6); 880 881 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5, POWER_DOMAIN_AUX_TBT5); 882 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6, POWER_DOMAIN_AUX_TBT6); 883 884 I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off, 885 POWER_DOMAIN_AUX_USBC1, 886 POWER_DOMAIN_AUX_USBC2, 887 POWER_DOMAIN_AUX_USBC3, 888 POWER_DOMAIN_AUX_USBC4, 889 POWER_DOMAIN_AUX_USBC5, 890 POWER_DOMAIN_AUX_USBC6, 891 POWER_DOMAIN_AUX_TBT1, 892 POWER_DOMAIN_AUX_TBT2, 893 POWER_DOMAIN_AUX_TBT3, 894 POWER_DOMAIN_AUX_TBT4, 895 POWER_DOMAIN_AUX_TBT5, 896 POWER_DOMAIN_AUX_TBT6, 897 POWER_DOMAIN_TC_COLD_OFF); 898 899 static const struct i915_power_well_desc tgl_power_wells_main[] = { 900 { 901 .instances = &I915_PW_INSTANCES( 902 I915_PW("DC_off", &tgl_pwdoms_dc_off, 903 .id = SKL_DISP_DC_OFF), 904 ), 905 .ops = &gen9_dc_off_power_well_ops, 906 }, { 907 .instances = &I915_PW_INSTANCES( 908 I915_PW("PW_2", &tgl_pwdoms_pw_2, 909 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 910 .id = SKL_DISP_PW_2), 911 ), 912 .ops = &hsw_power_well_ops, 913 .has_fuses = true, 914 }, { 915 .instances = &I915_PW_INSTANCES( 916 I915_PW("PW_3", &tgl_pwdoms_pw_3, 917 .hsw.idx = ICL_PW_CTL_IDX_PW_3, 918 .id = ICL_DISP_PW_3), 919 ), 920 .ops = &hsw_power_well_ops, 921 .has_vga = true, 922 .irq_pipe_mask = BIT(PIPE_B), 923 .has_fuses = true, 924 }, { 925 .instances = &I915_PW_INSTANCES( 926 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), 927 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), 928 I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C), 929 I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1), 930 I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2), 931 I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3), 932 I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4), 933 I915_PW("DDI_IO_TC5", &tgl_pwdoms_ddi_io_tc5, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5), 934 I915_PW("DDI_IO_TC6", &tgl_pwdoms_ddi_io_tc6, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6), 935 ), 936 .ops = &icl_ddi_power_well_ops, 937 }, { 938 .instances = &I915_PW_INSTANCES( 939 I915_PW("PW_4", &tgl_pwdoms_pw_4, 940 .hsw.idx = ICL_PW_CTL_IDX_PW_4), 941 ), 942 .ops = &hsw_power_well_ops, 943 .has_fuses = true, 944 .irq_pipe_mask = BIT(PIPE_C), 945 }, { 946 .instances = &I915_PW_INSTANCES( 947 I915_PW("PW_5", &tgl_pwdoms_pw_5, 948 .hsw.idx = TGL_PW_CTL_IDX_PW_5), 949 ), 950 .ops = &hsw_power_well_ops, 951 .has_fuses = true, 952 .irq_pipe_mask = BIT(PIPE_D), 953 }, 954 }; 955 956 static const struct i915_power_well_desc tgl_power_wells_tc_cold_off[] = { 957 { 958 .instances = &I915_PW_INSTANCES( 959 I915_PW("TC_cold_off", &tgl_pwdoms_tc_cold_off, 960 .id = TGL_DISP_PW_TC_COLD_OFF), 961 ), 962 .ops = &tgl_tc_cold_off_ops, 963 }, 964 }; 965 966 static const struct i915_power_well_desc tgl_power_wells_aux[] = { 967 { 968 .instances = &I915_PW_INSTANCES( 969 I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), 970 I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), 971 I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C), 972 I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1), 973 I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2), 974 I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3), 975 I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4), 976 I915_PW("AUX_USBC5", &tgl_pwdoms_aux_usbc5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5), 977 I915_PW("AUX_USBC6", &tgl_pwdoms_aux_usbc6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6), 978 ), 979 .ops = &icl_aux_power_well_ops, 980 }, { 981 .instances = &I915_PW_INSTANCES( 982 I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1), 983 I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2), 984 I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3), 985 I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4), 986 I915_PW("AUX_TBT5", &tgl_pwdoms_aux_tbt5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5), 987 I915_PW("AUX_TBT6", &tgl_pwdoms_aux_tbt6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6), 988 ), 989 .ops = &icl_aux_power_well_ops, 990 .is_tc_tbt = true, 991 }, 992 }; 993 994 static const struct i915_power_well_desc_list tgl_power_wells[] = { 995 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 996 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 997 I915_PW_DESCRIPTORS(tgl_power_wells_main), 998 I915_PW_DESCRIPTORS(tgl_power_wells_tc_cold_off), 999 I915_PW_DESCRIPTORS(tgl_power_wells_aux), 1000 }; 1001 1002 static const struct i915_power_well_desc_list adls_power_wells[] = { 1003 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1004 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1005 I915_PW_DESCRIPTORS(tgl_power_wells_main), 1006 I915_PW_DESCRIPTORS(tgl_power_wells_aux), 1007 }; 1008 1009 #define RKL_PW_4_POWER_DOMAINS \ 1010 POWER_DOMAIN_PIPE_C, \ 1011 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 1012 POWER_DOMAIN_TRANSCODER_C 1013 1014 I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_4, 1015 RKL_PW_4_POWER_DOMAINS, 1016 POWER_DOMAIN_INIT); 1017 1018 #define RKL_PW_3_POWER_DOMAINS \ 1019 RKL_PW_4_POWER_DOMAINS, \ 1020 POWER_DOMAIN_PIPE_B, \ 1021 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 1022 POWER_DOMAIN_TRANSCODER_B, \ 1023 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 1024 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 1025 POWER_DOMAIN_VGA, \ 1026 POWER_DOMAIN_AUDIO_MMIO, \ 1027 POWER_DOMAIN_AUDIO_PLAYBACK, \ 1028 POWER_DOMAIN_AUX_USBC1, \ 1029 POWER_DOMAIN_AUX_USBC2 1030 1031 I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3, 1032 RKL_PW_3_POWER_DOMAINS, 1033 POWER_DOMAIN_INIT); 1034 1035 /* 1036 * There is no PW_2/PG_2 on RKL. 1037 * 1038 * RKL PW_1/PG_1 domains (under HW/DMC control): 1039 * - DBUF function (note: registers are in PW0) 1040 * - PIPE_A and its planes and VDSC/joining, except VGA 1041 * - transcoder A 1042 * - DDI_A and DDI_B 1043 * - FBC 1044 * 1045 * RKL PW_0/PG_0 domains (under HW/DMC control): 1046 * - PCI 1047 * - clocks except port PLL 1048 * - shared functions: 1049 * * interrupts except pipe interrupts 1050 * * MBus except PIPE_MBUS_DBOX_CTL 1051 * * DBUF registers 1052 * - central power except FBC 1053 * - top-level GTC (DDI-level GTC is in the well associated with the DDI) 1054 */ 1055 1056 I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off, 1057 RKL_PW_3_POWER_DOMAINS, 1058 POWER_DOMAIN_AUX_A, 1059 POWER_DOMAIN_AUX_B, 1060 POWER_DOMAIN_MODESET, 1061 POWER_DOMAIN_DC_OFF, 1062 POWER_DOMAIN_INIT); 1063 1064 static const struct i915_power_well_desc rkl_power_wells_main[] = { 1065 { 1066 .instances = &I915_PW_INSTANCES( 1067 I915_PW("DC_off", &rkl_pwdoms_dc_off, 1068 .id = SKL_DISP_DC_OFF), 1069 ), 1070 .ops = &gen9_dc_off_power_well_ops, 1071 }, { 1072 .instances = &I915_PW_INSTANCES( 1073 I915_PW("PW_3", &rkl_pwdoms_pw_3, 1074 .hsw.idx = ICL_PW_CTL_IDX_PW_3, 1075 .id = ICL_DISP_PW_3), 1076 ), 1077 .ops = &hsw_power_well_ops, 1078 .irq_pipe_mask = BIT(PIPE_B), 1079 .has_vga = true, 1080 .has_fuses = true, 1081 }, { 1082 .instances = &I915_PW_INSTANCES( 1083 I915_PW("PW_4", &rkl_pwdoms_pw_4, 1084 .hsw.idx = ICL_PW_CTL_IDX_PW_4), 1085 ), 1086 .ops = &hsw_power_well_ops, 1087 .has_fuses = true, 1088 .irq_pipe_mask = BIT(PIPE_C), 1089 }, 1090 }; 1091 1092 static const struct i915_power_well_desc rkl_power_wells_ddi_aux[] = { 1093 { 1094 .instances = &I915_PW_INSTANCES( 1095 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), 1096 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), 1097 I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1), 1098 I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2), 1099 ), 1100 .ops = &icl_ddi_power_well_ops, 1101 }, { 1102 .instances = &I915_PW_INSTANCES( 1103 I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), 1104 I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), 1105 I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1), 1106 I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2), 1107 ), 1108 .ops = &icl_aux_power_well_ops, 1109 }, 1110 }; 1111 1112 static const struct i915_power_well_desc_list rkl_power_wells[] = { 1113 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1114 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1115 I915_PW_DESCRIPTORS(rkl_power_wells_main), 1116 I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux), 1117 }; 1118 1119 /* 1120 * DG1 onwards Audio MMIO/VERBS lies in PG0 power well. 1121 */ 1122 #define DG1_PW_3_POWER_DOMAINS \ 1123 TGL_PW_4_POWER_DOMAINS, \ 1124 POWER_DOMAIN_PIPE_B, \ 1125 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 1126 POWER_DOMAIN_TRANSCODER_B, \ 1127 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 1128 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 1129 POWER_DOMAIN_VGA, \ 1130 POWER_DOMAIN_AUDIO_PLAYBACK, \ 1131 POWER_DOMAIN_AUX_USBC1, \ 1132 POWER_DOMAIN_AUX_USBC2 1133 1134 I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3, 1135 DG1_PW_3_POWER_DOMAINS, 1136 POWER_DOMAIN_INIT); 1137 1138 I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off, 1139 DG1_PW_3_POWER_DOMAINS, 1140 POWER_DOMAIN_AUDIO_MMIO, 1141 POWER_DOMAIN_AUX_A, 1142 POWER_DOMAIN_AUX_B, 1143 POWER_DOMAIN_MODESET, 1144 POWER_DOMAIN_DC_OFF, 1145 POWER_DOMAIN_INIT); 1146 1147 I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2, 1148 DG1_PW_3_POWER_DOMAINS, 1149 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 1150 POWER_DOMAIN_INIT); 1151 1152 static const struct i915_power_well_desc dg1_power_wells_main[] = { 1153 { 1154 .instances = &I915_PW_INSTANCES( 1155 I915_PW("DC_off", &dg1_pwdoms_dc_off, 1156 .id = SKL_DISP_DC_OFF), 1157 ), 1158 .ops = &gen9_dc_off_power_well_ops, 1159 }, { 1160 .instances = &I915_PW_INSTANCES( 1161 I915_PW("PW_2", &dg1_pwdoms_pw_2, 1162 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 1163 .id = SKL_DISP_PW_2), 1164 ), 1165 .ops = &hsw_power_well_ops, 1166 .has_fuses = true, 1167 }, { 1168 .instances = &I915_PW_INSTANCES( 1169 I915_PW("PW_3", &dg1_pwdoms_pw_3, 1170 .hsw.idx = ICL_PW_CTL_IDX_PW_3, 1171 .id = ICL_DISP_PW_3), 1172 ), 1173 .ops = &hsw_power_well_ops, 1174 .irq_pipe_mask = BIT(PIPE_B), 1175 .has_vga = true, 1176 .has_fuses = true, 1177 }, { 1178 .instances = &I915_PW_INSTANCES( 1179 I915_PW("PW_4", &tgl_pwdoms_pw_4, 1180 .hsw.idx = ICL_PW_CTL_IDX_PW_4), 1181 ), 1182 .ops = &hsw_power_well_ops, 1183 .has_fuses = true, 1184 .irq_pipe_mask = BIT(PIPE_C), 1185 }, { 1186 .instances = &I915_PW_INSTANCES( 1187 I915_PW("PW_5", &tgl_pwdoms_pw_5, 1188 .hsw.idx = TGL_PW_CTL_IDX_PW_5), 1189 ), 1190 .ops = &hsw_power_well_ops, 1191 .has_fuses = true, 1192 .irq_pipe_mask = BIT(PIPE_D), 1193 }, 1194 }; 1195 1196 static const struct i915_power_well_desc_list dg1_power_wells[] = { 1197 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1198 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1199 I915_PW_DESCRIPTORS(dg1_power_wells_main), 1200 I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux), 1201 }; 1202 1203 /* 1204 * XE_LPD Power Domains 1205 * 1206 * Previous platforms required that PG(n-1) be enabled before PG(n). That 1207 * dependency chain turns into a dependency tree on XE_LPD: 1208 * 1209 * PG0 1210 * | 1211 * --PG1-- 1212 * / \ 1213 * PGA --PG2-- 1214 * / | \ 1215 * PGB PGC PGD 1216 * 1217 * Power wells must be enabled from top to bottom and disabled from bottom 1218 * to top. This allows pipes to be power gated independently. 1219 */ 1220 1221 #define XELPD_PW_D_POWER_DOMAINS \ 1222 POWER_DOMAIN_PIPE_D, \ 1223 POWER_DOMAIN_PIPE_PANEL_FITTER_D, \ 1224 POWER_DOMAIN_TRANSCODER_D 1225 1226 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_d, 1227 XELPD_PW_D_POWER_DOMAINS, 1228 POWER_DOMAIN_INIT); 1229 1230 #define XELPD_PW_C_POWER_DOMAINS \ 1231 POWER_DOMAIN_PIPE_C, \ 1232 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 1233 POWER_DOMAIN_TRANSCODER_C 1234 1235 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_c, 1236 XELPD_PW_C_POWER_DOMAINS, 1237 POWER_DOMAIN_INIT); 1238 1239 #define XELPD_PW_B_POWER_DOMAINS \ 1240 POWER_DOMAIN_PIPE_B, \ 1241 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 1242 POWER_DOMAIN_TRANSCODER_B 1243 1244 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_b, 1245 XELPD_PW_B_POWER_DOMAINS, 1246 POWER_DOMAIN_INIT); 1247 1248 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a, 1249 POWER_DOMAIN_PIPE_A, 1250 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 1251 POWER_DOMAIN_INIT); 1252 1253 #define XELPD_PW_2_POWER_DOMAINS \ 1254 XELPD_PW_B_POWER_DOMAINS, \ 1255 XELPD_PW_C_POWER_DOMAINS, \ 1256 XELPD_PW_D_POWER_DOMAINS, \ 1257 POWER_DOMAIN_PORT_DDI_LANES_C, \ 1258 POWER_DOMAIN_PORT_DDI_LANES_D, \ 1259 POWER_DOMAIN_PORT_DDI_LANES_E, \ 1260 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 1261 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 1262 POWER_DOMAIN_PORT_DDI_LANES_TC3, \ 1263 POWER_DOMAIN_PORT_DDI_LANES_TC4, \ 1264 POWER_DOMAIN_VGA, \ 1265 POWER_DOMAIN_AUDIO_PLAYBACK, \ 1266 POWER_DOMAIN_AUX_IO_C, \ 1267 POWER_DOMAIN_AUX_IO_D, \ 1268 POWER_DOMAIN_AUX_IO_E, \ 1269 POWER_DOMAIN_AUX_C, \ 1270 POWER_DOMAIN_AUX_D, \ 1271 POWER_DOMAIN_AUX_E, \ 1272 POWER_DOMAIN_AUX_USBC1, \ 1273 POWER_DOMAIN_AUX_USBC2, \ 1274 POWER_DOMAIN_AUX_USBC3, \ 1275 POWER_DOMAIN_AUX_USBC4, \ 1276 POWER_DOMAIN_AUX_TBT1, \ 1277 POWER_DOMAIN_AUX_TBT2, \ 1278 POWER_DOMAIN_AUX_TBT3, \ 1279 POWER_DOMAIN_AUX_TBT4 1280 1281 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2, 1282 XELPD_PW_2_POWER_DOMAINS, 1283 POWER_DOMAIN_INIT); 1284 1285 /* 1286 * XELPD PW_1/PG_1 domains (under HW/DMC control): 1287 * - DBUF function (registers are in PW0) 1288 * - Transcoder A 1289 * - DDI_A and DDI_B 1290 * 1291 * XELPD PW_0/PW_1 domains (under HW/DMC control): 1292 * - PCI 1293 * - Clocks except port PLL 1294 * - Shared functions: 1295 * * interrupts except pipe interrupts 1296 * * MBus except PIPE_MBUS_DBOX_CTL 1297 * * DBUF registers 1298 * - Central power except FBC 1299 * - Top-level GTC (DDI-level GTC is in the well associated with the DDI) 1300 */ 1301 1302 I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off, 1303 XELPD_PW_2_POWER_DOMAINS, 1304 POWER_DOMAIN_PORT_DSI, 1305 POWER_DOMAIN_AUDIO_MMIO, 1306 POWER_DOMAIN_AUX_A, 1307 POWER_DOMAIN_AUX_B, 1308 POWER_DOMAIN_MODESET, 1309 POWER_DOMAIN_DC_OFF, 1310 POWER_DOMAIN_INIT); 1311 1312 static const struct i915_power_well_desc xelpd_power_wells_main[] = { 1313 { 1314 .instances = &I915_PW_INSTANCES( 1315 I915_PW("DC_off", &xelpd_pwdoms_dc_off, 1316 .id = SKL_DISP_DC_OFF), 1317 ), 1318 .ops = &gen9_dc_off_power_well_ops, 1319 }, { 1320 .instances = &I915_PW_INSTANCES( 1321 I915_PW("PW_2", &xelpd_pwdoms_pw_2, 1322 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 1323 .id = SKL_DISP_PW_2), 1324 ), 1325 .ops = &hsw_power_well_ops, 1326 .has_vga = true, 1327 .has_fuses = true, 1328 }, { 1329 .instances = &I915_PW_INSTANCES( 1330 I915_PW("PW_A", &xelpd_pwdoms_pw_a, 1331 .hsw.idx = XELPD_PW_CTL_IDX_PW_A), 1332 ), 1333 .ops = &hsw_power_well_ops, 1334 .irq_pipe_mask = BIT(PIPE_A), 1335 .has_fuses = true, 1336 }, { 1337 .instances = &I915_PW_INSTANCES( 1338 I915_PW("PW_B", &xelpd_pwdoms_pw_b, 1339 .hsw.idx = XELPD_PW_CTL_IDX_PW_B), 1340 ), 1341 .ops = &hsw_power_well_ops, 1342 .irq_pipe_mask = BIT(PIPE_B), 1343 .has_fuses = true, 1344 }, { 1345 .instances = &I915_PW_INSTANCES( 1346 I915_PW("PW_C", &xelpd_pwdoms_pw_c, 1347 .hsw.idx = XELPD_PW_CTL_IDX_PW_C), 1348 ), 1349 .ops = &hsw_power_well_ops, 1350 .irq_pipe_mask = BIT(PIPE_C), 1351 .has_fuses = true, 1352 }, { 1353 .instances = &I915_PW_INSTANCES( 1354 I915_PW("PW_D", &xelpd_pwdoms_pw_d, 1355 .hsw.idx = XELPD_PW_CTL_IDX_PW_D), 1356 ), 1357 .ops = &hsw_power_well_ops, 1358 .irq_pipe_mask = BIT(PIPE_D), 1359 .has_fuses = true, 1360 }, { 1361 .instances = &I915_PW_INSTANCES( 1362 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), 1363 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), 1364 I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C), 1365 I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D), 1366 I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E), 1367 I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1), 1368 I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2), 1369 I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3), 1370 I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4), 1371 ), 1372 .ops = &icl_ddi_power_well_ops, 1373 }, { 1374 .instances = &I915_PW_INSTANCES( 1375 I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), 1376 I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), 1377 I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C), 1378 I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D), 1379 I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E), 1380 I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1), 1381 I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2), 1382 I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3), 1383 I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4), 1384 ), 1385 .ops = &icl_aux_power_well_ops, 1386 .fixed_enable_delay = true, 1387 }, { 1388 .instances = &I915_PW_INSTANCES( 1389 I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1), 1390 I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2), 1391 I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3), 1392 I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4), 1393 ), 1394 .ops = &icl_aux_power_well_ops, 1395 .is_tc_tbt = true, 1396 }, 1397 }; 1398 1399 static const struct i915_power_well_desc_list xelpd_power_wells[] = { 1400 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1401 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1402 I915_PW_DESCRIPTORS(xelpd_power_wells_main), 1403 }; 1404 1405 /* 1406 * MTL is based on XELPD power domains with the exception of power gating for: 1407 * - DDI_IO (moved to PLL logic) 1408 * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA always-on) 1409 */ 1410 #define XELPDP_PW_2_POWER_DOMAINS \ 1411 XELPD_PW_B_POWER_DOMAINS, \ 1412 XELPD_PW_C_POWER_DOMAINS, \ 1413 XELPD_PW_D_POWER_DOMAINS, \ 1414 POWER_DOMAIN_AUDIO_PLAYBACK, \ 1415 POWER_DOMAIN_VGA, \ 1416 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 1417 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 1418 POWER_DOMAIN_PORT_DDI_LANES_TC3, \ 1419 POWER_DOMAIN_PORT_DDI_LANES_TC4 1420 1421 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2, 1422 XELPDP_PW_2_POWER_DOMAINS, 1423 POWER_DOMAIN_INIT); 1424 1425 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off, 1426 XELPDP_PW_2_POWER_DOMAINS, 1427 POWER_DOMAIN_AUDIO_MMIO, 1428 POWER_DOMAIN_MODESET, 1429 POWER_DOMAIN_AUX_A, 1430 POWER_DOMAIN_AUX_B, 1431 POWER_DOMAIN_DC_OFF, 1432 POWER_DOMAIN_INIT); 1433 1434 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1, 1435 POWER_DOMAIN_AUX_USBC1, 1436 POWER_DOMAIN_AUX_TBT1); 1437 1438 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2, 1439 POWER_DOMAIN_AUX_USBC2, 1440 POWER_DOMAIN_AUX_TBT2); 1441 1442 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3, 1443 POWER_DOMAIN_AUX_USBC3, 1444 POWER_DOMAIN_AUX_TBT3); 1445 1446 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4, 1447 POWER_DOMAIN_AUX_USBC4, 1448 POWER_DOMAIN_AUX_TBT4); 1449 1450 static const struct i915_power_well_desc xelpdp_power_wells_main[] = { 1451 { 1452 .instances = &I915_PW_INSTANCES( 1453 I915_PW("DC_off", &xelpdp_pwdoms_dc_off, 1454 .id = SKL_DISP_DC_OFF), 1455 ), 1456 .ops = &gen9_dc_off_power_well_ops, 1457 }, { 1458 .instances = &I915_PW_INSTANCES( 1459 I915_PW("PW_2", &xelpdp_pwdoms_pw_2, 1460 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 1461 .id = SKL_DISP_PW_2), 1462 ), 1463 .ops = &hsw_power_well_ops, 1464 .has_vga = true, 1465 .has_fuses = true, 1466 }, { 1467 .instances = &I915_PW_INSTANCES( 1468 I915_PW("PW_A", &xelpd_pwdoms_pw_a, 1469 .hsw.idx = XELPD_PW_CTL_IDX_PW_A), 1470 ), 1471 .ops = &hsw_power_well_ops, 1472 .irq_pipe_mask = BIT(PIPE_A), 1473 .has_fuses = true, 1474 }, { 1475 .instances = &I915_PW_INSTANCES( 1476 I915_PW("PW_B", &xelpd_pwdoms_pw_b, 1477 .hsw.idx = XELPD_PW_CTL_IDX_PW_B), 1478 ), 1479 .ops = &hsw_power_well_ops, 1480 .irq_pipe_mask = BIT(PIPE_B), 1481 .has_fuses = true, 1482 }, { 1483 .instances = &I915_PW_INSTANCES( 1484 I915_PW("PW_C", &xelpd_pwdoms_pw_c, 1485 .hsw.idx = XELPD_PW_CTL_IDX_PW_C), 1486 ), 1487 .ops = &hsw_power_well_ops, 1488 .irq_pipe_mask = BIT(PIPE_C), 1489 .has_fuses = true, 1490 }, { 1491 .instances = &I915_PW_INSTANCES( 1492 I915_PW("PW_D", &xelpd_pwdoms_pw_d, 1493 .hsw.idx = XELPD_PW_CTL_IDX_PW_D), 1494 ), 1495 .ops = &hsw_power_well_ops, 1496 .irq_pipe_mask = BIT(PIPE_D), 1497 .has_fuses = true, 1498 }, { 1499 .instances = &I915_PW_INSTANCES( 1500 I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A), 1501 I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B), 1502 I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1), 1503 I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2), 1504 I915_PW("AUX_TC3", &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3), 1505 I915_PW("AUX_TC4", &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4), 1506 ), 1507 .ops = &xelpdp_aux_power_well_ops, 1508 }, 1509 }; 1510 1511 static const struct i915_power_well_desc_list xelpdp_power_wells[] = { 1512 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1513 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1514 I915_PW_DESCRIPTORS(xelpdp_power_wells_main), 1515 }; 1516 1517 static void init_power_well_domains(const struct i915_power_well_instance *inst, 1518 struct i915_power_well *power_well) 1519 { 1520 int j; 1521 1522 if (!inst->domain_list) 1523 return; 1524 1525 if (inst->domain_list->count == 0) { 1526 bitmap_fill(power_well->domains.bits, POWER_DOMAIN_NUM); 1527 1528 return; 1529 } 1530 1531 for (j = 0; j < inst->domain_list->count; j++) 1532 set_bit(inst->domain_list->list[j], power_well->domains.bits); 1533 } 1534 1535 #define for_each_power_well_instance_in_desc_list(_desc_list, _desc_count, _desc, _inst) \ 1536 for ((_desc) = (_desc_list); (_desc) - (_desc_list) < (_desc_count); (_desc)++) \ 1537 for ((_inst) = (_desc)->instances->list; \ 1538 (_inst) - (_desc)->instances->list < (_desc)->instances->count; \ 1539 (_inst)++) 1540 1541 #define for_each_power_well_instance(_desc_list, _desc_count, _descs, _desc, _inst) \ 1542 for ((_descs) = (_desc_list); \ 1543 (_descs) - (_desc_list) < (_desc_count); \ 1544 (_descs)++) \ 1545 for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \ 1546 (_desc), (_inst)) 1547 1548 static int 1549 __set_power_wells(struct i915_power_domains *power_domains, 1550 const struct i915_power_well_desc_list *power_well_descs, 1551 int power_well_descs_sz) 1552 { 1553 struct drm_i915_private *i915 = container_of(power_domains, 1554 struct drm_i915_private, 1555 display.power.domains); 1556 u64 power_well_ids = 0; 1557 const struct i915_power_well_desc_list *desc_list; 1558 const struct i915_power_well_desc *desc; 1559 const struct i915_power_well_instance *inst; 1560 int power_well_count = 0; 1561 int plt_idx = 0; 1562 1563 for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) 1564 power_well_count++; 1565 1566 power_domains->power_well_count = power_well_count; 1567 power_domains->power_wells = 1568 kcalloc(power_well_count, 1569 sizeof(*power_domains->power_wells), 1570 GFP_KERNEL); 1571 if (!power_domains->power_wells) 1572 return -ENOMEM; 1573 1574 for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) { 1575 struct i915_power_well *pw = &power_domains->power_wells[plt_idx]; 1576 enum i915_power_well_id id = inst->id; 1577 1578 pw->desc = desc; 1579 drm_WARN_ON(&i915->drm, 1580 overflows_type(inst - desc->instances->list, pw->instance_idx)); 1581 pw->instance_idx = inst - desc->instances->list; 1582 1583 init_power_well_domains(inst, pw); 1584 1585 plt_idx++; 1586 1587 if (id == DISP_PW_ID_NONE) 1588 continue; 1589 1590 drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) * 8); 1591 drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id)); 1592 power_well_ids |= BIT_ULL(id); 1593 } 1594 1595 return 0; 1596 } 1597 1598 #define set_power_wells(power_domains, __power_well_descs) \ 1599 __set_power_wells(power_domains, __power_well_descs, \ 1600 ARRAY_SIZE(__power_well_descs)) 1601 1602 /** 1603 * intel_display_power_map_init - initialize power domain -> power well mappings 1604 * @power_domains: power domain state 1605 * 1606 * Creates all the power wells for the current platform, initializes the 1607 * dynamic state for them and initializes the mapping of each power well to 1608 * all the power domains the power well belongs to. 1609 */ 1610 int intel_display_power_map_init(struct i915_power_domains *power_domains) 1611 { 1612 struct drm_i915_private *i915 = container_of(power_domains, 1613 struct drm_i915_private, 1614 display.power.domains); 1615 /* 1616 * The enabling order will be from lower to higher indexed wells, 1617 * the disabling order is reversed. 1618 */ 1619 if (!HAS_DISPLAY(i915)) { 1620 power_domains->power_well_count = 0; 1621 return 0; 1622 } 1623 1624 if (DISPLAY_VER(i915) >= 14) 1625 return set_power_wells(power_domains, xelpdp_power_wells); 1626 else if (DISPLAY_VER(i915) >= 13) 1627 return set_power_wells(power_domains, xelpd_power_wells); 1628 else if (IS_DG1(i915)) 1629 return set_power_wells(power_domains, dg1_power_wells); 1630 else if (IS_ALDERLAKE_S(i915)) 1631 return set_power_wells(power_domains, adls_power_wells); 1632 else if (IS_ROCKETLAKE(i915)) 1633 return set_power_wells(power_domains, rkl_power_wells); 1634 else if (DISPLAY_VER(i915) == 12) 1635 return set_power_wells(power_domains, tgl_power_wells); 1636 else if (DISPLAY_VER(i915) == 11) 1637 return set_power_wells(power_domains, icl_power_wells); 1638 else if (IS_GEMINILAKE(i915)) 1639 return set_power_wells(power_domains, glk_power_wells); 1640 else if (IS_BROXTON(i915)) 1641 return set_power_wells(power_domains, bxt_power_wells); 1642 else if (DISPLAY_VER(i915) == 9) 1643 return set_power_wells(power_domains, skl_power_wells); 1644 else if (IS_CHERRYVIEW(i915)) 1645 return set_power_wells(power_domains, chv_power_wells); 1646 else if (IS_BROADWELL(i915)) 1647 return set_power_wells(power_domains, bdw_power_wells); 1648 else if (IS_HASWELL(i915)) 1649 return set_power_wells(power_domains, hsw_power_wells); 1650 else if (IS_VALLEYVIEW(i915)) 1651 return set_power_wells(power_domains, vlv_power_wells); 1652 else if (IS_I830(i915)) 1653 return set_power_wells(power_domains, i830_power_wells); 1654 else 1655 return set_power_wells(power_domains, i9xx_power_wells); 1656 } 1657 1658 /** 1659 * intel_display_power_map_cleanup - clean up power domain -> power well mappings 1660 * @power_domains: power domain state 1661 * 1662 * Cleans up all the state that was initialized by intel_display_power_map_init(). 1663 */ 1664 void intel_display_power_map_cleanup(struct i915_power_domains *power_domains) 1665 { 1666 kfree(power_domains->power_wells); 1667 } 1668