1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_POWER_H__ 7 #define __INTEL_DISPLAY_POWER_H__ 8 9 #include <linux/mutex.h> 10 #include <linux/workqueue.h> 11 12 #include "intel_wakeref.h" 13 14 enum aux_ch; 15 enum dpio_channel; 16 enum dpio_phy; 17 enum i915_drm_suspend_mode; 18 enum port; 19 struct drm_i915_private; 20 struct i915_power_well; 21 struct intel_encoder; 22 struct seq_file; 23 24 /* 25 * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances 26 * consecutive, so that the pipe,transcoder,port -> power domain macros 27 * work correctly. 28 */ 29 enum intel_display_power_domain { 30 POWER_DOMAIN_DISPLAY_CORE, 31 POWER_DOMAIN_PIPE_A, 32 POWER_DOMAIN_PIPE_B, 33 POWER_DOMAIN_PIPE_C, 34 POWER_DOMAIN_PIPE_D, 35 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 36 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 37 POWER_DOMAIN_PIPE_PANEL_FITTER_C, 38 POWER_DOMAIN_PIPE_PANEL_FITTER_D, 39 POWER_DOMAIN_TRANSCODER_A, 40 POWER_DOMAIN_TRANSCODER_B, 41 POWER_DOMAIN_TRANSCODER_C, 42 POWER_DOMAIN_TRANSCODER_D, 43 POWER_DOMAIN_TRANSCODER_EDP, 44 POWER_DOMAIN_TRANSCODER_DSI_A, 45 POWER_DOMAIN_TRANSCODER_DSI_C, 46 47 /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */ 48 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 49 50 POWER_DOMAIN_PORT_DDI_LANES_A, 51 POWER_DOMAIN_PORT_DDI_LANES_B, 52 POWER_DOMAIN_PORT_DDI_LANES_C, 53 POWER_DOMAIN_PORT_DDI_LANES_D, 54 POWER_DOMAIN_PORT_DDI_LANES_E, 55 POWER_DOMAIN_PORT_DDI_LANES_F, 56 57 POWER_DOMAIN_PORT_DDI_LANES_TC1, 58 POWER_DOMAIN_PORT_DDI_LANES_TC2, 59 POWER_DOMAIN_PORT_DDI_LANES_TC3, 60 POWER_DOMAIN_PORT_DDI_LANES_TC4, 61 POWER_DOMAIN_PORT_DDI_LANES_TC5, 62 POWER_DOMAIN_PORT_DDI_LANES_TC6, 63 64 POWER_DOMAIN_PORT_DDI_IO_A, 65 POWER_DOMAIN_PORT_DDI_IO_B, 66 POWER_DOMAIN_PORT_DDI_IO_C, 67 POWER_DOMAIN_PORT_DDI_IO_D, 68 POWER_DOMAIN_PORT_DDI_IO_E, 69 POWER_DOMAIN_PORT_DDI_IO_F, 70 71 POWER_DOMAIN_PORT_DDI_IO_TC1, 72 POWER_DOMAIN_PORT_DDI_IO_TC2, 73 POWER_DOMAIN_PORT_DDI_IO_TC3, 74 POWER_DOMAIN_PORT_DDI_IO_TC4, 75 POWER_DOMAIN_PORT_DDI_IO_TC5, 76 POWER_DOMAIN_PORT_DDI_IO_TC6, 77 78 POWER_DOMAIN_PORT_DSI, 79 POWER_DOMAIN_PORT_CRT, 80 POWER_DOMAIN_PORT_OTHER, 81 POWER_DOMAIN_VGA, 82 POWER_DOMAIN_AUDIO_MMIO, 83 POWER_DOMAIN_AUDIO_PLAYBACK, 84 85 POWER_DOMAIN_AUX_IO_A, 86 POWER_DOMAIN_AUX_IO_B, 87 POWER_DOMAIN_AUX_IO_C, 88 POWER_DOMAIN_AUX_IO_D, 89 POWER_DOMAIN_AUX_IO_E, 90 POWER_DOMAIN_AUX_IO_F, 91 92 POWER_DOMAIN_AUX_A, 93 POWER_DOMAIN_AUX_B, 94 POWER_DOMAIN_AUX_C, 95 POWER_DOMAIN_AUX_D, 96 POWER_DOMAIN_AUX_E, 97 POWER_DOMAIN_AUX_F, 98 99 POWER_DOMAIN_AUX_USBC1, 100 POWER_DOMAIN_AUX_USBC2, 101 POWER_DOMAIN_AUX_USBC3, 102 POWER_DOMAIN_AUX_USBC4, 103 POWER_DOMAIN_AUX_USBC5, 104 POWER_DOMAIN_AUX_USBC6, 105 106 POWER_DOMAIN_AUX_TBT1, 107 POWER_DOMAIN_AUX_TBT2, 108 POWER_DOMAIN_AUX_TBT3, 109 POWER_DOMAIN_AUX_TBT4, 110 POWER_DOMAIN_AUX_TBT5, 111 POWER_DOMAIN_AUX_TBT6, 112 113 POWER_DOMAIN_GMBUS, 114 POWER_DOMAIN_MODESET, 115 POWER_DOMAIN_GT_IRQ, 116 POWER_DOMAIN_DC_OFF, 117 POWER_DOMAIN_TC_COLD_OFF, 118 POWER_DOMAIN_INIT, 119 120 POWER_DOMAIN_NUM, 121 POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM, 122 }; 123 124 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 125 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 126 ((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A) 127 #define POWER_DOMAIN_TRANSCODER(tran) \ 128 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 129 (tran) + POWER_DOMAIN_TRANSCODER_A) 130 131 struct intel_power_domain_mask { 132 DECLARE_BITMAP(bits, POWER_DOMAIN_NUM); 133 }; 134 135 struct i915_power_domains { 136 /* 137 * Power wells needed for initialization at driver init and suspend 138 * time are on. They are kept on until after the first modeset. 139 */ 140 bool initializing; 141 bool display_core_suspended; 142 int power_well_count; 143 144 u32 dc_state; 145 u32 target_dc_state; 146 u32 allowed_dc_mask; 147 148 intel_wakeref_t init_wakeref; 149 intel_wakeref_t disable_wakeref; 150 151 struct mutex lock; 152 int domain_use_count[POWER_DOMAIN_NUM]; 153 154 struct delayed_work async_put_work; 155 intel_wakeref_t async_put_wakeref; 156 struct intel_power_domain_mask async_put_domains[2]; 157 158 struct i915_power_well *power_wells; 159 }; 160 161 struct intel_display_power_domain_set { 162 struct intel_power_domain_mask mask; 163 #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM 164 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM]; 165 #endif 166 }; 167 168 #define for_each_power_domain(__domain, __mask) \ 169 for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \ 170 for_each_if(test_bit((__domain), (__mask)->bits)) 171 172 int intel_power_domains_init(struct drm_i915_private *dev_priv); 173 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 174 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 175 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 176 void intel_power_domains_enable(struct drm_i915_private *dev_priv); 177 void intel_power_domains_disable(struct drm_i915_private *dev_priv); 178 void intel_power_domains_suspend(struct drm_i915_private *dev_priv, bool s2idle); 179 void intel_power_domains_resume(struct drm_i915_private *dev_priv); 180 void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv); 181 182 void intel_display_power_suspend_late(struct drm_i915_private *i915); 183 void intel_display_power_resume_early(struct drm_i915_private *i915); 184 void intel_display_power_suspend(struct drm_i915_private *i915); 185 void intel_display_power_resume(struct drm_i915_private *i915); 186 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 187 u32 state); 188 189 const char * 190 intel_display_power_domain_str(enum intel_display_power_domain domain); 191 192 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 193 enum intel_display_power_domain domain); 194 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 195 enum intel_display_power_domain domain); 196 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 197 enum intel_display_power_domain domain); 198 intel_wakeref_t 199 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 200 enum intel_display_power_domain domain); 201 void __intel_display_power_put_async(struct drm_i915_private *i915, 202 enum intel_display_power_domain domain, 203 intel_wakeref_t wakeref); 204 void intel_display_power_flush_work(struct drm_i915_private *i915); 205 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 206 void intel_display_power_put(struct drm_i915_private *dev_priv, 207 enum intel_display_power_domain domain, 208 intel_wakeref_t wakeref); 209 static inline void 210 intel_display_power_put_async(struct drm_i915_private *i915, 211 enum intel_display_power_domain domain, 212 intel_wakeref_t wakeref) 213 { 214 __intel_display_power_put_async(i915, domain, wakeref); 215 } 216 #else 217 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 218 enum intel_display_power_domain domain); 219 220 static inline void 221 intel_display_power_put(struct drm_i915_private *i915, 222 enum intel_display_power_domain domain, 223 intel_wakeref_t wakeref) 224 { 225 intel_display_power_put_unchecked(i915, domain); 226 } 227 228 static inline void 229 intel_display_power_put_async(struct drm_i915_private *i915, 230 enum intel_display_power_domain domain, 231 intel_wakeref_t wakeref) 232 { 233 __intel_display_power_put_async(i915, domain, -1); 234 } 235 #endif 236 237 void 238 intel_display_power_get_in_set(struct drm_i915_private *i915, 239 struct intel_display_power_domain_set *power_domain_set, 240 enum intel_display_power_domain domain); 241 242 bool 243 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, 244 struct intel_display_power_domain_set *power_domain_set, 245 enum intel_display_power_domain domain); 246 247 void 248 intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 249 struct intel_display_power_domain_set *power_domain_set, 250 struct intel_power_domain_mask *mask); 251 252 static inline void 253 intel_display_power_put_all_in_set(struct drm_i915_private *i915, 254 struct intel_display_power_domain_set *power_domain_set) 255 { 256 intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask); 257 } 258 259 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m); 260 261 enum intel_display_power_domain 262 intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port); 263 enum intel_display_power_domain 264 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port); 265 enum intel_display_power_domain 266 intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch); 267 enum intel_display_power_domain 268 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch); 269 enum intel_display_power_domain 270 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch); 271 272 /* 273 * FIXME: We should probably switch this to a 0-based scheme to be consistent 274 * with how we now name/number DBUF_CTL instances. 275 */ 276 enum dbuf_slice { 277 DBUF_S1, 278 DBUF_S2, 279 DBUF_S3, 280 DBUF_S4, 281 I915_MAX_DBUF_SLICES 282 }; 283 284 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 285 u8 req_slices); 286 287 #define with_intel_display_power(i915, domain, wf) \ 288 for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 289 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 290 291 #define with_intel_display_power_if_enabled(i915, domain, wf) \ 292 for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \ 293 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 294 295 #endif /* __INTEL_DISPLAY_POWER_H__ */ 296