1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_POWER_H__ 7 #define __INTEL_DISPLAY_POWER_H__ 8 9 #include "intel_display.h" 10 #include "intel_runtime_pm.h" 11 #include "i915_reg.h" 12 13 struct drm_i915_private; 14 struct intel_encoder; 15 16 enum intel_display_power_domain { 17 POWER_DOMAIN_DISPLAY_CORE, 18 POWER_DOMAIN_PIPE_A, 19 POWER_DOMAIN_PIPE_B, 20 POWER_DOMAIN_PIPE_C, 21 POWER_DOMAIN_PIPE_D, 22 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 23 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 24 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 25 POWER_DOMAIN_PIPE_D_PANEL_FITTER, 26 POWER_DOMAIN_TRANSCODER_A, 27 POWER_DOMAIN_TRANSCODER_B, 28 POWER_DOMAIN_TRANSCODER_C, 29 POWER_DOMAIN_TRANSCODER_D, 30 POWER_DOMAIN_TRANSCODER_EDP, 31 /* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */ 32 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 33 POWER_DOMAIN_TRANSCODER_DSI_A, 34 POWER_DOMAIN_TRANSCODER_DSI_C, 35 POWER_DOMAIN_PORT_DDI_A_LANES, 36 POWER_DOMAIN_PORT_DDI_B_LANES, 37 POWER_DOMAIN_PORT_DDI_C_LANES, 38 POWER_DOMAIN_PORT_DDI_D_LANES, 39 POWER_DOMAIN_PORT_DDI_TC1_LANES = POWER_DOMAIN_PORT_DDI_D_LANES, 40 POWER_DOMAIN_PORT_DDI_E_LANES, 41 POWER_DOMAIN_PORT_DDI_TC2_LANES = POWER_DOMAIN_PORT_DDI_E_LANES, 42 POWER_DOMAIN_PORT_DDI_F_LANES, 43 POWER_DOMAIN_PORT_DDI_TC3_LANES = POWER_DOMAIN_PORT_DDI_F_LANES, 44 POWER_DOMAIN_PORT_DDI_TC4_LANES, 45 POWER_DOMAIN_PORT_DDI_TC5_LANES, 46 POWER_DOMAIN_PORT_DDI_TC6_LANES, 47 POWER_DOMAIN_PORT_DDI_A_IO, 48 POWER_DOMAIN_PORT_DDI_B_IO, 49 POWER_DOMAIN_PORT_DDI_C_IO, 50 POWER_DOMAIN_PORT_DDI_D_IO, 51 POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO, 52 POWER_DOMAIN_PORT_DDI_E_IO, 53 POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO, 54 POWER_DOMAIN_PORT_DDI_F_IO, 55 POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO, 56 POWER_DOMAIN_PORT_DDI_G_IO, 57 POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO, 58 POWER_DOMAIN_PORT_DDI_H_IO, 59 POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO, 60 POWER_DOMAIN_PORT_DDI_I_IO, 61 POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO, 62 POWER_DOMAIN_PORT_DSI, 63 POWER_DOMAIN_PORT_CRT, 64 POWER_DOMAIN_PORT_OTHER, 65 POWER_DOMAIN_VGA, 66 POWER_DOMAIN_AUDIO, 67 POWER_DOMAIN_AUX_A, 68 POWER_DOMAIN_AUX_B, 69 POWER_DOMAIN_AUX_C, 70 POWER_DOMAIN_AUX_D, 71 POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D, 72 POWER_DOMAIN_AUX_E, 73 POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E, 74 POWER_DOMAIN_AUX_F, 75 POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F, 76 POWER_DOMAIN_AUX_TC4, 77 POWER_DOMAIN_AUX_TC5, 78 POWER_DOMAIN_AUX_TC6, 79 POWER_DOMAIN_AUX_IO_A, 80 POWER_DOMAIN_AUX_TBT1, 81 POWER_DOMAIN_AUX_TBT2, 82 POWER_DOMAIN_AUX_TBT3, 83 POWER_DOMAIN_AUX_TBT4, 84 POWER_DOMAIN_AUX_TBT5, 85 POWER_DOMAIN_AUX_TBT6, 86 POWER_DOMAIN_GMBUS, 87 POWER_DOMAIN_MODESET, 88 POWER_DOMAIN_GT_IRQ, 89 POWER_DOMAIN_DPLL_DC_OFF, 90 POWER_DOMAIN_INIT, 91 92 POWER_DOMAIN_NUM, 93 }; 94 95 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 96 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 97 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 98 #define POWER_DOMAIN_TRANSCODER(tran) \ 99 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 100 (tran) + POWER_DOMAIN_TRANSCODER_A) 101 102 struct i915_power_well; 103 104 struct i915_power_well_ops { 105 /* 106 * Synchronize the well's hw state to match the current sw state, for 107 * example enable/disable it based on the current refcount. Called 108 * during driver init and resume time, possibly after first calling 109 * the enable/disable handlers. 110 */ 111 void (*sync_hw)(struct drm_i915_private *dev_priv, 112 struct i915_power_well *power_well); 113 /* 114 * Enable the well and resources that depend on it (for example 115 * interrupts located on the well). Called after the 0->1 refcount 116 * transition. 117 */ 118 void (*enable)(struct drm_i915_private *dev_priv, 119 struct i915_power_well *power_well); 120 /* 121 * Disable the well and resources that depend on it. Called after 122 * the 1->0 refcount transition. 123 */ 124 void (*disable)(struct drm_i915_private *dev_priv, 125 struct i915_power_well *power_well); 126 /* Returns the hw enabled state. */ 127 bool (*is_enabled)(struct drm_i915_private *dev_priv, 128 struct i915_power_well *power_well); 129 }; 130 131 struct i915_power_well_regs { 132 i915_reg_t bios; 133 i915_reg_t driver; 134 i915_reg_t kvmr; 135 i915_reg_t debug; 136 }; 137 138 /* Power well structure for haswell */ 139 struct i915_power_well_desc { 140 const char *name; 141 bool always_on; 142 u64 domains; 143 /* unique identifier for this power well */ 144 enum i915_power_well_id id; 145 /* 146 * Arbitraty data associated with this power well. Platform and power 147 * well specific. 148 */ 149 union { 150 struct { 151 /* 152 * request/status flag index in the PUNIT power well 153 * control/status registers. 154 */ 155 u8 idx; 156 } vlv; 157 struct { 158 enum dpio_phy phy; 159 } bxt; 160 struct { 161 const struct i915_power_well_regs *regs; 162 /* 163 * request/status flag index in the power well 164 * constrol/status registers. 165 */ 166 u8 idx; 167 /* Mask of pipes whose IRQ logic is backed by the pw */ 168 u8 irq_pipe_mask; 169 /* The pw is backing the VGA functionality */ 170 bool has_vga:1; 171 bool has_fuses:1; 172 /* 173 * The pw is for an ICL+ TypeC PHY port in 174 * Thunderbolt mode. 175 */ 176 bool is_tc_tbt:1; 177 } hsw; 178 }; 179 const struct i915_power_well_ops *ops; 180 }; 181 182 struct i915_power_well { 183 const struct i915_power_well_desc *desc; 184 /* power well enable/disable usage count */ 185 int count; 186 /* cached hw enabled state */ 187 bool hw_enabled; 188 }; 189 190 struct i915_power_domains { 191 /* 192 * Power wells needed for initialization at driver init and suspend 193 * time are on. They are kept on until after the first modeset. 194 */ 195 bool initializing; 196 bool display_core_suspended; 197 int power_well_count; 198 199 intel_wakeref_t wakeref; 200 201 struct mutex lock; 202 int domain_use_count[POWER_DOMAIN_NUM]; 203 204 struct delayed_work async_put_work; 205 intel_wakeref_t async_put_wakeref; 206 u64 async_put_domains[2]; 207 208 struct i915_power_well *power_wells; 209 }; 210 211 #define for_each_power_domain(domain, mask) \ 212 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 213 for_each_if(BIT_ULL(domain) & (mask)) 214 215 #define for_each_power_well(__dev_priv, __power_well) \ 216 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ 217 (__power_well) - (__dev_priv)->power_domains.power_wells < \ 218 (__dev_priv)->power_domains.power_well_count; \ 219 (__power_well)++) 220 221 #define for_each_power_well_reverse(__dev_priv, __power_well) \ 222 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ 223 (__dev_priv)->power_domains.power_well_count - 1; \ 224 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ 225 (__power_well)--) 226 227 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ 228 for_each_power_well(__dev_priv, __power_well) \ 229 for_each_if((__power_well)->desc->domains & (__domain_mask)) 230 231 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ 232 for_each_power_well_reverse(__dev_priv, __power_well) \ 233 for_each_if((__power_well)->desc->domains & (__domain_mask)) 234 235 void skl_enable_dc6(struct drm_i915_private *dev_priv); 236 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv); 237 void bxt_enable_dc9(struct drm_i915_private *dev_priv); 238 void bxt_disable_dc9(struct drm_i915_private *dev_priv); 239 void gen9_enable_dc5(struct drm_i915_private *dev_priv); 240 241 int intel_power_domains_init(struct drm_i915_private *dev_priv); 242 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 243 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 244 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 245 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume); 246 void icl_display_core_uninit(struct drm_i915_private *dev_priv); 247 void intel_power_domains_enable(struct drm_i915_private *dev_priv); 248 void intel_power_domains_disable(struct drm_i915_private *dev_priv); 249 void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 250 enum i915_drm_suspend_mode); 251 void intel_power_domains_resume(struct drm_i915_private *dev_priv); 252 void hsw_enable_pc8(struct drm_i915_private *dev_priv); 253 void hsw_disable_pc8(struct drm_i915_private *dev_priv); 254 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume); 255 void bxt_display_core_uninit(struct drm_i915_private *dev_priv); 256 257 const char * 258 intel_display_power_domain_str(struct drm_i915_private *i915, 259 enum intel_display_power_domain domain); 260 261 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 262 enum intel_display_power_domain domain); 263 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 264 enum intel_display_power_domain domain); 265 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 266 enum intel_display_power_domain domain); 267 intel_wakeref_t 268 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 269 enum intel_display_power_domain domain); 270 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 271 enum intel_display_power_domain domain); 272 void __intel_display_power_put_async(struct drm_i915_private *i915, 273 enum intel_display_power_domain domain, 274 intel_wakeref_t wakeref); 275 void intel_display_power_flush_work(struct drm_i915_private *i915); 276 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 277 void intel_display_power_put(struct drm_i915_private *dev_priv, 278 enum intel_display_power_domain domain, 279 intel_wakeref_t wakeref); 280 static inline void 281 intel_display_power_put_async(struct drm_i915_private *i915, 282 enum intel_display_power_domain domain, 283 intel_wakeref_t wakeref) 284 { 285 __intel_display_power_put_async(i915, domain, wakeref); 286 } 287 #else 288 static inline void 289 intel_display_power_put(struct drm_i915_private *i915, 290 enum intel_display_power_domain domain, 291 intel_wakeref_t wakeref) 292 { 293 intel_display_power_put_unchecked(i915, domain); 294 } 295 296 static inline void 297 intel_display_power_put_async(struct drm_i915_private *i915, 298 enum intel_display_power_domain domain, 299 intel_wakeref_t wakeref) 300 { 301 __intel_display_power_put_async(i915, domain, -1); 302 } 303 #endif 304 305 #define with_intel_display_power(i915, domain, wf) \ 306 for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 307 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 308 309 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, 310 u8 req_slices); 311 312 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 313 bool override, unsigned int mask); 314 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 315 enum dpio_channel ch, bool override); 316 317 #endif /* __INTEL_DISPLAY_POWER_H__ */ 318