1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_POWER_H__ 7 #define __INTEL_DISPLAY_POWER_H__ 8 9 #include "intel_display.h" 10 #include "intel_runtime_pm.h" 11 #include "i915_reg.h" 12 13 struct drm_i915_private; 14 struct intel_encoder; 15 16 enum intel_display_power_domain { 17 POWER_DOMAIN_DISPLAY_CORE, 18 POWER_DOMAIN_PIPE_A, 19 POWER_DOMAIN_PIPE_B, 20 POWER_DOMAIN_PIPE_C, 21 POWER_DOMAIN_PIPE_D, 22 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 23 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 24 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 25 POWER_DOMAIN_PIPE_D_PANEL_FITTER, 26 POWER_DOMAIN_TRANSCODER_A, 27 POWER_DOMAIN_TRANSCODER_B, 28 POWER_DOMAIN_TRANSCODER_C, 29 POWER_DOMAIN_TRANSCODER_D, 30 POWER_DOMAIN_TRANSCODER_EDP, 31 /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */ 32 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 33 POWER_DOMAIN_TRANSCODER_DSI_A, 34 POWER_DOMAIN_TRANSCODER_DSI_C, 35 POWER_DOMAIN_PORT_DDI_A_LANES, 36 POWER_DOMAIN_PORT_DDI_B_LANES, 37 POWER_DOMAIN_PORT_DDI_C_LANES, 38 POWER_DOMAIN_PORT_DDI_D_LANES, 39 POWER_DOMAIN_PORT_DDI_E_LANES, 40 POWER_DOMAIN_PORT_DDI_F_LANES, 41 POWER_DOMAIN_PORT_DDI_G_LANES, 42 POWER_DOMAIN_PORT_DDI_H_LANES, 43 POWER_DOMAIN_PORT_DDI_I_LANES, 44 POWER_DOMAIN_PORT_DDI_A_IO, 45 POWER_DOMAIN_PORT_DDI_B_IO, 46 POWER_DOMAIN_PORT_DDI_C_IO, 47 POWER_DOMAIN_PORT_DDI_D_IO, 48 POWER_DOMAIN_PORT_DDI_E_IO, 49 POWER_DOMAIN_PORT_DDI_F_IO, 50 POWER_DOMAIN_PORT_DDI_G_IO, 51 POWER_DOMAIN_PORT_DDI_H_IO, 52 POWER_DOMAIN_PORT_DDI_I_IO, 53 POWER_DOMAIN_PORT_DSI, 54 POWER_DOMAIN_PORT_CRT, 55 POWER_DOMAIN_PORT_OTHER, 56 POWER_DOMAIN_VGA, 57 POWER_DOMAIN_AUDIO, 58 POWER_DOMAIN_AUX_A, 59 POWER_DOMAIN_AUX_B, 60 POWER_DOMAIN_AUX_C, 61 POWER_DOMAIN_AUX_D, 62 POWER_DOMAIN_AUX_E, 63 POWER_DOMAIN_AUX_F, 64 POWER_DOMAIN_AUX_G, 65 POWER_DOMAIN_AUX_H, 66 POWER_DOMAIN_AUX_I, 67 POWER_DOMAIN_AUX_IO_A, 68 POWER_DOMAIN_AUX_C_TBT, 69 POWER_DOMAIN_AUX_D_TBT, 70 POWER_DOMAIN_AUX_E_TBT, 71 POWER_DOMAIN_AUX_F_TBT, 72 POWER_DOMAIN_AUX_G_TBT, 73 POWER_DOMAIN_AUX_H_TBT, 74 POWER_DOMAIN_AUX_I_TBT, 75 POWER_DOMAIN_GMBUS, 76 POWER_DOMAIN_MODESET, 77 POWER_DOMAIN_GT_IRQ, 78 POWER_DOMAIN_DPLL_DC_OFF, 79 POWER_DOMAIN_TC_COLD_OFF, 80 POWER_DOMAIN_INIT, 81 82 POWER_DOMAIN_NUM, 83 }; 84 85 /* 86 * i915_power_well_id: 87 * 88 * IDs used to look up power wells. Power wells accessed directly bypassing 89 * the power domains framework must be assigned a unique ID. The rest of power 90 * wells must be assigned DISP_PW_ID_NONE. 91 */ 92 enum i915_power_well_id { 93 DISP_PW_ID_NONE, 94 95 VLV_DISP_PW_DISP2D, 96 BXT_DISP_PW_DPIO_CMN_A, 97 VLV_DISP_PW_DPIO_CMN_BC, 98 GLK_DISP_PW_DPIO_CMN_C, 99 CHV_DISP_PW_DPIO_CMN_D, 100 HSW_DISP_PW_GLOBAL, 101 SKL_DISP_PW_MISC_IO, 102 SKL_DISP_PW_1, 103 SKL_DISP_PW_2, 104 CNL_DISP_PW_DDI_F_IO, 105 CNL_DISP_PW_DDI_F_AUX, 106 ICL_DISP_PW_3, 107 SKL_DISP_DC_OFF, 108 TGL_DISP_PW_TC_COLD_OFF, 109 }; 110 111 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 112 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 113 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 114 #define POWER_DOMAIN_TRANSCODER(tran) \ 115 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 116 (tran) + POWER_DOMAIN_TRANSCODER_A) 117 118 struct i915_power_well; 119 120 struct i915_power_well_ops { 121 /* 122 * Synchronize the well's hw state to match the current sw state, for 123 * example enable/disable it based on the current refcount. Called 124 * during driver init and resume time, possibly after first calling 125 * the enable/disable handlers. 126 */ 127 void (*sync_hw)(struct drm_i915_private *dev_priv, 128 struct i915_power_well *power_well); 129 /* 130 * Enable the well and resources that depend on it (for example 131 * interrupts located on the well). Called after the 0->1 refcount 132 * transition. 133 */ 134 void (*enable)(struct drm_i915_private *dev_priv, 135 struct i915_power_well *power_well); 136 /* 137 * Disable the well and resources that depend on it. Called after 138 * the 1->0 refcount transition. 139 */ 140 void (*disable)(struct drm_i915_private *dev_priv, 141 struct i915_power_well *power_well); 142 /* Returns the hw enabled state. */ 143 bool (*is_enabled)(struct drm_i915_private *dev_priv, 144 struct i915_power_well *power_well); 145 }; 146 147 struct i915_power_well_regs { 148 i915_reg_t bios; 149 i915_reg_t driver; 150 i915_reg_t kvmr; 151 i915_reg_t debug; 152 }; 153 154 /* Power well structure for haswell */ 155 struct i915_power_well_desc { 156 const char *name; 157 bool always_on; 158 u64 domains; 159 /* unique identifier for this power well */ 160 enum i915_power_well_id id; 161 /* 162 * Arbitraty data associated with this power well. Platform and power 163 * well specific. 164 */ 165 union { 166 struct { 167 /* 168 * request/status flag index in the PUNIT power well 169 * control/status registers. 170 */ 171 u8 idx; 172 } vlv; 173 struct { 174 enum dpio_phy phy; 175 } bxt; 176 struct { 177 const struct i915_power_well_regs *regs; 178 /* 179 * request/status flag index in the power well 180 * constrol/status registers. 181 */ 182 u8 idx; 183 /* Mask of pipes whose IRQ logic is backed by the pw */ 184 u8 irq_pipe_mask; 185 /* The pw is backing the VGA functionality */ 186 bool has_vga:1; 187 bool has_fuses:1; 188 /* 189 * The pw is for an ICL+ TypeC PHY port in 190 * Thunderbolt mode. 191 */ 192 bool is_tc_tbt:1; 193 } hsw; 194 }; 195 const struct i915_power_well_ops *ops; 196 }; 197 198 struct i915_power_well { 199 const struct i915_power_well_desc *desc; 200 /* power well enable/disable usage count */ 201 int count; 202 /* cached hw enabled state */ 203 bool hw_enabled; 204 }; 205 206 struct i915_power_domains { 207 /* 208 * Power wells needed for initialization at driver init and suspend 209 * time are on. They are kept on until after the first modeset. 210 */ 211 bool initializing; 212 bool display_core_suspended; 213 int power_well_count; 214 215 intel_wakeref_t init_wakeref; 216 intel_wakeref_t disable_wakeref; 217 218 struct mutex lock; 219 int domain_use_count[POWER_DOMAIN_NUM]; 220 221 struct delayed_work async_put_work; 222 intel_wakeref_t async_put_wakeref; 223 u64 async_put_domains[2]; 224 225 struct i915_power_well *power_wells; 226 }; 227 228 struct intel_display_power_domain_set { 229 u64 mask; 230 #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM 231 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM]; 232 #endif 233 }; 234 235 #define for_each_power_domain(domain, mask) \ 236 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 237 for_each_if(BIT_ULL(domain) & (mask)) 238 239 #define for_each_power_well(__dev_priv, __power_well) \ 240 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ 241 (__power_well) - (__dev_priv)->power_domains.power_wells < \ 242 (__dev_priv)->power_domains.power_well_count; \ 243 (__power_well)++) 244 245 #define for_each_power_well_reverse(__dev_priv, __power_well) \ 246 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ 247 (__dev_priv)->power_domains.power_well_count - 1; \ 248 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ 249 (__power_well)--) 250 251 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ 252 for_each_power_well(__dev_priv, __power_well) \ 253 for_each_if((__power_well)->desc->domains & (__domain_mask)) 254 255 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ 256 for_each_power_well_reverse(__dev_priv, __power_well) \ 257 for_each_if((__power_well)->desc->domains & (__domain_mask)) 258 259 int intel_power_domains_init(struct drm_i915_private *dev_priv); 260 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 261 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 262 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 263 void intel_power_domains_enable(struct drm_i915_private *dev_priv); 264 void intel_power_domains_disable(struct drm_i915_private *dev_priv); 265 void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 266 enum i915_drm_suspend_mode); 267 void intel_power_domains_resume(struct drm_i915_private *dev_priv); 268 269 void intel_display_power_suspend_late(struct drm_i915_private *i915); 270 void intel_display_power_resume_early(struct drm_i915_private *i915); 271 void intel_display_power_suspend(struct drm_i915_private *i915); 272 void intel_display_power_resume(struct drm_i915_private *i915); 273 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 274 u32 state); 275 276 const char * 277 intel_display_power_domain_str(enum intel_display_power_domain domain); 278 279 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 280 enum intel_display_power_domain domain); 281 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 282 enum i915_power_well_id power_well_id); 283 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 284 enum intel_display_power_domain domain); 285 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 286 enum intel_display_power_domain domain); 287 intel_wakeref_t 288 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 289 enum intel_display_power_domain domain); 290 void __intel_display_power_put_async(struct drm_i915_private *i915, 291 enum intel_display_power_domain domain, 292 intel_wakeref_t wakeref); 293 void intel_display_power_flush_work(struct drm_i915_private *i915); 294 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 295 void intel_display_power_put(struct drm_i915_private *dev_priv, 296 enum intel_display_power_domain domain, 297 intel_wakeref_t wakeref); 298 static inline void 299 intel_display_power_put_async(struct drm_i915_private *i915, 300 enum intel_display_power_domain domain, 301 intel_wakeref_t wakeref) 302 { 303 __intel_display_power_put_async(i915, domain, wakeref); 304 } 305 #else 306 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 307 enum intel_display_power_domain domain); 308 309 static inline void 310 intel_display_power_put(struct drm_i915_private *i915, 311 enum intel_display_power_domain domain, 312 intel_wakeref_t wakeref) 313 { 314 intel_display_power_put_unchecked(i915, domain); 315 } 316 317 static inline void 318 intel_display_power_put_async(struct drm_i915_private *i915, 319 enum intel_display_power_domain domain, 320 intel_wakeref_t wakeref) 321 { 322 __intel_display_power_put_async(i915, domain, -1); 323 } 324 #endif 325 326 void 327 intel_display_power_get_in_set(struct drm_i915_private *i915, 328 struct intel_display_power_domain_set *power_domain_set, 329 enum intel_display_power_domain domain); 330 331 bool 332 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, 333 struct intel_display_power_domain_set *power_domain_set, 334 enum intel_display_power_domain domain); 335 336 void 337 intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 338 struct intel_display_power_domain_set *power_domain_set, 339 u64 mask); 340 341 static inline void 342 intel_display_power_put_all_in_set(struct drm_i915_private *i915, 343 struct intel_display_power_domain_set *power_domain_set) 344 { 345 intel_display_power_put_mask_in_set(i915, power_domain_set, power_domain_set->mask); 346 } 347 348 enum dbuf_slice { 349 DBUF_S1, 350 DBUF_S2, 351 I915_MAX_DBUF_SLICES 352 }; 353 354 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 355 u8 req_slices); 356 357 #define with_intel_display_power(i915, domain, wf) \ 358 for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 359 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 360 361 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 362 bool override, unsigned int mask); 363 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 364 enum dpio_channel ch, bool override); 365 366 #endif /* __INTEL_DISPLAY_POWER_H__ */ 367