1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_POWER_H__ 7 #define __INTEL_DISPLAY_POWER_H__ 8 9 #include "intel_display.h" 10 #include "intel_runtime_pm.h" 11 #include "i915_reg.h" 12 13 struct drm_i915_private; 14 struct intel_encoder; 15 16 enum intel_display_power_domain { 17 POWER_DOMAIN_DISPLAY_CORE, 18 POWER_DOMAIN_PIPE_A, 19 POWER_DOMAIN_PIPE_B, 20 POWER_DOMAIN_PIPE_C, 21 POWER_DOMAIN_PIPE_D, 22 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 23 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 24 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 25 POWER_DOMAIN_PIPE_D_PANEL_FITTER, 26 POWER_DOMAIN_TRANSCODER_A, 27 POWER_DOMAIN_TRANSCODER_B, 28 POWER_DOMAIN_TRANSCODER_C, 29 POWER_DOMAIN_TRANSCODER_D, 30 POWER_DOMAIN_TRANSCODER_EDP, 31 /* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */ 32 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 33 POWER_DOMAIN_TRANSCODER_DSI_A, 34 POWER_DOMAIN_TRANSCODER_DSI_C, 35 POWER_DOMAIN_PORT_DDI_A_LANES, 36 POWER_DOMAIN_PORT_DDI_B_LANES, 37 POWER_DOMAIN_PORT_DDI_C_LANES, 38 POWER_DOMAIN_PORT_DDI_D_LANES, 39 POWER_DOMAIN_PORT_DDI_E_LANES, 40 POWER_DOMAIN_PORT_DDI_F_LANES, 41 POWER_DOMAIN_PORT_DDI_G_LANES, 42 POWER_DOMAIN_PORT_DDI_H_LANES, 43 POWER_DOMAIN_PORT_DDI_I_LANES, 44 POWER_DOMAIN_PORT_DDI_A_IO, 45 POWER_DOMAIN_PORT_DDI_B_IO, 46 POWER_DOMAIN_PORT_DDI_C_IO, 47 POWER_DOMAIN_PORT_DDI_D_IO, 48 POWER_DOMAIN_PORT_DDI_E_IO, 49 POWER_DOMAIN_PORT_DDI_F_IO, 50 POWER_DOMAIN_PORT_DDI_G_IO, 51 POWER_DOMAIN_PORT_DDI_H_IO, 52 POWER_DOMAIN_PORT_DDI_I_IO, 53 POWER_DOMAIN_PORT_DSI, 54 POWER_DOMAIN_PORT_CRT, 55 POWER_DOMAIN_PORT_OTHER, 56 POWER_DOMAIN_VGA, 57 POWER_DOMAIN_AUDIO, 58 POWER_DOMAIN_AUX_A, 59 POWER_DOMAIN_AUX_B, 60 POWER_DOMAIN_AUX_C, 61 POWER_DOMAIN_AUX_D, 62 POWER_DOMAIN_AUX_E, 63 POWER_DOMAIN_AUX_F, 64 POWER_DOMAIN_AUX_G, 65 POWER_DOMAIN_AUX_H, 66 POWER_DOMAIN_AUX_I, 67 POWER_DOMAIN_AUX_IO_A, 68 POWER_DOMAIN_AUX_C_TBT, 69 POWER_DOMAIN_AUX_D_TBT, 70 POWER_DOMAIN_AUX_E_TBT, 71 POWER_DOMAIN_AUX_F_TBT, 72 POWER_DOMAIN_AUX_G_TBT, 73 POWER_DOMAIN_AUX_H_TBT, 74 POWER_DOMAIN_AUX_I_TBT, 75 POWER_DOMAIN_GMBUS, 76 POWER_DOMAIN_MODESET, 77 POWER_DOMAIN_GT_IRQ, 78 POWER_DOMAIN_DPLL_DC_OFF, 79 POWER_DOMAIN_INIT, 80 81 POWER_DOMAIN_NUM, 82 }; 83 84 /* 85 * i915_power_well_id: 86 * 87 * IDs used to look up power wells. Power wells accessed directly bypassing 88 * the power domains framework must be assigned a unique ID. The rest of power 89 * wells must be assigned DISP_PW_ID_NONE. 90 */ 91 enum i915_power_well_id { 92 DISP_PW_ID_NONE, 93 94 VLV_DISP_PW_DISP2D, 95 BXT_DISP_PW_DPIO_CMN_A, 96 VLV_DISP_PW_DPIO_CMN_BC, 97 GLK_DISP_PW_DPIO_CMN_C, 98 CHV_DISP_PW_DPIO_CMN_D, 99 HSW_DISP_PW_GLOBAL, 100 SKL_DISP_PW_MISC_IO, 101 SKL_DISP_PW_1, 102 SKL_DISP_PW_2, 103 }; 104 105 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 106 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 107 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 108 #define POWER_DOMAIN_TRANSCODER(tran) \ 109 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 110 (tran) + POWER_DOMAIN_TRANSCODER_A) 111 112 struct i915_power_well; 113 114 struct i915_power_well_ops { 115 /* 116 * Synchronize the well's hw state to match the current sw state, for 117 * example enable/disable it based on the current refcount. Called 118 * during driver init and resume time, possibly after first calling 119 * the enable/disable handlers. 120 */ 121 void (*sync_hw)(struct drm_i915_private *dev_priv, 122 struct i915_power_well *power_well); 123 /* 124 * Enable the well and resources that depend on it (for example 125 * interrupts located on the well). Called after the 0->1 refcount 126 * transition. 127 */ 128 void (*enable)(struct drm_i915_private *dev_priv, 129 struct i915_power_well *power_well); 130 /* 131 * Disable the well and resources that depend on it. Called after 132 * the 1->0 refcount transition. 133 */ 134 void (*disable)(struct drm_i915_private *dev_priv, 135 struct i915_power_well *power_well); 136 /* Returns the hw enabled state. */ 137 bool (*is_enabled)(struct drm_i915_private *dev_priv, 138 struct i915_power_well *power_well); 139 }; 140 141 struct i915_power_well_regs { 142 i915_reg_t bios; 143 i915_reg_t driver; 144 i915_reg_t kvmr; 145 i915_reg_t debug; 146 }; 147 148 /* Power well structure for haswell */ 149 struct i915_power_well_desc { 150 const char *name; 151 bool always_on; 152 u64 domains; 153 /* unique identifier for this power well */ 154 enum i915_power_well_id id; 155 /* 156 * Arbitraty data associated with this power well. Platform and power 157 * well specific. 158 */ 159 union { 160 struct { 161 /* 162 * request/status flag index in the PUNIT power well 163 * control/status registers. 164 */ 165 u8 idx; 166 } vlv; 167 struct { 168 enum dpio_phy phy; 169 } bxt; 170 struct { 171 const struct i915_power_well_regs *regs; 172 /* 173 * request/status flag index in the power well 174 * constrol/status registers. 175 */ 176 u8 idx; 177 /* Mask of pipes whose IRQ logic is backed by the pw */ 178 u8 irq_pipe_mask; 179 /* The pw is backing the VGA functionality */ 180 bool has_vga:1; 181 bool has_fuses:1; 182 /* 183 * The pw is for an ICL+ TypeC PHY port in 184 * Thunderbolt mode. 185 */ 186 bool is_tc_tbt:1; 187 } hsw; 188 }; 189 const struct i915_power_well_ops *ops; 190 }; 191 192 struct i915_power_well { 193 const struct i915_power_well_desc *desc; 194 /* power well enable/disable usage count */ 195 int count; 196 /* cached hw enabled state */ 197 bool hw_enabled; 198 }; 199 200 struct i915_power_domains { 201 /* 202 * Power wells needed for initialization at driver init and suspend 203 * time are on. They are kept on until after the first modeset. 204 */ 205 bool initializing; 206 bool display_core_suspended; 207 int power_well_count; 208 209 intel_wakeref_t wakeref; 210 211 struct mutex lock; 212 int domain_use_count[POWER_DOMAIN_NUM]; 213 214 struct delayed_work async_put_work; 215 intel_wakeref_t async_put_wakeref; 216 u64 async_put_domains[2]; 217 218 struct i915_power_well *power_wells; 219 }; 220 221 #define for_each_power_domain(domain, mask) \ 222 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 223 for_each_if(BIT_ULL(domain) & (mask)) 224 225 #define for_each_power_well(__dev_priv, __power_well) \ 226 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ 227 (__power_well) - (__dev_priv)->power_domains.power_wells < \ 228 (__dev_priv)->power_domains.power_well_count; \ 229 (__power_well)++) 230 231 #define for_each_power_well_reverse(__dev_priv, __power_well) \ 232 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ 233 (__dev_priv)->power_domains.power_well_count - 1; \ 234 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ 235 (__power_well)--) 236 237 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ 238 for_each_power_well(__dev_priv, __power_well) \ 239 for_each_if((__power_well)->desc->domains & (__domain_mask)) 240 241 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ 242 for_each_power_well_reverse(__dev_priv, __power_well) \ 243 for_each_if((__power_well)->desc->domains & (__domain_mask)) 244 245 int intel_power_domains_init(struct drm_i915_private *dev_priv); 246 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 247 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 248 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 249 void intel_power_domains_enable(struct drm_i915_private *dev_priv); 250 void intel_power_domains_disable(struct drm_i915_private *dev_priv); 251 void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 252 enum i915_drm_suspend_mode); 253 void intel_power_domains_resume(struct drm_i915_private *dev_priv); 254 255 void intel_display_power_suspend_late(struct drm_i915_private *i915); 256 void intel_display_power_resume_early(struct drm_i915_private *i915); 257 void intel_display_power_suspend(struct drm_i915_private *i915); 258 void intel_display_power_resume(struct drm_i915_private *i915); 259 260 const char * 261 intel_display_power_domain_str(enum intel_display_power_domain domain); 262 263 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 264 enum intel_display_power_domain domain); 265 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 266 enum intel_display_power_domain domain); 267 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 268 enum intel_display_power_domain domain); 269 intel_wakeref_t 270 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 271 enum intel_display_power_domain domain); 272 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 273 enum intel_display_power_domain domain); 274 void __intel_display_power_put_async(struct drm_i915_private *i915, 275 enum intel_display_power_domain domain, 276 intel_wakeref_t wakeref); 277 void intel_display_power_flush_work(struct drm_i915_private *i915); 278 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 279 void intel_display_power_put(struct drm_i915_private *dev_priv, 280 enum intel_display_power_domain domain, 281 intel_wakeref_t wakeref); 282 static inline void 283 intel_display_power_put_async(struct drm_i915_private *i915, 284 enum intel_display_power_domain domain, 285 intel_wakeref_t wakeref) 286 { 287 __intel_display_power_put_async(i915, domain, wakeref); 288 } 289 #else 290 static inline void 291 intel_display_power_put(struct drm_i915_private *i915, 292 enum intel_display_power_domain domain, 293 intel_wakeref_t wakeref) 294 { 295 intel_display_power_put_unchecked(i915, domain); 296 } 297 298 static inline void 299 intel_display_power_put_async(struct drm_i915_private *i915, 300 enum intel_display_power_domain domain, 301 intel_wakeref_t wakeref) 302 { 303 __intel_display_power_put_async(i915, domain, -1); 304 } 305 #endif 306 307 #define with_intel_display_power(i915, domain, wf) \ 308 for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 309 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 310 311 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, 312 u8 req_slices); 313 314 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 315 bool override, unsigned int mask); 316 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 317 enum dpio_channel ch, bool override); 318 319 #endif /* __INTEL_DISPLAY_POWER_H__ */ 320