1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #ifndef __INTEL_DISPLAY_POWER_H__
7 #define __INTEL_DISPLAY_POWER_H__
8 
9 #include "intel_wakeref.h"
10 
11 enum aux_ch;
12 enum dpio_channel;
13 enum dpio_phy;
14 enum i915_drm_suspend_mode;
15 enum port;
16 struct drm_i915_private;
17 struct i915_power_well;
18 struct intel_encoder;
19 
20 /*
21  * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances
22  * consecutive, so that the pipe,transcoder,port -> power domain macros
23  * work correctly.
24  */
25 enum intel_display_power_domain {
26 	POWER_DOMAIN_DISPLAY_CORE,
27 	POWER_DOMAIN_PIPE_A,
28 	POWER_DOMAIN_PIPE_B,
29 	POWER_DOMAIN_PIPE_C,
30 	POWER_DOMAIN_PIPE_D,
31 	POWER_DOMAIN_PIPE_PANEL_FITTER_A,
32 	POWER_DOMAIN_PIPE_PANEL_FITTER_B,
33 	POWER_DOMAIN_PIPE_PANEL_FITTER_C,
34 	POWER_DOMAIN_PIPE_PANEL_FITTER_D,
35 	POWER_DOMAIN_TRANSCODER_A,
36 	POWER_DOMAIN_TRANSCODER_B,
37 	POWER_DOMAIN_TRANSCODER_C,
38 	POWER_DOMAIN_TRANSCODER_D,
39 	POWER_DOMAIN_TRANSCODER_EDP,
40 	POWER_DOMAIN_TRANSCODER_DSI_A,
41 	POWER_DOMAIN_TRANSCODER_DSI_C,
42 
43 	/* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
44 	POWER_DOMAIN_TRANSCODER_VDSC_PW2,
45 
46 	POWER_DOMAIN_PORT_DDI_LANES_A,
47 	POWER_DOMAIN_PORT_DDI_LANES_B,
48 	POWER_DOMAIN_PORT_DDI_LANES_C,
49 	POWER_DOMAIN_PORT_DDI_LANES_D,
50 	POWER_DOMAIN_PORT_DDI_LANES_E,
51 	POWER_DOMAIN_PORT_DDI_LANES_F,
52 
53 	POWER_DOMAIN_PORT_DDI_LANES_TC1,
54 	POWER_DOMAIN_PORT_DDI_LANES_TC2,
55 	POWER_DOMAIN_PORT_DDI_LANES_TC3,
56 	POWER_DOMAIN_PORT_DDI_LANES_TC4,
57 	POWER_DOMAIN_PORT_DDI_LANES_TC5,
58 	POWER_DOMAIN_PORT_DDI_LANES_TC6,
59 
60 	POWER_DOMAIN_PORT_DDI_IO_A,
61 	POWER_DOMAIN_PORT_DDI_IO_B,
62 	POWER_DOMAIN_PORT_DDI_IO_C,
63 	POWER_DOMAIN_PORT_DDI_IO_D,
64 	POWER_DOMAIN_PORT_DDI_IO_E,
65 	POWER_DOMAIN_PORT_DDI_IO_F,
66 
67 	POWER_DOMAIN_PORT_DDI_IO_TC1,
68 	POWER_DOMAIN_PORT_DDI_IO_TC2,
69 	POWER_DOMAIN_PORT_DDI_IO_TC3,
70 	POWER_DOMAIN_PORT_DDI_IO_TC4,
71 	POWER_DOMAIN_PORT_DDI_IO_TC5,
72 	POWER_DOMAIN_PORT_DDI_IO_TC6,
73 
74 	POWER_DOMAIN_PORT_DSI,
75 	POWER_DOMAIN_PORT_CRT,
76 	POWER_DOMAIN_PORT_OTHER,
77 	POWER_DOMAIN_VGA,
78 	POWER_DOMAIN_AUDIO_MMIO,
79 	POWER_DOMAIN_AUDIO_PLAYBACK,
80 	POWER_DOMAIN_AUX_A,
81 	POWER_DOMAIN_AUX_B,
82 	POWER_DOMAIN_AUX_C,
83 	POWER_DOMAIN_AUX_D,
84 	POWER_DOMAIN_AUX_E,
85 	POWER_DOMAIN_AUX_F,
86 
87 	POWER_DOMAIN_AUX_USBC1,
88 	POWER_DOMAIN_AUX_USBC2,
89 	POWER_DOMAIN_AUX_USBC3,
90 	POWER_DOMAIN_AUX_USBC4,
91 	POWER_DOMAIN_AUX_USBC5,
92 	POWER_DOMAIN_AUX_USBC6,
93 
94 	POWER_DOMAIN_AUX_IO_A,
95 
96 	POWER_DOMAIN_AUX_TBT1,
97 	POWER_DOMAIN_AUX_TBT2,
98 	POWER_DOMAIN_AUX_TBT3,
99 	POWER_DOMAIN_AUX_TBT4,
100 	POWER_DOMAIN_AUX_TBT5,
101 	POWER_DOMAIN_AUX_TBT6,
102 
103 	POWER_DOMAIN_GMBUS,
104 	POWER_DOMAIN_MODESET,
105 	POWER_DOMAIN_GT_IRQ,
106 	POWER_DOMAIN_DC_OFF,
107 	POWER_DOMAIN_TC_COLD_OFF,
108 	POWER_DOMAIN_INIT,
109 
110 	POWER_DOMAIN_NUM,
111 	POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM,
112 };
113 
114 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
115 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
116 		((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A)
117 #define POWER_DOMAIN_TRANSCODER(tran) \
118 	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
119 	 (tran) + POWER_DOMAIN_TRANSCODER_A)
120 
121 struct intel_power_domain_mask {
122 	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
123 };
124 
125 struct i915_power_domains {
126 	/*
127 	 * Power wells needed for initialization at driver init and suspend
128 	 * time are on. They are kept on until after the first modeset.
129 	 */
130 	bool initializing;
131 	bool display_core_suspended;
132 	int power_well_count;
133 
134 	intel_wakeref_t init_wakeref;
135 	intel_wakeref_t disable_wakeref;
136 
137 	struct mutex lock;
138 	int domain_use_count[POWER_DOMAIN_NUM];
139 
140 	struct delayed_work async_put_work;
141 	intel_wakeref_t async_put_wakeref;
142 	struct intel_power_domain_mask async_put_domains[2];
143 
144 	struct i915_power_well *power_wells;
145 };
146 
147 struct intel_display_power_domain_set {
148 	struct intel_power_domain_mask mask;
149 #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
150 	intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
151 #endif
152 };
153 
154 #define for_each_power_domain(__domain, __mask)				\
155 	for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++)	\
156 		for_each_if(test_bit((__domain), (__mask)->bits))
157 
158 int intel_power_domains_init(struct drm_i915_private *dev_priv);
159 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
160 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
161 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
162 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
163 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
164 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
165 				 enum i915_drm_suspend_mode);
166 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
167 void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv);
168 
169 void intel_display_power_suspend_late(struct drm_i915_private *i915);
170 void intel_display_power_resume_early(struct drm_i915_private *i915);
171 void intel_display_power_suspend(struct drm_i915_private *i915);
172 void intel_display_power_resume(struct drm_i915_private *i915);
173 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
174 					     u32 state);
175 
176 const char *
177 intel_display_power_domain_str(enum intel_display_power_domain domain);
178 
179 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
180 				    enum intel_display_power_domain domain);
181 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
182 				      enum intel_display_power_domain domain);
183 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
184 					enum intel_display_power_domain domain);
185 intel_wakeref_t
186 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
187 				   enum intel_display_power_domain domain);
188 void __intel_display_power_put_async(struct drm_i915_private *i915,
189 				     enum intel_display_power_domain domain,
190 				     intel_wakeref_t wakeref);
191 void intel_display_power_flush_work(struct drm_i915_private *i915);
192 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
193 void intel_display_power_put(struct drm_i915_private *dev_priv,
194 			     enum intel_display_power_domain domain,
195 			     intel_wakeref_t wakeref);
196 static inline void
197 intel_display_power_put_async(struct drm_i915_private *i915,
198 			      enum intel_display_power_domain domain,
199 			      intel_wakeref_t wakeref)
200 {
201 	__intel_display_power_put_async(i915, domain, wakeref);
202 }
203 #else
204 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
205 				       enum intel_display_power_domain domain);
206 
207 static inline void
208 intel_display_power_put(struct drm_i915_private *i915,
209 			enum intel_display_power_domain domain,
210 			intel_wakeref_t wakeref)
211 {
212 	intel_display_power_put_unchecked(i915, domain);
213 }
214 
215 static inline void
216 intel_display_power_put_async(struct drm_i915_private *i915,
217 			      enum intel_display_power_domain domain,
218 			      intel_wakeref_t wakeref)
219 {
220 	__intel_display_power_put_async(i915, domain, -1);
221 }
222 #endif
223 
224 void
225 intel_display_power_get_in_set(struct drm_i915_private *i915,
226 			       struct intel_display_power_domain_set *power_domain_set,
227 			       enum intel_display_power_domain domain);
228 
229 bool
230 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
231 					  struct intel_display_power_domain_set *power_domain_set,
232 					  enum intel_display_power_domain domain);
233 
234 void
235 intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
236 				    struct intel_display_power_domain_set *power_domain_set,
237 				    struct intel_power_domain_mask *mask);
238 
239 static inline void
240 intel_display_power_put_all_in_set(struct drm_i915_private *i915,
241 				   struct intel_display_power_domain_set *power_domain_set)
242 {
243 	intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
244 }
245 
246 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
247 
248 enum intel_display_power_domain
249 intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port);
250 enum intel_display_power_domain
251 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
252 enum intel_display_power_domain
253 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
254 enum intel_display_power_domain
255 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
256 
257 /*
258  * FIXME: We should probably switch this to a 0-based scheme to be consistent
259  * with how we now name/number DBUF_CTL instances.
260  */
261 enum dbuf_slice {
262 	DBUF_S1,
263 	DBUF_S2,
264 	DBUF_S3,
265 	DBUF_S4,
266 	I915_MAX_DBUF_SLICES
267 };
268 
269 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
270 			     u8 req_slices);
271 
272 #define with_intel_display_power(i915, domain, wf) \
273 	for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
274 	     intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
275 
276 #define with_intel_display_power_if_enabled(i915, domain, wf) \
277 	for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \
278 	     intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
279 
280 #endif /* __INTEL_DISPLAY_POWER_H__ */
281