1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_POWER_H__ 7 #define __INTEL_DISPLAY_POWER_H__ 8 9 #include "intel_display.h" 10 #include "intel_runtime_pm.h" 11 #include "i915_reg.h" 12 13 struct drm_i915_private; 14 struct intel_encoder; 15 16 enum intel_display_power_domain { 17 POWER_DOMAIN_DISPLAY_CORE, 18 POWER_DOMAIN_PIPE_A, 19 POWER_DOMAIN_PIPE_B, 20 POWER_DOMAIN_PIPE_C, 21 POWER_DOMAIN_PIPE_D, 22 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 23 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 24 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 25 POWER_DOMAIN_PIPE_D_PANEL_FITTER, 26 POWER_DOMAIN_TRANSCODER_A, 27 POWER_DOMAIN_TRANSCODER_B, 28 POWER_DOMAIN_TRANSCODER_C, 29 POWER_DOMAIN_TRANSCODER_D, 30 POWER_DOMAIN_TRANSCODER_EDP, 31 /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */ 32 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 33 POWER_DOMAIN_TRANSCODER_DSI_A, 34 POWER_DOMAIN_TRANSCODER_DSI_C, 35 POWER_DOMAIN_PORT_DDI_A_LANES, 36 POWER_DOMAIN_PORT_DDI_B_LANES, 37 POWER_DOMAIN_PORT_DDI_C_LANES, 38 POWER_DOMAIN_PORT_DDI_D_LANES, 39 POWER_DOMAIN_PORT_DDI_E_LANES, 40 POWER_DOMAIN_PORT_DDI_F_LANES, 41 POWER_DOMAIN_PORT_DDI_G_LANES, 42 POWER_DOMAIN_PORT_DDI_H_LANES, 43 POWER_DOMAIN_PORT_DDI_I_LANES, 44 POWER_DOMAIN_PORT_DDI_A_IO, 45 POWER_DOMAIN_PORT_DDI_B_IO, 46 POWER_DOMAIN_PORT_DDI_C_IO, 47 POWER_DOMAIN_PORT_DDI_D_IO, 48 POWER_DOMAIN_PORT_DDI_E_IO, 49 POWER_DOMAIN_PORT_DDI_F_IO, 50 POWER_DOMAIN_PORT_DDI_G_IO, 51 POWER_DOMAIN_PORT_DDI_H_IO, 52 POWER_DOMAIN_PORT_DDI_I_IO, 53 POWER_DOMAIN_PORT_DSI, 54 POWER_DOMAIN_PORT_CRT, 55 POWER_DOMAIN_PORT_OTHER, 56 POWER_DOMAIN_VGA, 57 POWER_DOMAIN_AUDIO, 58 POWER_DOMAIN_AUX_A, 59 POWER_DOMAIN_AUX_B, 60 POWER_DOMAIN_AUX_C, 61 POWER_DOMAIN_AUX_D, 62 POWER_DOMAIN_AUX_E, 63 POWER_DOMAIN_AUX_F, 64 POWER_DOMAIN_AUX_G, 65 POWER_DOMAIN_AUX_H, 66 POWER_DOMAIN_AUX_I, 67 POWER_DOMAIN_AUX_IO_A, 68 POWER_DOMAIN_AUX_C_TBT, 69 POWER_DOMAIN_AUX_D_TBT, 70 POWER_DOMAIN_AUX_E_TBT, 71 POWER_DOMAIN_AUX_F_TBT, 72 POWER_DOMAIN_AUX_G_TBT, 73 POWER_DOMAIN_AUX_H_TBT, 74 POWER_DOMAIN_AUX_I_TBT, 75 POWER_DOMAIN_GMBUS, 76 POWER_DOMAIN_MODESET, 77 POWER_DOMAIN_GT_IRQ, 78 POWER_DOMAIN_DPLL_DC_OFF, 79 POWER_DOMAIN_INIT, 80 81 POWER_DOMAIN_NUM, 82 }; 83 84 /* 85 * i915_power_well_id: 86 * 87 * IDs used to look up power wells. Power wells accessed directly bypassing 88 * the power domains framework must be assigned a unique ID. The rest of power 89 * wells must be assigned DISP_PW_ID_NONE. 90 */ 91 enum i915_power_well_id { 92 DISP_PW_ID_NONE, 93 94 VLV_DISP_PW_DISP2D, 95 BXT_DISP_PW_DPIO_CMN_A, 96 VLV_DISP_PW_DPIO_CMN_BC, 97 GLK_DISP_PW_DPIO_CMN_C, 98 CHV_DISP_PW_DPIO_CMN_D, 99 HSW_DISP_PW_GLOBAL, 100 SKL_DISP_PW_MISC_IO, 101 SKL_DISP_PW_1, 102 SKL_DISP_PW_2, 103 SKL_DISP_DC_OFF, 104 }; 105 106 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 107 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 108 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 109 #define POWER_DOMAIN_TRANSCODER(tran) \ 110 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 111 (tran) + POWER_DOMAIN_TRANSCODER_A) 112 113 struct i915_power_well; 114 115 struct i915_power_well_ops { 116 /* 117 * Synchronize the well's hw state to match the current sw state, for 118 * example enable/disable it based on the current refcount. Called 119 * during driver init and resume time, possibly after first calling 120 * the enable/disable handlers. 121 */ 122 void (*sync_hw)(struct drm_i915_private *dev_priv, 123 struct i915_power_well *power_well); 124 /* 125 * Enable the well and resources that depend on it (for example 126 * interrupts located on the well). Called after the 0->1 refcount 127 * transition. 128 */ 129 void (*enable)(struct drm_i915_private *dev_priv, 130 struct i915_power_well *power_well); 131 /* 132 * Disable the well and resources that depend on it. Called after 133 * the 1->0 refcount transition. 134 */ 135 void (*disable)(struct drm_i915_private *dev_priv, 136 struct i915_power_well *power_well); 137 /* Returns the hw enabled state. */ 138 bool (*is_enabled)(struct drm_i915_private *dev_priv, 139 struct i915_power_well *power_well); 140 }; 141 142 struct i915_power_well_regs { 143 i915_reg_t bios; 144 i915_reg_t driver; 145 i915_reg_t kvmr; 146 i915_reg_t debug; 147 }; 148 149 /* Power well structure for haswell */ 150 struct i915_power_well_desc { 151 const char *name; 152 bool always_on; 153 u64 domains; 154 /* unique identifier for this power well */ 155 enum i915_power_well_id id; 156 /* 157 * Arbitraty data associated with this power well. Platform and power 158 * well specific. 159 */ 160 union { 161 struct { 162 /* 163 * request/status flag index in the PUNIT power well 164 * control/status registers. 165 */ 166 u8 idx; 167 } vlv; 168 struct { 169 enum dpio_phy phy; 170 } bxt; 171 struct { 172 const struct i915_power_well_regs *regs; 173 /* 174 * request/status flag index in the power well 175 * constrol/status registers. 176 */ 177 u8 idx; 178 /* Mask of pipes whose IRQ logic is backed by the pw */ 179 u8 irq_pipe_mask; 180 /* The pw is backing the VGA functionality */ 181 bool has_vga:1; 182 bool has_fuses:1; 183 /* 184 * The pw is for an ICL+ TypeC PHY port in 185 * Thunderbolt mode. 186 */ 187 bool is_tc_tbt:1; 188 } hsw; 189 }; 190 const struct i915_power_well_ops *ops; 191 }; 192 193 struct i915_power_well { 194 const struct i915_power_well_desc *desc; 195 /* power well enable/disable usage count */ 196 int count; 197 /* cached hw enabled state */ 198 bool hw_enabled; 199 }; 200 201 struct i915_power_domains { 202 /* 203 * Power wells needed for initialization at driver init and suspend 204 * time are on. They are kept on until after the first modeset. 205 */ 206 bool initializing; 207 bool display_core_suspended; 208 int power_well_count; 209 210 intel_wakeref_t wakeref; 211 212 struct mutex lock; 213 int domain_use_count[POWER_DOMAIN_NUM]; 214 215 struct delayed_work async_put_work; 216 intel_wakeref_t async_put_wakeref; 217 u64 async_put_domains[2]; 218 219 struct i915_power_well *power_wells; 220 }; 221 222 #define for_each_power_domain(domain, mask) \ 223 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 224 for_each_if(BIT_ULL(domain) & (mask)) 225 226 #define for_each_power_well(__dev_priv, __power_well) \ 227 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ 228 (__power_well) - (__dev_priv)->power_domains.power_wells < \ 229 (__dev_priv)->power_domains.power_well_count; \ 230 (__power_well)++) 231 232 #define for_each_power_well_reverse(__dev_priv, __power_well) \ 233 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ 234 (__dev_priv)->power_domains.power_well_count - 1; \ 235 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ 236 (__power_well)--) 237 238 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ 239 for_each_power_well(__dev_priv, __power_well) \ 240 for_each_if((__power_well)->desc->domains & (__domain_mask)) 241 242 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ 243 for_each_power_well_reverse(__dev_priv, __power_well) \ 244 for_each_if((__power_well)->desc->domains & (__domain_mask)) 245 246 int intel_power_domains_init(struct drm_i915_private *dev_priv); 247 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 248 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 249 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 250 void intel_power_domains_enable(struct drm_i915_private *dev_priv); 251 void intel_power_domains_disable(struct drm_i915_private *dev_priv); 252 void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 253 enum i915_drm_suspend_mode); 254 void intel_power_domains_resume(struct drm_i915_private *dev_priv); 255 256 void intel_display_power_suspend_late(struct drm_i915_private *i915); 257 void intel_display_power_resume_early(struct drm_i915_private *i915); 258 void intel_display_power_suspend(struct drm_i915_private *i915); 259 void intel_display_power_resume(struct drm_i915_private *i915); 260 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 261 u32 state); 262 263 const char * 264 intel_display_power_domain_str(enum intel_display_power_domain domain); 265 266 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 267 enum intel_display_power_domain domain); 268 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 269 enum intel_display_power_domain domain); 270 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 271 enum intel_display_power_domain domain); 272 intel_wakeref_t 273 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 274 enum intel_display_power_domain domain); 275 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 276 enum intel_display_power_domain domain); 277 void __intel_display_power_put_async(struct drm_i915_private *i915, 278 enum intel_display_power_domain domain, 279 intel_wakeref_t wakeref); 280 void intel_display_power_flush_work(struct drm_i915_private *i915); 281 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 282 void intel_display_power_put(struct drm_i915_private *dev_priv, 283 enum intel_display_power_domain domain, 284 intel_wakeref_t wakeref); 285 static inline void 286 intel_display_power_put_async(struct drm_i915_private *i915, 287 enum intel_display_power_domain domain, 288 intel_wakeref_t wakeref) 289 { 290 __intel_display_power_put_async(i915, domain, wakeref); 291 } 292 #else 293 static inline void 294 intel_display_power_put(struct drm_i915_private *i915, 295 enum intel_display_power_domain domain, 296 intel_wakeref_t wakeref) 297 { 298 intel_display_power_put_unchecked(i915, domain); 299 } 300 301 static inline void 302 intel_display_power_put_async(struct drm_i915_private *i915, 303 enum intel_display_power_domain domain, 304 intel_wakeref_t wakeref) 305 { 306 __intel_display_power_put_async(i915, domain, -1); 307 } 308 #endif 309 310 #define with_intel_display_power(i915, domain, wf) \ 311 for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 312 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 313 314 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, 315 u8 req_slices); 316 317 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 318 bool override, unsigned int mask); 319 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 320 enum dpio_channel ch, bool override); 321 322 #endif /* __INTEL_DISPLAY_POWER_H__ */ 323