1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_POWER_H__ 7 #define __INTEL_DISPLAY_POWER_H__ 8 9 #include "intel_runtime_pm.h" 10 11 enum dpio_channel; 12 enum dpio_phy; 13 struct drm_i915_private; 14 struct i915_power_well; 15 struct intel_encoder; 16 17 /* 18 * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances 19 * consecutive, so that the pipe,transcoder,port -> power domain macros 20 * work correctly. 21 */ 22 enum intel_display_power_domain { 23 POWER_DOMAIN_DISPLAY_CORE, 24 POWER_DOMAIN_PIPE_A, 25 POWER_DOMAIN_PIPE_B, 26 POWER_DOMAIN_PIPE_C, 27 POWER_DOMAIN_PIPE_D, 28 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 29 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 30 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 31 POWER_DOMAIN_PIPE_D_PANEL_FITTER, 32 POWER_DOMAIN_TRANSCODER_A, 33 POWER_DOMAIN_TRANSCODER_B, 34 POWER_DOMAIN_TRANSCODER_C, 35 POWER_DOMAIN_TRANSCODER_D, 36 POWER_DOMAIN_TRANSCODER_EDP, 37 POWER_DOMAIN_TRANSCODER_DSI_A, 38 POWER_DOMAIN_TRANSCODER_DSI_C, 39 40 /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */ 41 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 42 43 POWER_DOMAIN_PORT_DDI_A_LANES, 44 POWER_DOMAIN_PORT_DDI_B_LANES, 45 POWER_DOMAIN_PORT_DDI_C_LANES, 46 POWER_DOMAIN_PORT_DDI_D_LANES, 47 POWER_DOMAIN_PORT_DDI_E_LANES, 48 POWER_DOMAIN_PORT_DDI_F_LANES, 49 POWER_DOMAIN_PORT_DDI_G_LANES, 50 POWER_DOMAIN_PORT_DDI_H_LANES, 51 POWER_DOMAIN_PORT_DDI_I_LANES, 52 53 POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_D_LANES, /* tgl+ */ 54 POWER_DOMAIN_PORT_DDI_LANES_TC2, 55 POWER_DOMAIN_PORT_DDI_LANES_TC3, 56 POWER_DOMAIN_PORT_DDI_LANES_TC4, 57 POWER_DOMAIN_PORT_DDI_LANES_TC5, 58 POWER_DOMAIN_PORT_DDI_LANES_TC6, 59 60 POWER_DOMAIN_PORT_DDI_LANES_D_XELPD = POWER_DOMAIN_PORT_DDI_LANES_TC5, /* XELPD */ 61 POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, 62 63 POWER_DOMAIN_PORT_DDI_A_IO, 64 POWER_DOMAIN_PORT_DDI_B_IO, 65 POWER_DOMAIN_PORT_DDI_C_IO, 66 POWER_DOMAIN_PORT_DDI_D_IO, 67 POWER_DOMAIN_PORT_DDI_E_IO, 68 POWER_DOMAIN_PORT_DDI_F_IO, 69 POWER_DOMAIN_PORT_DDI_G_IO, 70 POWER_DOMAIN_PORT_DDI_H_IO, 71 POWER_DOMAIN_PORT_DDI_I_IO, 72 73 POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_D_IO, /* tgl+ */ 74 POWER_DOMAIN_PORT_DDI_IO_TC2, 75 POWER_DOMAIN_PORT_DDI_IO_TC3, 76 POWER_DOMAIN_PORT_DDI_IO_TC4, 77 POWER_DOMAIN_PORT_DDI_IO_TC5, 78 POWER_DOMAIN_PORT_DDI_IO_TC6, 79 80 POWER_DOMAIN_PORT_DDI_IO_D_XELPD = POWER_DOMAIN_PORT_DDI_IO_TC5, /* XELPD */ 81 POWER_DOMAIN_PORT_DDI_IO_E_XELPD, 82 83 POWER_DOMAIN_PORT_DSI, 84 POWER_DOMAIN_PORT_CRT, 85 POWER_DOMAIN_PORT_OTHER, 86 POWER_DOMAIN_VGA, 87 POWER_DOMAIN_AUDIO_MMIO, 88 POWER_DOMAIN_AUDIO_PLAYBACK, 89 POWER_DOMAIN_AUX_A, 90 POWER_DOMAIN_AUX_B, 91 POWER_DOMAIN_AUX_C, 92 POWER_DOMAIN_AUX_D, 93 POWER_DOMAIN_AUX_E, 94 POWER_DOMAIN_AUX_F, 95 POWER_DOMAIN_AUX_G, 96 POWER_DOMAIN_AUX_H, 97 POWER_DOMAIN_AUX_I, 98 99 POWER_DOMAIN_AUX_USBC1 = POWER_DOMAIN_AUX_D, /* tgl+ */ 100 POWER_DOMAIN_AUX_USBC2, 101 POWER_DOMAIN_AUX_USBC3, 102 POWER_DOMAIN_AUX_USBC4, 103 POWER_DOMAIN_AUX_USBC5, 104 POWER_DOMAIN_AUX_USBC6, 105 106 POWER_DOMAIN_AUX_D_XELPD = POWER_DOMAIN_AUX_USBC5, /* XELPD */ 107 POWER_DOMAIN_AUX_E_XELPD, 108 109 POWER_DOMAIN_AUX_IO_A, 110 POWER_DOMAIN_AUX_C_TBT, 111 POWER_DOMAIN_AUX_D_TBT, 112 POWER_DOMAIN_AUX_E_TBT, 113 POWER_DOMAIN_AUX_F_TBT, 114 POWER_DOMAIN_AUX_G_TBT, 115 POWER_DOMAIN_AUX_H_TBT, 116 POWER_DOMAIN_AUX_I_TBT, 117 118 POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_D_TBT, /* tgl+ */ 119 POWER_DOMAIN_AUX_TBT2, 120 POWER_DOMAIN_AUX_TBT3, 121 POWER_DOMAIN_AUX_TBT4, 122 POWER_DOMAIN_AUX_TBT5, 123 POWER_DOMAIN_AUX_TBT6, 124 125 POWER_DOMAIN_GMBUS, 126 POWER_DOMAIN_MODESET, 127 POWER_DOMAIN_GT_IRQ, 128 POWER_DOMAIN_DC_OFF, 129 POWER_DOMAIN_TC_COLD_OFF, 130 POWER_DOMAIN_INIT, 131 132 POWER_DOMAIN_NUM, 133 }; 134 135 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 136 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 137 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 138 #define POWER_DOMAIN_TRANSCODER(tran) \ 139 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 140 (tran) + POWER_DOMAIN_TRANSCODER_A) 141 142 struct i915_power_domains { 143 /* 144 * Power wells needed for initialization at driver init and suspend 145 * time are on. They are kept on until after the first modeset. 146 */ 147 bool initializing; 148 bool display_core_suspended; 149 int power_well_count; 150 151 intel_wakeref_t init_wakeref; 152 intel_wakeref_t disable_wakeref; 153 154 struct mutex lock; 155 int domain_use_count[POWER_DOMAIN_NUM]; 156 157 struct delayed_work async_put_work; 158 intel_wakeref_t async_put_wakeref; 159 u64 async_put_domains[2]; 160 161 struct i915_power_well *power_wells; 162 }; 163 164 struct intel_display_power_domain_set { 165 u64 mask; 166 #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM 167 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM]; 168 #endif 169 }; 170 171 #define for_each_power_domain(domain, mask) \ 172 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 173 for_each_if(BIT_ULL(domain) & (mask)) 174 175 #define for_each_power_well(__dev_priv, __power_well) \ 176 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ 177 (__power_well) - (__dev_priv)->power_domains.power_wells < \ 178 (__dev_priv)->power_domains.power_well_count; \ 179 (__power_well)++) 180 181 #define for_each_power_well_reverse(__dev_priv, __power_well) \ 182 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ 183 (__dev_priv)->power_domains.power_well_count - 1; \ 184 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ 185 (__power_well)--) 186 187 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ 188 for_each_power_well(__dev_priv, __power_well) \ 189 for_each_if((__power_well)->desc->domains & (__domain_mask)) 190 191 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ 192 for_each_power_well_reverse(__dev_priv, __power_well) \ 193 for_each_if((__power_well)->desc->domains & (__domain_mask)) 194 195 int intel_power_domains_init(struct drm_i915_private *dev_priv); 196 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 197 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 198 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 199 void intel_power_domains_enable(struct drm_i915_private *dev_priv); 200 void intel_power_domains_disable(struct drm_i915_private *dev_priv); 201 void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 202 enum i915_drm_suspend_mode); 203 void intel_power_domains_resume(struct drm_i915_private *dev_priv); 204 void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv); 205 206 void intel_display_power_suspend_late(struct drm_i915_private *i915); 207 void intel_display_power_resume_early(struct drm_i915_private *i915); 208 void intel_display_power_suspend(struct drm_i915_private *i915); 209 void intel_display_power_resume(struct drm_i915_private *i915); 210 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 211 u32 state); 212 213 const char * 214 intel_display_power_domain_str(enum intel_display_power_domain domain); 215 216 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 217 enum intel_display_power_domain domain); 218 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 219 enum intel_display_power_domain domain); 220 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 221 enum intel_display_power_domain domain); 222 intel_wakeref_t 223 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 224 enum intel_display_power_domain domain); 225 void __intel_display_power_put_async(struct drm_i915_private *i915, 226 enum intel_display_power_domain domain, 227 intel_wakeref_t wakeref); 228 void intel_display_power_flush_work(struct drm_i915_private *i915); 229 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 230 void intel_display_power_put(struct drm_i915_private *dev_priv, 231 enum intel_display_power_domain domain, 232 intel_wakeref_t wakeref); 233 static inline void 234 intel_display_power_put_async(struct drm_i915_private *i915, 235 enum intel_display_power_domain domain, 236 intel_wakeref_t wakeref) 237 { 238 __intel_display_power_put_async(i915, domain, wakeref); 239 } 240 #else 241 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 242 enum intel_display_power_domain domain); 243 244 static inline void 245 intel_display_power_put(struct drm_i915_private *i915, 246 enum intel_display_power_domain domain, 247 intel_wakeref_t wakeref) 248 { 249 intel_display_power_put_unchecked(i915, domain); 250 } 251 252 static inline void 253 intel_display_power_put_async(struct drm_i915_private *i915, 254 enum intel_display_power_domain domain, 255 intel_wakeref_t wakeref) 256 { 257 __intel_display_power_put_async(i915, domain, -1); 258 } 259 #endif 260 261 void 262 intel_display_power_get_in_set(struct drm_i915_private *i915, 263 struct intel_display_power_domain_set *power_domain_set, 264 enum intel_display_power_domain domain); 265 266 bool 267 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, 268 struct intel_display_power_domain_set *power_domain_set, 269 enum intel_display_power_domain domain); 270 271 void 272 intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 273 struct intel_display_power_domain_set *power_domain_set, 274 u64 mask); 275 276 static inline void 277 intel_display_power_put_all_in_set(struct drm_i915_private *i915, 278 struct intel_display_power_domain_set *power_domain_set) 279 { 280 intel_display_power_put_mask_in_set(i915, power_domain_set, power_domain_set->mask); 281 } 282 283 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m); 284 285 /* 286 * FIXME: We should probably switch this to a 0-based scheme to be consistent 287 * with how we now name/number DBUF_CTL instances. 288 */ 289 enum dbuf_slice { 290 DBUF_S1, 291 DBUF_S2, 292 DBUF_S3, 293 DBUF_S4, 294 I915_MAX_DBUF_SLICES 295 }; 296 297 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 298 u8 req_slices); 299 300 #define with_intel_display_power(i915, domain, wf) \ 301 for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 302 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 303 304 #define with_intel_display_power_if_enabled(i915, domain, wf) \ 305 for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \ 306 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 307 308 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 309 bool override, unsigned int mask); 310 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 311 enum dpio_channel ch, bool override); 312 313 #endif /* __INTEL_DISPLAY_POWER_H__ */ 314