1df0566a6SJani Nikula /* SPDX-License-Identifier: MIT */ 2df0566a6SJani Nikula /* 3df0566a6SJani Nikula * Copyright © 2019 Intel Corporation 4df0566a6SJani Nikula */ 5df0566a6SJani Nikula 6df0566a6SJani Nikula #ifndef __INTEL_DISPLAY_POWER_H__ 7df0566a6SJani Nikula #define __INTEL_DISPLAY_POWER_H__ 8df0566a6SJani Nikula 9df0566a6SJani Nikula #include "intel_display.h" 10df0566a6SJani Nikula #include "intel_runtime_pm.h" 11df0566a6SJani Nikula #include "i915_reg.h" 12df0566a6SJani Nikula 13df0566a6SJani Nikula struct drm_i915_private; 14*de511df7SJani Nikula struct i915_power_well; 15df0566a6SJani Nikula struct intel_encoder; 16df0566a6SJani Nikula 17df0566a6SJani Nikula enum intel_display_power_domain { 18df0566a6SJani Nikula POWER_DOMAIN_DISPLAY_CORE, 19df0566a6SJani Nikula POWER_DOMAIN_PIPE_A, 20df0566a6SJani Nikula POWER_DOMAIN_PIPE_B, 21df0566a6SJani Nikula POWER_DOMAIN_PIPE_C, 221db27a72SMika Kahola POWER_DOMAIN_PIPE_D, 23df0566a6SJani Nikula POWER_DOMAIN_PIPE_A_PANEL_FITTER, 24df0566a6SJani Nikula POWER_DOMAIN_PIPE_B_PANEL_FITTER, 25df0566a6SJani Nikula POWER_DOMAIN_PIPE_C_PANEL_FITTER, 261db27a72SMika Kahola POWER_DOMAIN_PIPE_D_PANEL_FITTER, 27df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_A, 28df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_B, 29df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_C, 301db27a72SMika Kahola POWER_DOMAIN_TRANSCODER_D, 31df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_EDP, 32f7fd2373SJani Nikula /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */ 33276199e6SJosé Roberto de Souza POWER_DOMAIN_TRANSCODER_VDSC_PW2, 34df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_A, 35df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_C, 36df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_A_LANES, 37df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_B_LANES, 38df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_C_LANES, 39df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_D_LANES, 40df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_E_LANES, 41df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_F_LANES, 428a84bacbSImre Deak POWER_DOMAIN_PORT_DDI_G_LANES, 438a84bacbSImre Deak POWER_DOMAIN_PORT_DDI_H_LANES, 448a84bacbSImre Deak POWER_DOMAIN_PORT_DDI_I_LANES, 45c7392718SImre Deak 46c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_D_LANES, /* tgl+ */ 47c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC2, 48c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC3, 49c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC4, 50c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC5, 51c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC6, 52c7392718SImre Deak 53a6922f4aSMatt Roper POWER_DOMAIN_PORT_DDI_LANES_D_XELPD = POWER_DOMAIN_PORT_DDI_LANES_TC5, /* XELPD */ 54a6922f4aSMatt Roper POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, 55a6922f4aSMatt Roper 56df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_A_IO, 57df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_B_IO, 58df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_C_IO, 59df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_D_IO, 60df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_E_IO, 61df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_F_IO, 62656409bbSImre Deak POWER_DOMAIN_PORT_DDI_G_IO, 63656409bbSImre Deak POWER_DOMAIN_PORT_DDI_H_IO, 64656409bbSImre Deak POWER_DOMAIN_PORT_DDI_I_IO, 65c7392718SImre Deak 66c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_D_IO, /* tgl+ */ 67c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC2, 68c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC3, 69c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC4, 70c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC5, 71c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC6, 72c7392718SImre Deak 73a6922f4aSMatt Roper POWER_DOMAIN_PORT_DDI_IO_D_XELPD = POWER_DOMAIN_PORT_DDI_IO_TC5, /* XELPD */ 74a6922f4aSMatt Roper POWER_DOMAIN_PORT_DDI_IO_E_XELPD, 75a6922f4aSMatt Roper 76df0566a6SJani Nikula POWER_DOMAIN_PORT_DSI, 77df0566a6SJani Nikula POWER_DOMAIN_PORT_CRT, 78df0566a6SJani Nikula POWER_DOMAIN_PORT_OTHER, 79df0566a6SJani Nikula POWER_DOMAIN_VGA, 80615a7724SAnshuman Gupta POWER_DOMAIN_AUDIO_MMIO, 81615a7724SAnshuman Gupta POWER_DOMAIN_AUDIO_PLAYBACK, 82df0566a6SJani Nikula POWER_DOMAIN_AUX_A, 83df0566a6SJani Nikula POWER_DOMAIN_AUX_B, 84df0566a6SJani Nikula POWER_DOMAIN_AUX_C, 85df0566a6SJani Nikula POWER_DOMAIN_AUX_D, 86df0566a6SJani Nikula POWER_DOMAIN_AUX_E, 87df0566a6SJani Nikula POWER_DOMAIN_AUX_F, 888a84bacbSImre Deak POWER_DOMAIN_AUX_G, 898a84bacbSImre Deak POWER_DOMAIN_AUX_H, 908a84bacbSImre Deak POWER_DOMAIN_AUX_I, 91c7392718SImre Deak 92c7392718SImre Deak POWER_DOMAIN_AUX_USBC1 = POWER_DOMAIN_AUX_D, /* tgl+ */ 93c7392718SImre Deak POWER_DOMAIN_AUX_USBC2, 94c7392718SImre Deak POWER_DOMAIN_AUX_USBC3, 95c7392718SImre Deak POWER_DOMAIN_AUX_USBC4, 96c7392718SImre Deak POWER_DOMAIN_AUX_USBC5, 97c7392718SImre Deak POWER_DOMAIN_AUX_USBC6, 98c7392718SImre Deak 99a6922f4aSMatt Roper POWER_DOMAIN_AUX_D_XELPD = POWER_DOMAIN_AUX_USBC5, /* XELPD */ 100a6922f4aSMatt Roper POWER_DOMAIN_AUX_E_XELPD, 101a6922f4aSMatt Roper 102df0566a6SJani Nikula POWER_DOMAIN_AUX_IO_A, 1038a84bacbSImre Deak POWER_DOMAIN_AUX_C_TBT, 1048a84bacbSImre Deak POWER_DOMAIN_AUX_D_TBT, 1058a84bacbSImre Deak POWER_DOMAIN_AUX_E_TBT, 1068a84bacbSImre Deak POWER_DOMAIN_AUX_F_TBT, 1078a84bacbSImre Deak POWER_DOMAIN_AUX_G_TBT, 1088a84bacbSImre Deak POWER_DOMAIN_AUX_H_TBT, 1098a84bacbSImre Deak POWER_DOMAIN_AUX_I_TBT, 110c7392718SImre Deak 111c7392718SImre Deak POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_D_TBT, /* tgl+ */ 112c7392718SImre Deak POWER_DOMAIN_AUX_TBT2, 113c7392718SImre Deak POWER_DOMAIN_AUX_TBT3, 114c7392718SImre Deak POWER_DOMAIN_AUX_TBT4, 115c7392718SImre Deak POWER_DOMAIN_AUX_TBT5, 116c7392718SImre Deak POWER_DOMAIN_AUX_TBT6, 117c7392718SImre Deak 118df0566a6SJani Nikula POWER_DOMAIN_GMBUS, 119df0566a6SJani Nikula POWER_DOMAIN_MODESET, 120df0566a6SJani Nikula POWER_DOMAIN_GT_IRQ, 121808b79ebSJosé Roberto de Souza POWER_DOMAIN_DC_OFF, 1223c02934bSJosé Roberto de Souza POWER_DOMAIN_TC_COLD_OFF, 123df0566a6SJani Nikula POWER_DOMAIN_INIT, 124df0566a6SJani Nikula 125df0566a6SJani Nikula POWER_DOMAIN_NUM, 126df0566a6SJani Nikula }; 127df0566a6SJani Nikula 1283e5d0641SDaniele Ceraolo Spurio /* 1293e5d0641SDaniele Ceraolo Spurio * i915_power_well_id: 1303e5d0641SDaniele Ceraolo Spurio * 1313e5d0641SDaniele Ceraolo Spurio * IDs used to look up power wells. Power wells accessed directly bypassing 1323e5d0641SDaniele Ceraolo Spurio * the power domains framework must be assigned a unique ID. The rest of power 1333e5d0641SDaniele Ceraolo Spurio * wells must be assigned DISP_PW_ID_NONE. 1343e5d0641SDaniele Ceraolo Spurio */ 1353e5d0641SDaniele Ceraolo Spurio enum i915_power_well_id { 1363e5d0641SDaniele Ceraolo Spurio DISP_PW_ID_NONE, 1373e5d0641SDaniele Ceraolo Spurio 1383e5d0641SDaniele Ceraolo Spurio VLV_DISP_PW_DISP2D, 1393e5d0641SDaniele Ceraolo Spurio BXT_DISP_PW_DPIO_CMN_A, 1403e5d0641SDaniele Ceraolo Spurio VLV_DISP_PW_DPIO_CMN_BC, 1413e5d0641SDaniele Ceraolo Spurio GLK_DISP_PW_DPIO_CMN_C, 1423e5d0641SDaniele Ceraolo Spurio CHV_DISP_PW_DPIO_CMN_D, 1433e5d0641SDaniele Ceraolo Spurio HSW_DISP_PW_GLOBAL, 1443e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_MISC_IO, 1453e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_1, 1463e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_2, 147fc4a8c16SAnshuman Gupta ICL_DISP_PW_3, 1484645e906SAnshuman Gupta SKL_DISP_DC_OFF, 149240abb3cSLucas De Marchi TGL_DISP_PW_TC_COLD_OFF, 1503e5d0641SDaniele Ceraolo Spurio }; 1513e5d0641SDaniele Ceraolo Spurio 152df0566a6SJani Nikula #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 153df0566a6SJani Nikula #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 154df0566a6SJani Nikula ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 155df0566a6SJani Nikula #define POWER_DOMAIN_TRANSCODER(tran) \ 156df0566a6SJani Nikula ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 157df0566a6SJani Nikula (tran) + POWER_DOMAIN_TRANSCODER_A) 158df0566a6SJani Nikula 159df0566a6SJani Nikula struct i915_power_domains { 160df0566a6SJani Nikula /* 161df0566a6SJani Nikula * Power wells needed for initialization at driver init and suspend 162df0566a6SJani Nikula * time are on. They are kept on until after the first modeset. 163df0566a6SJani Nikula */ 164df0566a6SJani Nikula bool initializing; 165df0566a6SJani Nikula bool display_core_suspended; 166df0566a6SJani Nikula int power_well_count; 167df0566a6SJani Nikula 168a0b024edSImre Deak intel_wakeref_t init_wakeref; 16993b916fdSImre Deak intel_wakeref_t disable_wakeref; 170df0566a6SJani Nikula 171df0566a6SJani Nikula struct mutex lock; 172df0566a6SJani Nikula int domain_use_count[POWER_DOMAIN_NUM]; 173df0566a6SJani Nikula 174df0566a6SJani Nikula struct delayed_work async_put_work; 175df0566a6SJani Nikula intel_wakeref_t async_put_wakeref; 176df0566a6SJani Nikula u64 async_put_domains[2]; 177df0566a6SJani Nikula 178df0566a6SJani Nikula struct i915_power_well *power_wells; 179df0566a6SJani Nikula }; 180df0566a6SJani Nikula 1816979cb9aSImre Deak struct intel_display_power_domain_set { 1826979cb9aSImre Deak u64 mask; 1836979cb9aSImre Deak #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM 1846979cb9aSImre Deak intel_wakeref_t wakerefs[POWER_DOMAIN_NUM]; 1856979cb9aSImre Deak #endif 1866979cb9aSImre Deak }; 1876979cb9aSImre Deak 188df0566a6SJani Nikula #define for_each_power_domain(domain, mask) \ 189df0566a6SJani Nikula for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 190df0566a6SJani Nikula for_each_if(BIT_ULL(domain) & (mask)) 191df0566a6SJani Nikula 192df0566a6SJani Nikula #define for_each_power_well(__dev_priv, __power_well) \ 193df0566a6SJani Nikula for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ 194df0566a6SJani Nikula (__power_well) - (__dev_priv)->power_domains.power_wells < \ 195df0566a6SJani Nikula (__dev_priv)->power_domains.power_well_count; \ 196df0566a6SJani Nikula (__power_well)++) 197df0566a6SJani Nikula 198df0566a6SJani Nikula #define for_each_power_well_reverse(__dev_priv, __power_well) \ 199df0566a6SJani Nikula for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ 200df0566a6SJani Nikula (__dev_priv)->power_domains.power_well_count - 1; \ 201df0566a6SJani Nikula (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ 202df0566a6SJani Nikula (__power_well)--) 203df0566a6SJani Nikula 204df0566a6SJani Nikula #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ 205df0566a6SJani Nikula for_each_power_well(__dev_priv, __power_well) \ 206df0566a6SJani Nikula for_each_if((__power_well)->desc->domains & (__domain_mask)) 207df0566a6SJani Nikula 208df0566a6SJani Nikula #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ 209df0566a6SJani Nikula for_each_power_well_reverse(__dev_priv, __power_well) \ 210df0566a6SJani Nikula for_each_if((__power_well)->desc->domains & (__domain_mask)) 211df0566a6SJani Nikula 212df0566a6SJani Nikula int intel_power_domains_init(struct drm_i915_private *dev_priv); 213df0566a6SJani Nikula void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 214df0566a6SJani Nikula void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 21578dae1acSJanusz Krzysztofik void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 216df0566a6SJani Nikula void intel_power_domains_enable(struct drm_i915_private *dev_priv); 217df0566a6SJani Nikula void intel_power_domains_disable(struct drm_i915_private *dev_priv); 218df0566a6SJani Nikula void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 219df0566a6SJani Nikula enum i915_drm_suspend_mode); 220df0566a6SJani Nikula void intel_power_domains_resume(struct drm_i915_private *dev_priv); 221071b68ccSRodrigo Vivi 222071b68ccSRodrigo Vivi void intel_display_power_suspend_late(struct drm_i915_private *i915); 223071b68ccSRodrigo Vivi void intel_display_power_resume_early(struct drm_i915_private *i915); 224071b68ccSRodrigo Vivi void intel_display_power_suspend(struct drm_i915_private *i915); 225071b68ccSRodrigo Vivi void intel_display_power_resume(struct drm_i915_private *i915); 2261c4d821dSAnshuman Gupta void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 2271c4d821dSAnshuman Gupta u32 state); 228df0566a6SJani Nikula 229df0566a6SJani Nikula const char * 2308a84bacbSImre Deak intel_display_power_domain_str(enum intel_display_power_domain domain); 231df0566a6SJani Nikula 232df0566a6SJani Nikula bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 233df0566a6SJani Nikula enum intel_display_power_domain domain); 2349efa0c1aSAnshuman Gupta bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 2359efa0c1aSAnshuman Gupta enum i915_power_well_id power_well_id); 236df0566a6SJani Nikula bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 237df0566a6SJani Nikula enum intel_display_power_domain domain); 238df0566a6SJani Nikula intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 239df0566a6SJani Nikula enum intel_display_power_domain domain); 240df0566a6SJani Nikula intel_wakeref_t 241df0566a6SJani Nikula intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 242df0566a6SJani Nikula enum intel_display_power_domain domain); 243df0566a6SJani Nikula void __intel_display_power_put_async(struct drm_i915_private *i915, 244df0566a6SJani Nikula enum intel_display_power_domain domain, 245df0566a6SJani Nikula intel_wakeref_t wakeref); 246df0566a6SJani Nikula void intel_display_power_flush_work(struct drm_i915_private *i915); 247df0566a6SJani Nikula #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 248df0566a6SJani Nikula void intel_display_power_put(struct drm_i915_private *dev_priv, 249df0566a6SJani Nikula enum intel_display_power_domain domain, 250df0566a6SJani Nikula intel_wakeref_t wakeref); 251df0566a6SJani Nikula static inline void 252df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 253df0566a6SJani Nikula enum intel_display_power_domain domain, 254df0566a6SJani Nikula intel_wakeref_t wakeref) 255df0566a6SJani Nikula { 256df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, wakeref); 257df0566a6SJani Nikula } 258df0566a6SJani Nikula #else 259e3529346SImre Deak void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 260e3529346SImre Deak enum intel_display_power_domain domain); 261e3529346SImre Deak 262df0566a6SJani Nikula static inline void 263df0566a6SJani Nikula intel_display_power_put(struct drm_i915_private *i915, 264df0566a6SJani Nikula enum intel_display_power_domain domain, 265df0566a6SJani Nikula intel_wakeref_t wakeref) 266df0566a6SJani Nikula { 267df0566a6SJani Nikula intel_display_power_put_unchecked(i915, domain); 268df0566a6SJani Nikula } 269df0566a6SJani Nikula 270df0566a6SJani Nikula static inline void 271df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 272df0566a6SJani Nikula enum intel_display_power_domain domain, 273df0566a6SJani Nikula intel_wakeref_t wakeref) 274df0566a6SJani Nikula { 275df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, -1); 276df0566a6SJani Nikula } 277df0566a6SJani Nikula #endif 278df0566a6SJani Nikula 2796979cb9aSImre Deak void 2806979cb9aSImre Deak intel_display_power_get_in_set(struct drm_i915_private *i915, 2816979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 2826979cb9aSImre Deak enum intel_display_power_domain domain); 2836979cb9aSImre Deak 2846979cb9aSImre Deak bool 2856979cb9aSImre Deak intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, 2866979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 2876979cb9aSImre Deak enum intel_display_power_domain domain); 2886979cb9aSImre Deak 2896979cb9aSImre Deak void 2906979cb9aSImre Deak intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 2916979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 2926979cb9aSImre Deak u64 mask); 2936979cb9aSImre Deak 2946979cb9aSImre Deak static inline void 2956979cb9aSImre Deak intel_display_power_put_all_in_set(struct drm_i915_private *i915, 2966979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set) 2976979cb9aSImre Deak { 2986979cb9aSImre Deak intel_display_power_put_mask_in_set(i915, power_domain_set, power_domain_set->mask); 2996979cb9aSImre Deak } 3006979cb9aSImre Deak 3016abf2fc0SJani Nikula void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m); 3026abf2fc0SJani Nikula 30349f75634SMatt Roper /* 30449f75634SMatt Roper * FIXME: We should probably switch this to a 0-based scheme to be consistent 30549f75634SMatt Roper * with how we now name/number DBUF_CTL instances. 30649f75634SMatt Roper */ 3072570b7e3SStanislav Lisovskiy enum dbuf_slice { 3082570b7e3SStanislav Lisovskiy DBUF_S1, 3092570b7e3SStanislav Lisovskiy DBUF_S2, 3108398024bSMatt Roper DBUF_S3, 3118398024bSMatt Roper DBUF_S4, 3128435576bSStanislav Lisovskiy I915_MAX_DBUF_SLICES 3132570b7e3SStanislav Lisovskiy }; 3142570b7e3SStanislav Lisovskiy 31556f48c1dSVille Syrjälä void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 31656f48c1dSVille Syrjälä u8 req_slices); 31756f48c1dSVille Syrjälä 318df0566a6SJani Nikula #define with_intel_display_power(i915, domain, wf) \ 319df0566a6SJani Nikula for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 320df0566a6SJani Nikula intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 321df0566a6SJani Nikula 322c98e3d15SVille Syrjälä #define with_intel_display_power_if_enabled(i915, domain, wf) \ 323c98e3d15SVille Syrjälä for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \ 324c98e3d15SVille Syrjälä intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 325c98e3d15SVille Syrjälä 326df0566a6SJani Nikula void chv_phy_powergate_lanes(struct intel_encoder *encoder, 327df0566a6SJani Nikula bool override, unsigned int mask); 328df0566a6SJani Nikula bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 329df0566a6SJani Nikula enum dpio_channel ch, bool override); 330df0566a6SJani Nikula 331df0566a6SJani Nikula #endif /* __INTEL_DISPLAY_POWER_H__ */ 332