1df0566a6SJani Nikula /* SPDX-License-Identifier: MIT */ 2df0566a6SJani Nikula /* 3df0566a6SJani Nikula * Copyright © 2019 Intel Corporation 4df0566a6SJani Nikula */ 5df0566a6SJani Nikula 6df0566a6SJani Nikula #ifndef __INTEL_DISPLAY_POWER_H__ 7df0566a6SJani Nikula #define __INTEL_DISPLAY_POWER_H__ 8df0566a6SJani Nikula 9df0566a6SJani Nikula #include "intel_runtime_pm.h" 10df0566a6SJani Nikula 11979e1b32SImre Deak enum aux_ch; 125ed597daSJani Nikula enum dpio_channel; 135ed597daSJani Nikula enum dpio_phy; 14979e1b32SImre Deak enum port; 15df0566a6SJani Nikula struct drm_i915_private; 16de511df7SJani Nikula struct i915_power_well; 17df0566a6SJani Nikula struct intel_encoder; 18df0566a6SJani Nikula 19492c1ae2SImre Deak /* 20492c1ae2SImre Deak * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances 21492c1ae2SImre Deak * consecutive, so that the pipe,transcoder,port -> power domain macros 22492c1ae2SImre Deak * work correctly. 23492c1ae2SImre Deak */ 24df0566a6SJani Nikula enum intel_display_power_domain { 25df0566a6SJani Nikula POWER_DOMAIN_DISPLAY_CORE, 26df0566a6SJani Nikula POWER_DOMAIN_PIPE_A, 27df0566a6SJani Nikula POWER_DOMAIN_PIPE_B, 28df0566a6SJani Nikula POWER_DOMAIN_PIPE_C, 291db27a72SMika Kahola POWER_DOMAIN_PIPE_D, 300ba2661dSImre Deak POWER_DOMAIN_PIPE_PANEL_FITTER_A, 310ba2661dSImre Deak POWER_DOMAIN_PIPE_PANEL_FITTER_B, 320ba2661dSImre Deak POWER_DOMAIN_PIPE_PANEL_FITTER_C, 330ba2661dSImre Deak POWER_DOMAIN_PIPE_PANEL_FITTER_D, 34df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_A, 35df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_B, 36df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_C, 371db27a72SMika Kahola POWER_DOMAIN_TRANSCODER_D, 38df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_EDP, 39df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_A, 40df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_C, 41492c1ae2SImre Deak 42492c1ae2SImre Deak /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */ 43492c1ae2SImre Deak POWER_DOMAIN_TRANSCODER_VDSC_PW2, 44492c1ae2SImre Deak 450ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_A, 460ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_B, 470ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_C, 480ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_D, 490ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_E, 500ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_F, 51c7392718SImre Deak 52*c97bbab0SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC1, 53c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC2, 54c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC3, 55c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC4, 56c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC5, 57c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC6, 58c7392718SImre Deak 59*c97bbab0SImre Deak POWER_DOMAIN_PORT_DDI_LANES_D_XELPD, 60a6922f4aSMatt Roper POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, 61a6922f4aSMatt Roper 620ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_A, 630ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_B, 640ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_C, 650ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_D, 660ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_E, 670ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_F, 68c7392718SImre Deak 69*c97bbab0SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC1, 70c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC2, 71c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC3, 72c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC4, 73c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC5, 74c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC6, 75c7392718SImre Deak 76*c97bbab0SImre Deak POWER_DOMAIN_PORT_DDI_IO_D_XELPD, 77a6922f4aSMatt Roper POWER_DOMAIN_PORT_DDI_IO_E_XELPD, 78a6922f4aSMatt Roper 79df0566a6SJani Nikula POWER_DOMAIN_PORT_DSI, 80df0566a6SJani Nikula POWER_DOMAIN_PORT_CRT, 81df0566a6SJani Nikula POWER_DOMAIN_PORT_OTHER, 82df0566a6SJani Nikula POWER_DOMAIN_VGA, 83615a7724SAnshuman Gupta POWER_DOMAIN_AUDIO_MMIO, 84615a7724SAnshuman Gupta POWER_DOMAIN_AUDIO_PLAYBACK, 85df0566a6SJani Nikula POWER_DOMAIN_AUX_A, 86df0566a6SJani Nikula POWER_DOMAIN_AUX_B, 87df0566a6SJani Nikula POWER_DOMAIN_AUX_C, 88df0566a6SJani Nikula POWER_DOMAIN_AUX_D, 89df0566a6SJani Nikula POWER_DOMAIN_AUX_E, 90df0566a6SJani Nikula POWER_DOMAIN_AUX_F, 91c7392718SImre Deak 92*c97bbab0SImre Deak POWER_DOMAIN_AUX_USBC1, 93c7392718SImre Deak POWER_DOMAIN_AUX_USBC2, 94c7392718SImre Deak POWER_DOMAIN_AUX_USBC3, 95c7392718SImre Deak POWER_DOMAIN_AUX_USBC4, 96c7392718SImre Deak POWER_DOMAIN_AUX_USBC5, 97c7392718SImre Deak POWER_DOMAIN_AUX_USBC6, 98c7392718SImre Deak 99*c97bbab0SImre Deak POWER_DOMAIN_AUX_D_XELPD, 100a6922f4aSMatt Roper POWER_DOMAIN_AUX_E_XELPD, 101a6922f4aSMatt Roper 102df0566a6SJani Nikula POWER_DOMAIN_AUX_IO_A, 1030ba2661dSImre Deak POWER_DOMAIN_AUX_TBT_C, 1040ba2661dSImre Deak POWER_DOMAIN_AUX_TBT_D, 1050ba2661dSImre Deak POWER_DOMAIN_AUX_TBT_E, 1060ba2661dSImre Deak POWER_DOMAIN_AUX_TBT_F, 107c7392718SImre Deak 108*c97bbab0SImre Deak POWER_DOMAIN_AUX_TBT1, 109c7392718SImre Deak POWER_DOMAIN_AUX_TBT2, 110c7392718SImre Deak POWER_DOMAIN_AUX_TBT3, 111c7392718SImre Deak POWER_DOMAIN_AUX_TBT4, 112c7392718SImre Deak POWER_DOMAIN_AUX_TBT5, 113c7392718SImre Deak POWER_DOMAIN_AUX_TBT6, 114c7392718SImre Deak 115df0566a6SJani Nikula POWER_DOMAIN_GMBUS, 116df0566a6SJani Nikula POWER_DOMAIN_MODESET, 117df0566a6SJani Nikula POWER_DOMAIN_GT_IRQ, 118808b79ebSJosé Roberto de Souza POWER_DOMAIN_DC_OFF, 1193c02934bSJosé Roberto de Souza POWER_DOMAIN_TC_COLD_OFF, 120df0566a6SJani Nikula POWER_DOMAIN_INIT, 121df0566a6SJani Nikula 122df0566a6SJani Nikula POWER_DOMAIN_NUM, 123979e1b32SImre Deak POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM, 124df0566a6SJani Nikula }; 125df0566a6SJani Nikula 126df0566a6SJani Nikula #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 127df0566a6SJani Nikula #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 1280ba2661dSImre Deak ((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A) 129df0566a6SJani Nikula #define POWER_DOMAIN_TRANSCODER(tran) \ 130df0566a6SJani Nikula ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 131df0566a6SJani Nikula (tran) + POWER_DOMAIN_TRANSCODER_A) 132df0566a6SJani Nikula 133888a2a63SImre Deak struct intel_power_domain_mask { 134888a2a63SImre Deak DECLARE_BITMAP(bits, POWER_DOMAIN_NUM); 135888a2a63SImre Deak }; 136888a2a63SImre Deak 137df0566a6SJani Nikula struct i915_power_domains { 138df0566a6SJani Nikula /* 139df0566a6SJani Nikula * Power wells needed for initialization at driver init and suspend 140df0566a6SJani Nikula * time are on. They are kept on until after the first modeset. 141df0566a6SJani Nikula */ 142df0566a6SJani Nikula bool initializing; 143df0566a6SJani Nikula bool display_core_suspended; 144df0566a6SJani Nikula int power_well_count; 145df0566a6SJani Nikula 146a0b024edSImre Deak intel_wakeref_t init_wakeref; 14793b916fdSImre Deak intel_wakeref_t disable_wakeref; 148df0566a6SJani Nikula 149df0566a6SJani Nikula struct mutex lock; 150df0566a6SJani Nikula int domain_use_count[POWER_DOMAIN_NUM]; 151df0566a6SJani Nikula 152df0566a6SJani Nikula struct delayed_work async_put_work; 153df0566a6SJani Nikula intel_wakeref_t async_put_wakeref; 154888a2a63SImre Deak struct intel_power_domain_mask async_put_domains[2]; 155df0566a6SJani Nikula 156df0566a6SJani Nikula struct i915_power_well *power_wells; 157df0566a6SJani Nikula }; 158df0566a6SJani Nikula 1596979cb9aSImre Deak struct intel_display_power_domain_set { 160888a2a63SImre Deak struct intel_power_domain_mask mask; 1616979cb9aSImre Deak #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM 1626979cb9aSImre Deak intel_wakeref_t wakerefs[POWER_DOMAIN_NUM]; 1636979cb9aSImre Deak #endif 1646979cb9aSImre Deak }; 1656979cb9aSImre Deak 166888a2a63SImre Deak #define for_each_power_domain(__domain, __mask) \ 167888a2a63SImre Deak for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \ 168888a2a63SImre Deak for_each_if(test_bit((__domain), (__mask)->bits)) 169df0566a6SJani Nikula 170df0566a6SJani Nikula int intel_power_domains_init(struct drm_i915_private *dev_priv); 171df0566a6SJani Nikula void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 172df0566a6SJani Nikula void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 17378dae1acSJanusz Krzysztofik void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 174df0566a6SJani Nikula void intel_power_domains_enable(struct drm_i915_private *dev_priv); 175df0566a6SJani Nikula void intel_power_domains_disable(struct drm_i915_private *dev_priv); 176df0566a6SJani Nikula void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 177df0566a6SJani Nikula enum i915_drm_suspend_mode); 178df0566a6SJani Nikula void intel_power_domains_resume(struct drm_i915_private *dev_priv); 179d946bc44SImre Deak void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv); 180071b68ccSRodrigo Vivi 181071b68ccSRodrigo Vivi void intel_display_power_suspend_late(struct drm_i915_private *i915); 182071b68ccSRodrigo Vivi void intel_display_power_resume_early(struct drm_i915_private *i915); 183071b68ccSRodrigo Vivi void intel_display_power_suspend(struct drm_i915_private *i915); 184071b68ccSRodrigo Vivi void intel_display_power_resume(struct drm_i915_private *i915); 1851c4d821dSAnshuman Gupta void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 1861c4d821dSAnshuman Gupta u32 state); 187df0566a6SJani Nikula 188df0566a6SJani Nikula const char * 1898a84bacbSImre Deak intel_display_power_domain_str(enum intel_display_power_domain domain); 190df0566a6SJani Nikula 191df0566a6SJani Nikula bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 192df0566a6SJani Nikula enum intel_display_power_domain domain); 193df0566a6SJani Nikula bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 194df0566a6SJani Nikula enum intel_display_power_domain domain); 195df0566a6SJani Nikula intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 196df0566a6SJani Nikula enum intel_display_power_domain domain); 197df0566a6SJani Nikula intel_wakeref_t 198df0566a6SJani Nikula intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 199df0566a6SJani Nikula enum intel_display_power_domain domain); 200df0566a6SJani Nikula void __intel_display_power_put_async(struct drm_i915_private *i915, 201df0566a6SJani Nikula enum intel_display_power_domain domain, 202df0566a6SJani Nikula intel_wakeref_t wakeref); 203df0566a6SJani Nikula void intel_display_power_flush_work(struct drm_i915_private *i915); 204df0566a6SJani Nikula #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 205df0566a6SJani Nikula void intel_display_power_put(struct drm_i915_private *dev_priv, 206df0566a6SJani Nikula enum intel_display_power_domain domain, 207df0566a6SJani Nikula intel_wakeref_t wakeref); 208df0566a6SJani Nikula static inline void 209df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 210df0566a6SJani Nikula enum intel_display_power_domain domain, 211df0566a6SJani Nikula intel_wakeref_t wakeref) 212df0566a6SJani Nikula { 213df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, wakeref); 214df0566a6SJani Nikula } 215df0566a6SJani Nikula #else 216e3529346SImre Deak void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 217e3529346SImre Deak enum intel_display_power_domain domain); 218e3529346SImre Deak 219df0566a6SJani Nikula static inline void 220df0566a6SJani Nikula intel_display_power_put(struct drm_i915_private *i915, 221df0566a6SJani Nikula enum intel_display_power_domain domain, 222df0566a6SJani Nikula intel_wakeref_t wakeref) 223df0566a6SJani Nikula { 224df0566a6SJani Nikula intel_display_power_put_unchecked(i915, domain); 225df0566a6SJani Nikula } 226df0566a6SJani Nikula 227df0566a6SJani Nikula static inline void 228df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 229df0566a6SJani Nikula enum intel_display_power_domain domain, 230df0566a6SJani Nikula intel_wakeref_t wakeref) 231df0566a6SJani Nikula { 232df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, -1); 233df0566a6SJani Nikula } 234df0566a6SJani Nikula #endif 235df0566a6SJani Nikula 2366979cb9aSImre Deak void 2376979cb9aSImre Deak intel_display_power_get_in_set(struct drm_i915_private *i915, 2386979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 2396979cb9aSImre Deak enum intel_display_power_domain domain); 2406979cb9aSImre Deak 2416979cb9aSImre Deak bool 2426979cb9aSImre Deak intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, 2436979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 2446979cb9aSImre Deak enum intel_display_power_domain domain); 2456979cb9aSImre Deak 2466979cb9aSImre Deak void 2476979cb9aSImre Deak intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 2486979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 249888a2a63SImre Deak struct intel_power_domain_mask *mask); 2506979cb9aSImre Deak 2516979cb9aSImre Deak static inline void 2526979cb9aSImre Deak intel_display_power_put_all_in_set(struct drm_i915_private *i915, 2536979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set) 2546979cb9aSImre Deak { 255888a2a63SImre Deak intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask); 2566979cb9aSImre Deak } 2576979cb9aSImre Deak 2586abf2fc0SJani Nikula void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m); 2596abf2fc0SJani Nikula 260979e1b32SImre Deak enum intel_display_power_domain 261979e1b32SImre Deak intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port); 262979e1b32SImre Deak enum intel_display_power_domain 263979e1b32SImre Deak intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port); 264979e1b32SImre Deak enum intel_display_power_domain 265979e1b32SImre Deak intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch); 266979e1b32SImre Deak enum intel_display_power_domain 267979e1b32SImre Deak intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch); 268979e1b32SImre Deak 26949f75634SMatt Roper /* 27049f75634SMatt Roper * FIXME: We should probably switch this to a 0-based scheme to be consistent 27149f75634SMatt Roper * with how we now name/number DBUF_CTL instances. 27249f75634SMatt Roper */ 2732570b7e3SStanislav Lisovskiy enum dbuf_slice { 2742570b7e3SStanislav Lisovskiy DBUF_S1, 2752570b7e3SStanislav Lisovskiy DBUF_S2, 2768398024bSMatt Roper DBUF_S3, 2778398024bSMatt Roper DBUF_S4, 2788435576bSStanislav Lisovskiy I915_MAX_DBUF_SLICES 2792570b7e3SStanislav Lisovskiy }; 2802570b7e3SStanislav Lisovskiy 28156f48c1dSVille Syrjälä void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 28256f48c1dSVille Syrjälä u8 req_slices); 28356f48c1dSVille Syrjälä 284df0566a6SJani Nikula #define with_intel_display_power(i915, domain, wf) \ 285df0566a6SJani Nikula for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 286df0566a6SJani Nikula intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 287df0566a6SJani Nikula 288c98e3d15SVille Syrjälä #define with_intel_display_power_if_enabled(i915, domain, wf) \ 289c98e3d15SVille Syrjälä for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \ 290c98e3d15SVille Syrjälä intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 291c98e3d15SVille Syrjälä 292df0566a6SJani Nikula #endif /* __INTEL_DISPLAY_POWER_H__ */ 293