1df0566a6SJani Nikula /* SPDX-License-Identifier: MIT */ 2df0566a6SJani Nikula /* 3df0566a6SJani Nikula * Copyright © 2019 Intel Corporation 4df0566a6SJani Nikula */ 5df0566a6SJani Nikula 6df0566a6SJani Nikula #ifndef __INTEL_DISPLAY_POWER_H__ 7df0566a6SJani Nikula #define __INTEL_DISPLAY_POWER_H__ 8df0566a6SJani Nikula 950ae1a1cSJani Nikula #include "intel_wakeref.h" 10df0566a6SJani Nikula 11979e1b32SImre Deak enum aux_ch; 125ed597daSJani Nikula enum dpio_channel; 135ed597daSJani Nikula enum dpio_phy; 1450ae1a1cSJani Nikula enum i915_drm_suspend_mode; 15979e1b32SImre Deak enum port; 16df0566a6SJani Nikula struct drm_i915_private; 17de511df7SJani Nikula struct i915_power_well; 18df0566a6SJani Nikula struct intel_encoder; 19df0566a6SJani Nikula 20492c1ae2SImre Deak /* 21492c1ae2SImre Deak * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances 22492c1ae2SImre Deak * consecutive, so that the pipe,transcoder,port -> power domain macros 23492c1ae2SImre Deak * work correctly. 24492c1ae2SImre Deak */ 25df0566a6SJani Nikula enum intel_display_power_domain { 26df0566a6SJani Nikula POWER_DOMAIN_DISPLAY_CORE, 27df0566a6SJani Nikula POWER_DOMAIN_PIPE_A, 28df0566a6SJani Nikula POWER_DOMAIN_PIPE_B, 29df0566a6SJani Nikula POWER_DOMAIN_PIPE_C, 301db27a72SMika Kahola POWER_DOMAIN_PIPE_D, 310ba2661dSImre Deak POWER_DOMAIN_PIPE_PANEL_FITTER_A, 320ba2661dSImre Deak POWER_DOMAIN_PIPE_PANEL_FITTER_B, 330ba2661dSImre Deak POWER_DOMAIN_PIPE_PANEL_FITTER_C, 340ba2661dSImre Deak POWER_DOMAIN_PIPE_PANEL_FITTER_D, 35df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_A, 36df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_B, 37df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_C, 381db27a72SMika Kahola POWER_DOMAIN_TRANSCODER_D, 39df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_EDP, 40df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_A, 41df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_C, 42492c1ae2SImre Deak 43492c1ae2SImre Deak /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */ 44492c1ae2SImre Deak POWER_DOMAIN_TRANSCODER_VDSC_PW2, 45492c1ae2SImre Deak 460ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_A, 470ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_B, 480ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_C, 490ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_D, 500ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_E, 510ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_F, 52c7392718SImre Deak 53c97bbab0SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC1, 54c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC2, 55c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC3, 56c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC4, 57c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC5, 58c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC6, 59c7392718SImre Deak 600ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_A, 610ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_B, 620ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_C, 630ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_D, 640ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_E, 650ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_F, 66c7392718SImre Deak 67c97bbab0SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC1, 68c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC2, 69c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC3, 70c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC4, 71c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC5, 72c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC6, 73c7392718SImre Deak 74df0566a6SJani Nikula POWER_DOMAIN_PORT_DSI, 75df0566a6SJani Nikula POWER_DOMAIN_PORT_CRT, 76df0566a6SJani Nikula POWER_DOMAIN_PORT_OTHER, 77df0566a6SJani Nikula POWER_DOMAIN_VGA, 78615a7724SAnshuman Gupta POWER_DOMAIN_AUDIO_MMIO, 79615a7724SAnshuman Gupta POWER_DOMAIN_AUDIO_PLAYBACK, 805c30cfcdSImre Deak 815c30cfcdSImre Deak POWER_DOMAIN_AUX_IO_A, 82f645cbdaSImre Deak POWER_DOMAIN_AUX_IO_B, 83f645cbdaSImre Deak POWER_DOMAIN_AUX_IO_C, 84f645cbdaSImre Deak POWER_DOMAIN_AUX_IO_D, 85f645cbdaSImre Deak POWER_DOMAIN_AUX_IO_E, 86f645cbdaSImre Deak POWER_DOMAIN_AUX_IO_F, 875c30cfcdSImre Deak 88df0566a6SJani Nikula POWER_DOMAIN_AUX_A, 89df0566a6SJani Nikula POWER_DOMAIN_AUX_B, 90df0566a6SJani Nikula POWER_DOMAIN_AUX_C, 91df0566a6SJani Nikula POWER_DOMAIN_AUX_D, 92df0566a6SJani Nikula POWER_DOMAIN_AUX_E, 93df0566a6SJani Nikula POWER_DOMAIN_AUX_F, 94c7392718SImre Deak 95c97bbab0SImre Deak POWER_DOMAIN_AUX_USBC1, 96c7392718SImre Deak POWER_DOMAIN_AUX_USBC2, 97c7392718SImre Deak POWER_DOMAIN_AUX_USBC3, 98c7392718SImre Deak POWER_DOMAIN_AUX_USBC4, 99c7392718SImre Deak POWER_DOMAIN_AUX_USBC5, 100c7392718SImre Deak POWER_DOMAIN_AUX_USBC6, 101c7392718SImre Deak 102c97bbab0SImre Deak POWER_DOMAIN_AUX_TBT1, 103c7392718SImre Deak POWER_DOMAIN_AUX_TBT2, 104c7392718SImre Deak POWER_DOMAIN_AUX_TBT3, 105c7392718SImre Deak POWER_DOMAIN_AUX_TBT4, 106c7392718SImre Deak POWER_DOMAIN_AUX_TBT5, 107c7392718SImre Deak POWER_DOMAIN_AUX_TBT6, 108c7392718SImre Deak 109df0566a6SJani Nikula POWER_DOMAIN_GMBUS, 110df0566a6SJani Nikula POWER_DOMAIN_MODESET, 111df0566a6SJani Nikula POWER_DOMAIN_GT_IRQ, 112808b79ebSJosé Roberto de Souza POWER_DOMAIN_DC_OFF, 1133c02934bSJosé Roberto de Souza POWER_DOMAIN_TC_COLD_OFF, 114df0566a6SJani Nikula POWER_DOMAIN_INIT, 115df0566a6SJani Nikula 116df0566a6SJani Nikula POWER_DOMAIN_NUM, 117979e1b32SImre Deak POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM, 118df0566a6SJani Nikula }; 119df0566a6SJani Nikula 120df0566a6SJani Nikula #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 121df0566a6SJani Nikula #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 1220ba2661dSImre Deak ((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A) 123df0566a6SJani Nikula #define POWER_DOMAIN_TRANSCODER(tran) \ 124df0566a6SJani Nikula ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 125df0566a6SJani Nikula (tran) + POWER_DOMAIN_TRANSCODER_A) 126df0566a6SJani Nikula 127888a2a63SImre Deak struct intel_power_domain_mask { 128888a2a63SImre Deak DECLARE_BITMAP(bits, POWER_DOMAIN_NUM); 129888a2a63SImre Deak }; 130888a2a63SImre Deak 131df0566a6SJani Nikula struct i915_power_domains { 132df0566a6SJani Nikula /* 133df0566a6SJani Nikula * Power wells needed for initialization at driver init and suspend 134df0566a6SJani Nikula * time are on. They are kept on until after the first modeset. 135df0566a6SJani Nikula */ 136df0566a6SJani Nikula bool initializing; 137df0566a6SJani Nikula bool display_core_suspended; 138df0566a6SJani Nikula int power_well_count; 139df0566a6SJani Nikula 140825f0de2SJani Nikula u32 dc_state; 141825f0de2SJani Nikula u32 target_dc_state; 142825f0de2SJani Nikula u32 allowed_dc_mask; 143825f0de2SJani Nikula 144a0b024edSImre Deak intel_wakeref_t init_wakeref; 14593b916fdSImre Deak intel_wakeref_t disable_wakeref; 146df0566a6SJani Nikula 147df0566a6SJani Nikula struct mutex lock; 148df0566a6SJani Nikula int domain_use_count[POWER_DOMAIN_NUM]; 149df0566a6SJani Nikula 150df0566a6SJani Nikula struct delayed_work async_put_work; 151df0566a6SJani Nikula intel_wakeref_t async_put_wakeref; 152888a2a63SImre Deak struct intel_power_domain_mask async_put_domains[2]; 153df0566a6SJani Nikula 154df0566a6SJani Nikula struct i915_power_well *power_wells; 155df0566a6SJani Nikula }; 156df0566a6SJani Nikula 1576979cb9aSImre Deak struct intel_display_power_domain_set { 158888a2a63SImre Deak struct intel_power_domain_mask mask; 1596979cb9aSImre Deak #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM 1606979cb9aSImre Deak intel_wakeref_t wakerefs[POWER_DOMAIN_NUM]; 1616979cb9aSImre Deak #endif 1626979cb9aSImre Deak }; 1636979cb9aSImre Deak 164888a2a63SImre Deak #define for_each_power_domain(__domain, __mask) \ 165888a2a63SImre Deak for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \ 166888a2a63SImre Deak for_each_if(test_bit((__domain), (__mask)->bits)) 167df0566a6SJani Nikula 168df0566a6SJani Nikula int intel_power_domains_init(struct drm_i915_private *dev_priv); 169df0566a6SJani Nikula void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 170df0566a6SJani Nikula void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 17178dae1acSJanusz Krzysztofik void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 172df0566a6SJani Nikula void intel_power_domains_enable(struct drm_i915_private *dev_priv); 173df0566a6SJani Nikula void intel_power_domains_disable(struct drm_i915_private *dev_priv); 174*c7b5abd3SMaarten Lankhorst void intel_power_domains_suspend(struct drm_i915_private *dev_priv, bool s2idle); 175df0566a6SJani Nikula void intel_power_domains_resume(struct drm_i915_private *dev_priv); 176d946bc44SImre Deak void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv); 177071b68ccSRodrigo Vivi 178071b68ccSRodrigo Vivi void intel_display_power_suspend_late(struct drm_i915_private *i915); 179071b68ccSRodrigo Vivi void intel_display_power_resume_early(struct drm_i915_private *i915); 180071b68ccSRodrigo Vivi void intel_display_power_suspend(struct drm_i915_private *i915); 181071b68ccSRodrigo Vivi void intel_display_power_resume(struct drm_i915_private *i915); 1821c4d821dSAnshuman Gupta void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 1831c4d821dSAnshuman Gupta u32 state); 184df0566a6SJani Nikula 185df0566a6SJani Nikula const char * 1868a84bacbSImre Deak intel_display_power_domain_str(enum intel_display_power_domain domain); 187df0566a6SJani Nikula 188df0566a6SJani Nikula bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 189df0566a6SJani Nikula enum intel_display_power_domain domain); 190df0566a6SJani Nikula bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 191df0566a6SJani Nikula enum intel_display_power_domain domain); 192df0566a6SJani Nikula intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 193df0566a6SJani Nikula enum intel_display_power_domain domain); 194df0566a6SJani Nikula intel_wakeref_t 195df0566a6SJani Nikula intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 196df0566a6SJani Nikula enum intel_display_power_domain domain); 197df0566a6SJani Nikula void __intel_display_power_put_async(struct drm_i915_private *i915, 198df0566a6SJani Nikula enum intel_display_power_domain domain, 199df0566a6SJani Nikula intel_wakeref_t wakeref); 200df0566a6SJani Nikula void intel_display_power_flush_work(struct drm_i915_private *i915); 201df0566a6SJani Nikula #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 202df0566a6SJani Nikula void intel_display_power_put(struct drm_i915_private *dev_priv, 203df0566a6SJani Nikula enum intel_display_power_domain domain, 204df0566a6SJani Nikula intel_wakeref_t wakeref); 205df0566a6SJani Nikula static inline void 206df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 207df0566a6SJani Nikula enum intel_display_power_domain domain, 208df0566a6SJani Nikula intel_wakeref_t wakeref) 209df0566a6SJani Nikula { 210df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, wakeref); 211df0566a6SJani Nikula } 212df0566a6SJani Nikula #else 213e3529346SImre Deak void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 214e3529346SImre Deak enum intel_display_power_domain domain); 215e3529346SImre Deak 216df0566a6SJani Nikula static inline void 217df0566a6SJani Nikula intel_display_power_put(struct drm_i915_private *i915, 218df0566a6SJani Nikula enum intel_display_power_domain domain, 219df0566a6SJani Nikula intel_wakeref_t wakeref) 220df0566a6SJani Nikula { 221df0566a6SJani Nikula intel_display_power_put_unchecked(i915, domain); 222df0566a6SJani Nikula } 223df0566a6SJani Nikula 224df0566a6SJani Nikula static inline void 225df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 226df0566a6SJani Nikula enum intel_display_power_domain domain, 227df0566a6SJani Nikula intel_wakeref_t wakeref) 228df0566a6SJani Nikula { 229df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, -1); 230df0566a6SJani Nikula } 231df0566a6SJani Nikula #endif 232df0566a6SJani Nikula 2336979cb9aSImre Deak void 2346979cb9aSImre Deak intel_display_power_get_in_set(struct drm_i915_private *i915, 2356979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 2366979cb9aSImre Deak enum intel_display_power_domain domain); 2376979cb9aSImre Deak 2386979cb9aSImre Deak bool 2396979cb9aSImre Deak intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, 2406979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 2416979cb9aSImre Deak enum intel_display_power_domain domain); 2426979cb9aSImre Deak 2436979cb9aSImre Deak void 2446979cb9aSImre Deak intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 2456979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 246888a2a63SImre Deak struct intel_power_domain_mask *mask); 2476979cb9aSImre Deak 2486979cb9aSImre Deak static inline void 2496979cb9aSImre Deak intel_display_power_put_all_in_set(struct drm_i915_private *i915, 2506979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set) 2516979cb9aSImre Deak { 252888a2a63SImre Deak intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask); 2536979cb9aSImre Deak } 2546979cb9aSImre Deak 2556abf2fc0SJani Nikula void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m); 2566abf2fc0SJani Nikula 257979e1b32SImre Deak enum intel_display_power_domain 258979e1b32SImre Deak intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port); 259979e1b32SImre Deak enum intel_display_power_domain 260979e1b32SImre Deak intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port); 261979e1b32SImre Deak enum intel_display_power_domain 262f645cbdaSImre Deak intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch); 263f645cbdaSImre Deak enum intel_display_power_domain 264979e1b32SImre Deak intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch); 265979e1b32SImre Deak enum intel_display_power_domain 266979e1b32SImre Deak intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch); 267979e1b32SImre Deak 26849f75634SMatt Roper /* 26949f75634SMatt Roper * FIXME: We should probably switch this to a 0-based scheme to be consistent 27049f75634SMatt Roper * with how we now name/number DBUF_CTL instances. 27149f75634SMatt Roper */ 2722570b7e3SStanislav Lisovskiy enum dbuf_slice { 2732570b7e3SStanislav Lisovskiy DBUF_S1, 2742570b7e3SStanislav Lisovskiy DBUF_S2, 2758398024bSMatt Roper DBUF_S3, 2768398024bSMatt Roper DBUF_S4, 2778435576bSStanislav Lisovskiy I915_MAX_DBUF_SLICES 2782570b7e3SStanislav Lisovskiy }; 2792570b7e3SStanislav Lisovskiy 28056f48c1dSVille Syrjälä void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 28156f48c1dSVille Syrjälä u8 req_slices); 28256f48c1dSVille Syrjälä 283df0566a6SJani Nikula #define with_intel_display_power(i915, domain, wf) \ 284df0566a6SJani Nikula for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 285df0566a6SJani Nikula intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 286df0566a6SJani Nikula 287c98e3d15SVille Syrjälä #define with_intel_display_power_if_enabled(i915, domain, wf) \ 288c98e3d15SVille Syrjälä for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \ 289c98e3d15SVille Syrjälä intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 290c98e3d15SVille Syrjälä 291df0566a6SJani Nikula #endif /* __INTEL_DISPLAY_POWER_H__ */ 292