1df0566a6SJani Nikula /* SPDX-License-Identifier: MIT */ 2df0566a6SJani Nikula /* 3df0566a6SJani Nikula * Copyright © 2019 Intel Corporation 4df0566a6SJani Nikula */ 5df0566a6SJani Nikula 6df0566a6SJani Nikula #ifndef __INTEL_DISPLAY_POWER_H__ 7df0566a6SJani Nikula #define __INTEL_DISPLAY_POWER_H__ 8df0566a6SJani Nikula 9df0566a6SJani Nikula #include "intel_display.h" 10df0566a6SJani Nikula #include "intel_runtime_pm.h" 11df0566a6SJani Nikula #include "i915_reg.h" 12df0566a6SJani Nikula 13df0566a6SJani Nikula struct drm_i915_private; 14df0566a6SJani Nikula struct intel_encoder; 15df0566a6SJani Nikula 16df0566a6SJani Nikula enum intel_display_power_domain { 17df0566a6SJani Nikula POWER_DOMAIN_DISPLAY_CORE, 18df0566a6SJani Nikula POWER_DOMAIN_PIPE_A, 19df0566a6SJani Nikula POWER_DOMAIN_PIPE_B, 20df0566a6SJani Nikula POWER_DOMAIN_PIPE_C, 211db27a72SMika Kahola POWER_DOMAIN_PIPE_D, 22df0566a6SJani Nikula POWER_DOMAIN_PIPE_A_PANEL_FITTER, 23df0566a6SJani Nikula POWER_DOMAIN_PIPE_B_PANEL_FITTER, 24df0566a6SJani Nikula POWER_DOMAIN_PIPE_C_PANEL_FITTER, 251db27a72SMika Kahola POWER_DOMAIN_PIPE_D_PANEL_FITTER, 26df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_A, 27df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_B, 28df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_C, 291db27a72SMika Kahola POWER_DOMAIN_TRANSCODER_D, 30df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_EDP, 31f7fd2373SJani Nikula /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */ 32276199e6SJosé Roberto de Souza POWER_DOMAIN_TRANSCODER_VDSC_PW2, 33df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_A, 34df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_C, 35df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_A_LANES, 36df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_B_LANES, 37df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_C_LANES, 38df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_D_LANES, 39df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_E_LANES, 40df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_F_LANES, 418a84bacbSImre Deak POWER_DOMAIN_PORT_DDI_G_LANES, 428a84bacbSImre Deak POWER_DOMAIN_PORT_DDI_H_LANES, 438a84bacbSImre Deak POWER_DOMAIN_PORT_DDI_I_LANES, 44*c7392718SImre Deak 45*c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_D_LANES, /* tgl+ */ 46*c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC2, 47*c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC3, 48*c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC4, 49*c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC5, 50*c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC6, 51*c7392718SImre Deak 52df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_A_IO, 53df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_B_IO, 54df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_C_IO, 55df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_D_IO, 56df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_E_IO, 57df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_F_IO, 58656409bbSImre Deak POWER_DOMAIN_PORT_DDI_G_IO, 59656409bbSImre Deak POWER_DOMAIN_PORT_DDI_H_IO, 60656409bbSImre Deak POWER_DOMAIN_PORT_DDI_I_IO, 61*c7392718SImre Deak 62*c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_D_IO, /* tgl+ */ 63*c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC2, 64*c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC3, 65*c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC4, 66*c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC5, 67*c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC6, 68*c7392718SImre Deak 69df0566a6SJani Nikula POWER_DOMAIN_PORT_DSI, 70df0566a6SJani Nikula POWER_DOMAIN_PORT_CRT, 71df0566a6SJani Nikula POWER_DOMAIN_PORT_OTHER, 72df0566a6SJani Nikula POWER_DOMAIN_VGA, 73df0566a6SJani Nikula POWER_DOMAIN_AUDIO, 74df0566a6SJani Nikula POWER_DOMAIN_AUX_A, 75df0566a6SJani Nikula POWER_DOMAIN_AUX_B, 76df0566a6SJani Nikula POWER_DOMAIN_AUX_C, 77df0566a6SJani Nikula POWER_DOMAIN_AUX_D, 78df0566a6SJani Nikula POWER_DOMAIN_AUX_E, 79df0566a6SJani Nikula POWER_DOMAIN_AUX_F, 808a84bacbSImre Deak POWER_DOMAIN_AUX_G, 818a84bacbSImre Deak POWER_DOMAIN_AUX_H, 828a84bacbSImre Deak POWER_DOMAIN_AUX_I, 83*c7392718SImre Deak 84*c7392718SImre Deak POWER_DOMAIN_AUX_USBC1 = POWER_DOMAIN_AUX_D, /* tgl+ */ 85*c7392718SImre Deak POWER_DOMAIN_AUX_USBC2, 86*c7392718SImre Deak POWER_DOMAIN_AUX_USBC3, 87*c7392718SImre Deak POWER_DOMAIN_AUX_USBC4, 88*c7392718SImre Deak POWER_DOMAIN_AUX_USBC5, 89*c7392718SImre Deak POWER_DOMAIN_AUX_USBC6, 90*c7392718SImre Deak 91df0566a6SJani Nikula POWER_DOMAIN_AUX_IO_A, 928a84bacbSImre Deak POWER_DOMAIN_AUX_C_TBT, 938a84bacbSImre Deak POWER_DOMAIN_AUX_D_TBT, 948a84bacbSImre Deak POWER_DOMAIN_AUX_E_TBT, 958a84bacbSImre Deak POWER_DOMAIN_AUX_F_TBT, 968a84bacbSImre Deak POWER_DOMAIN_AUX_G_TBT, 978a84bacbSImre Deak POWER_DOMAIN_AUX_H_TBT, 988a84bacbSImre Deak POWER_DOMAIN_AUX_I_TBT, 99*c7392718SImre Deak 100*c7392718SImre Deak POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_D_TBT, /* tgl+ */ 101*c7392718SImre Deak POWER_DOMAIN_AUX_TBT2, 102*c7392718SImre Deak POWER_DOMAIN_AUX_TBT3, 103*c7392718SImre Deak POWER_DOMAIN_AUX_TBT4, 104*c7392718SImre Deak POWER_DOMAIN_AUX_TBT5, 105*c7392718SImre Deak POWER_DOMAIN_AUX_TBT6, 106*c7392718SImre Deak 107df0566a6SJani Nikula POWER_DOMAIN_GMBUS, 108df0566a6SJani Nikula POWER_DOMAIN_MODESET, 109df0566a6SJani Nikula POWER_DOMAIN_GT_IRQ, 110eef037eaSVivek Kasireddy POWER_DOMAIN_DPLL_DC_OFF, 1113c02934bSJosé Roberto de Souza POWER_DOMAIN_TC_COLD_OFF, 112df0566a6SJani Nikula POWER_DOMAIN_INIT, 113df0566a6SJani Nikula 114df0566a6SJani Nikula POWER_DOMAIN_NUM, 115df0566a6SJani Nikula }; 116df0566a6SJani Nikula 1173e5d0641SDaniele Ceraolo Spurio /* 1183e5d0641SDaniele Ceraolo Spurio * i915_power_well_id: 1193e5d0641SDaniele Ceraolo Spurio * 1203e5d0641SDaniele Ceraolo Spurio * IDs used to look up power wells. Power wells accessed directly bypassing 1213e5d0641SDaniele Ceraolo Spurio * the power domains framework must be assigned a unique ID. The rest of power 1223e5d0641SDaniele Ceraolo Spurio * wells must be assigned DISP_PW_ID_NONE. 1233e5d0641SDaniele Ceraolo Spurio */ 1243e5d0641SDaniele Ceraolo Spurio enum i915_power_well_id { 1253e5d0641SDaniele Ceraolo Spurio DISP_PW_ID_NONE, 1263e5d0641SDaniele Ceraolo Spurio 1273e5d0641SDaniele Ceraolo Spurio VLV_DISP_PW_DISP2D, 1283e5d0641SDaniele Ceraolo Spurio BXT_DISP_PW_DPIO_CMN_A, 1293e5d0641SDaniele Ceraolo Spurio VLV_DISP_PW_DPIO_CMN_BC, 1303e5d0641SDaniele Ceraolo Spurio GLK_DISP_PW_DPIO_CMN_C, 1313e5d0641SDaniele Ceraolo Spurio CHV_DISP_PW_DPIO_CMN_D, 1323e5d0641SDaniele Ceraolo Spurio HSW_DISP_PW_GLOBAL, 1333e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_MISC_IO, 1343e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_1, 1353e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_2, 13662277f33SLucas De Marchi CNL_DISP_PW_DDI_F_IO, 13762277f33SLucas De Marchi CNL_DISP_PW_DDI_F_AUX, 138fc4a8c16SAnshuman Gupta ICL_DISP_PW_3, 1394645e906SAnshuman Gupta SKL_DISP_DC_OFF, 140240abb3cSLucas De Marchi TGL_DISP_PW_TC_COLD_OFF, 1413e5d0641SDaniele Ceraolo Spurio }; 1423e5d0641SDaniele Ceraolo Spurio 143df0566a6SJani Nikula #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 144df0566a6SJani Nikula #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 145df0566a6SJani Nikula ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 146df0566a6SJani Nikula #define POWER_DOMAIN_TRANSCODER(tran) \ 147df0566a6SJani Nikula ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 148df0566a6SJani Nikula (tran) + POWER_DOMAIN_TRANSCODER_A) 149df0566a6SJani Nikula 150df0566a6SJani Nikula struct i915_power_well; 151df0566a6SJani Nikula 152df0566a6SJani Nikula struct i915_power_well_ops { 153df0566a6SJani Nikula /* 154df0566a6SJani Nikula * Synchronize the well's hw state to match the current sw state, for 155df0566a6SJani Nikula * example enable/disable it based on the current refcount. Called 156df0566a6SJani Nikula * during driver init and resume time, possibly after first calling 157df0566a6SJani Nikula * the enable/disable handlers. 158df0566a6SJani Nikula */ 159df0566a6SJani Nikula void (*sync_hw)(struct drm_i915_private *dev_priv, 160df0566a6SJani Nikula struct i915_power_well *power_well); 161df0566a6SJani Nikula /* 162df0566a6SJani Nikula * Enable the well and resources that depend on it (for example 163df0566a6SJani Nikula * interrupts located on the well). Called after the 0->1 refcount 164df0566a6SJani Nikula * transition. 165df0566a6SJani Nikula */ 166df0566a6SJani Nikula void (*enable)(struct drm_i915_private *dev_priv, 167df0566a6SJani Nikula struct i915_power_well *power_well); 168df0566a6SJani Nikula /* 169df0566a6SJani Nikula * Disable the well and resources that depend on it. Called after 170df0566a6SJani Nikula * the 1->0 refcount transition. 171df0566a6SJani Nikula */ 172df0566a6SJani Nikula void (*disable)(struct drm_i915_private *dev_priv, 173df0566a6SJani Nikula struct i915_power_well *power_well); 174df0566a6SJani Nikula /* Returns the hw enabled state. */ 175df0566a6SJani Nikula bool (*is_enabled)(struct drm_i915_private *dev_priv, 176df0566a6SJani Nikula struct i915_power_well *power_well); 177df0566a6SJani Nikula }; 178df0566a6SJani Nikula 179df0566a6SJani Nikula struct i915_power_well_regs { 180df0566a6SJani Nikula i915_reg_t bios; 181df0566a6SJani Nikula i915_reg_t driver; 182df0566a6SJani Nikula i915_reg_t kvmr; 183df0566a6SJani Nikula i915_reg_t debug; 184df0566a6SJani Nikula }; 185df0566a6SJani Nikula 186df0566a6SJani Nikula /* Power well structure for haswell */ 187df0566a6SJani Nikula struct i915_power_well_desc { 188df0566a6SJani Nikula const char *name; 189df0566a6SJani Nikula bool always_on; 190df0566a6SJani Nikula u64 domains; 191df0566a6SJani Nikula /* unique identifier for this power well */ 192df0566a6SJani Nikula enum i915_power_well_id id; 193df0566a6SJani Nikula /* 194df0566a6SJani Nikula * Arbitraty data associated with this power well. Platform and power 195df0566a6SJani Nikula * well specific. 196df0566a6SJani Nikula */ 197df0566a6SJani Nikula union { 198df0566a6SJani Nikula struct { 199df0566a6SJani Nikula /* 200df0566a6SJani Nikula * request/status flag index in the PUNIT power well 201df0566a6SJani Nikula * control/status registers. 202df0566a6SJani Nikula */ 203df0566a6SJani Nikula u8 idx; 204df0566a6SJani Nikula } vlv; 205df0566a6SJani Nikula struct { 206df0566a6SJani Nikula enum dpio_phy phy; 207df0566a6SJani Nikula } bxt; 208df0566a6SJani Nikula struct { 209df0566a6SJani Nikula const struct i915_power_well_regs *regs; 210df0566a6SJani Nikula /* 211df0566a6SJani Nikula * request/status flag index in the power well 212df0566a6SJani Nikula * constrol/status registers. 213df0566a6SJani Nikula */ 214df0566a6SJani Nikula u8 idx; 215df0566a6SJani Nikula /* Mask of pipes whose IRQ logic is backed by the pw */ 216df0566a6SJani Nikula u8 irq_pipe_mask; 217df0566a6SJani Nikula /* The pw is backing the VGA functionality */ 218df0566a6SJani Nikula bool has_vga:1; 219df0566a6SJani Nikula bool has_fuses:1; 220df0566a6SJani Nikula /* 221df0566a6SJani Nikula * The pw is for an ICL+ TypeC PHY port in 222df0566a6SJani Nikula * Thunderbolt mode. 223df0566a6SJani Nikula */ 224df0566a6SJani Nikula bool is_tc_tbt:1; 225df0566a6SJani Nikula } hsw; 226df0566a6SJani Nikula }; 227df0566a6SJani Nikula const struct i915_power_well_ops *ops; 228df0566a6SJani Nikula }; 229df0566a6SJani Nikula 230df0566a6SJani Nikula struct i915_power_well { 231df0566a6SJani Nikula const struct i915_power_well_desc *desc; 232df0566a6SJani Nikula /* power well enable/disable usage count */ 233df0566a6SJani Nikula int count; 234df0566a6SJani Nikula /* cached hw enabled state */ 235df0566a6SJani Nikula bool hw_enabled; 236df0566a6SJani Nikula }; 237df0566a6SJani Nikula 238df0566a6SJani Nikula struct i915_power_domains { 239df0566a6SJani Nikula /* 240df0566a6SJani Nikula * Power wells needed for initialization at driver init and suspend 241df0566a6SJani Nikula * time are on. They are kept on until after the first modeset. 242df0566a6SJani Nikula */ 243df0566a6SJani Nikula bool initializing; 244df0566a6SJani Nikula bool display_core_suspended; 245df0566a6SJani Nikula int power_well_count; 246df0566a6SJani Nikula 247a0b024edSImre Deak intel_wakeref_t init_wakeref; 24893b916fdSImre Deak intel_wakeref_t disable_wakeref; 249df0566a6SJani Nikula 250df0566a6SJani Nikula struct mutex lock; 251df0566a6SJani Nikula int domain_use_count[POWER_DOMAIN_NUM]; 252df0566a6SJani Nikula 253df0566a6SJani Nikula struct delayed_work async_put_work; 254df0566a6SJani Nikula intel_wakeref_t async_put_wakeref; 255df0566a6SJani Nikula u64 async_put_domains[2]; 256df0566a6SJani Nikula 257df0566a6SJani Nikula struct i915_power_well *power_wells; 258df0566a6SJani Nikula }; 259df0566a6SJani Nikula 2606979cb9aSImre Deak struct intel_display_power_domain_set { 2616979cb9aSImre Deak u64 mask; 2626979cb9aSImre Deak #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM 2636979cb9aSImre Deak intel_wakeref_t wakerefs[POWER_DOMAIN_NUM]; 2646979cb9aSImre Deak #endif 2656979cb9aSImre Deak }; 2666979cb9aSImre Deak 267df0566a6SJani Nikula #define for_each_power_domain(domain, mask) \ 268df0566a6SJani Nikula for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 269df0566a6SJani Nikula for_each_if(BIT_ULL(domain) & (mask)) 270df0566a6SJani Nikula 271df0566a6SJani Nikula #define for_each_power_well(__dev_priv, __power_well) \ 272df0566a6SJani Nikula for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ 273df0566a6SJani Nikula (__power_well) - (__dev_priv)->power_domains.power_wells < \ 274df0566a6SJani Nikula (__dev_priv)->power_domains.power_well_count; \ 275df0566a6SJani Nikula (__power_well)++) 276df0566a6SJani Nikula 277df0566a6SJani Nikula #define for_each_power_well_reverse(__dev_priv, __power_well) \ 278df0566a6SJani Nikula for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ 279df0566a6SJani Nikula (__dev_priv)->power_domains.power_well_count - 1; \ 280df0566a6SJani Nikula (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ 281df0566a6SJani Nikula (__power_well)--) 282df0566a6SJani Nikula 283df0566a6SJani Nikula #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ 284df0566a6SJani Nikula for_each_power_well(__dev_priv, __power_well) \ 285df0566a6SJani Nikula for_each_if((__power_well)->desc->domains & (__domain_mask)) 286df0566a6SJani Nikula 287df0566a6SJani Nikula #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ 288df0566a6SJani Nikula for_each_power_well_reverse(__dev_priv, __power_well) \ 289df0566a6SJani Nikula for_each_if((__power_well)->desc->domains & (__domain_mask)) 290df0566a6SJani Nikula 291df0566a6SJani Nikula int intel_power_domains_init(struct drm_i915_private *dev_priv); 292df0566a6SJani Nikula void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 293df0566a6SJani Nikula void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 29478dae1acSJanusz Krzysztofik void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 295df0566a6SJani Nikula void intel_power_domains_enable(struct drm_i915_private *dev_priv); 296df0566a6SJani Nikula void intel_power_domains_disable(struct drm_i915_private *dev_priv); 297df0566a6SJani Nikula void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 298df0566a6SJani Nikula enum i915_drm_suspend_mode); 299df0566a6SJani Nikula void intel_power_domains_resume(struct drm_i915_private *dev_priv); 300071b68ccSRodrigo Vivi 301071b68ccSRodrigo Vivi void intel_display_power_suspend_late(struct drm_i915_private *i915); 302071b68ccSRodrigo Vivi void intel_display_power_resume_early(struct drm_i915_private *i915); 303071b68ccSRodrigo Vivi void intel_display_power_suspend(struct drm_i915_private *i915); 304071b68ccSRodrigo Vivi void intel_display_power_resume(struct drm_i915_private *i915); 3051c4d821dSAnshuman Gupta void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 3061c4d821dSAnshuman Gupta u32 state); 307df0566a6SJani Nikula 308df0566a6SJani Nikula const char * 3098a84bacbSImre Deak intel_display_power_domain_str(enum intel_display_power_domain domain); 310df0566a6SJani Nikula 311df0566a6SJani Nikula bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 312df0566a6SJani Nikula enum intel_display_power_domain domain); 3139efa0c1aSAnshuman Gupta bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 3149efa0c1aSAnshuman Gupta enum i915_power_well_id power_well_id); 315df0566a6SJani Nikula bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 316df0566a6SJani Nikula enum intel_display_power_domain domain); 317df0566a6SJani Nikula intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 318df0566a6SJani Nikula enum intel_display_power_domain domain); 319df0566a6SJani Nikula intel_wakeref_t 320df0566a6SJani Nikula intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 321df0566a6SJani Nikula enum intel_display_power_domain domain); 322df0566a6SJani Nikula void __intel_display_power_put_async(struct drm_i915_private *i915, 323df0566a6SJani Nikula enum intel_display_power_domain domain, 324df0566a6SJani Nikula intel_wakeref_t wakeref); 325df0566a6SJani Nikula void intel_display_power_flush_work(struct drm_i915_private *i915); 326df0566a6SJani Nikula #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 327df0566a6SJani Nikula void intel_display_power_put(struct drm_i915_private *dev_priv, 328df0566a6SJani Nikula enum intel_display_power_domain domain, 329df0566a6SJani Nikula intel_wakeref_t wakeref); 330df0566a6SJani Nikula static inline void 331df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 332df0566a6SJani Nikula enum intel_display_power_domain domain, 333df0566a6SJani Nikula intel_wakeref_t wakeref) 334df0566a6SJani Nikula { 335df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, wakeref); 336df0566a6SJani Nikula } 337df0566a6SJani Nikula #else 338e3529346SImre Deak void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 339e3529346SImre Deak enum intel_display_power_domain domain); 340e3529346SImre Deak 341df0566a6SJani Nikula static inline void 342df0566a6SJani Nikula intel_display_power_put(struct drm_i915_private *i915, 343df0566a6SJani Nikula enum intel_display_power_domain domain, 344df0566a6SJani Nikula intel_wakeref_t wakeref) 345df0566a6SJani Nikula { 346df0566a6SJani Nikula intel_display_power_put_unchecked(i915, domain); 347df0566a6SJani Nikula } 348df0566a6SJani Nikula 349df0566a6SJani Nikula static inline void 350df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 351df0566a6SJani Nikula enum intel_display_power_domain domain, 352df0566a6SJani Nikula intel_wakeref_t wakeref) 353df0566a6SJani Nikula { 354df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, -1); 355df0566a6SJani Nikula } 356df0566a6SJani Nikula #endif 357df0566a6SJani Nikula 3586979cb9aSImre Deak void 3596979cb9aSImre Deak intel_display_power_get_in_set(struct drm_i915_private *i915, 3606979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 3616979cb9aSImre Deak enum intel_display_power_domain domain); 3626979cb9aSImre Deak 3636979cb9aSImre Deak bool 3646979cb9aSImre Deak intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, 3656979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 3666979cb9aSImre Deak enum intel_display_power_domain domain); 3676979cb9aSImre Deak 3686979cb9aSImre Deak void 3696979cb9aSImre Deak intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 3706979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 3716979cb9aSImre Deak u64 mask); 3726979cb9aSImre Deak 3736979cb9aSImre Deak static inline void 3746979cb9aSImre Deak intel_display_power_put_all_in_set(struct drm_i915_private *i915, 3756979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set) 3766979cb9aSImre Deak { 3776979cb9aSImre Deak intel_display_power_put_mask_in_set(i915, power_domain_set, power_domain_set->mask); 3786979cb9aSImre Deak } 3796979cb9aSImre Deak 3802570b7e3SStanislav Lisovskiy enum dbuf_slice { 3812570b7e3SStanislav Lisovskiy DBUF_S1, 3822570b7e3SStanislav Lisovskiy DBUF_S2, 3838435576bSStanislav Lisovskiy I915_MAX_DBUF_SLICES 3842570b7e3SStanislav Lisovskiy }; 3852570b7e3SStanislav Lisovskiy 38656f48c1dSVille Syrjälä void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 38756f48c1dSVille Syrjälä u8 req_slices); 38856f48c1dSVille Syrjälä 389df0566a6SJani Nikula #define with_intel_display_power(i915, domain, wf) \ 390df0566a6SJani Nikula for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 391df0566a6SJani Nikula intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 392df0566a6SJani Nikula 393df0566a6SJani Nikula void chv_phy_powergate_lanes(struct intel_encoder *encoder, 394df0566a6SJani Nikula bool override, unsigned int mask); 395df0566a6SJani Nikula bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 396df0566a6SJani Nikula enum dpio_channel ch, bool override); 397df0566a6SJani Nikula 398df0566a6SJani Nikula #endif /* __INTEL_DISPLAY_POWER_H__ */ 399