1df0566a6SJani Nikula /* SPDX-License-Identifier: MIT */ 2df0566a6SJani Nikula /* 3df0566a6SJani Nikula * Copyright © 2019 Intel Corporation 4df0566a6SJani Nikula */ 5df0566a6SJani Nikula 6df0566a6SJani Nikula #ifndef __INTEL_DISPLAY_POWER_H__ 7df0566a6SJani Nikula #define __INTEL_DISPLAY_POWER_H__ 8df0566a6SJani Nikula 9df0566a6SJani Nikula #include "intel_display.h" 10df0566a6SJani Nikula #include "intel_runtime_pm.h" 11df0566a6SJani Nikula #include "i915_reg.h" 12df0566a6SJani Nikula 13df0566a6SJani Nikula struct drm_i915_private; 14df0566a6SJani Nikula struct intel_encoder; 15df0566a6SJani Nikula 16df0566a6SJani Nikula enum intel_display_power_domain { 17df0566a6SJani Nikula POWER_DOMAIN_DISPLAY_CORE, 18df0566a6SJani Nikula POWER_DOMAIN_PIPE_A, 19df0566a6SJani Nikula POWER_DOMAIN_PIPE_B, 20df0566a6SJani Nikula POWER_DOMAIN_PIPE_C, 211db27a72SMika Kahola POWER_DOMAIN_PIPE_D, 22df0566a6SJani Nikula POWER_DOMAIN_PIPE_A_PANEL_FITTER, 23df0566a6SJani Nikula POWER_DOMAIN_PIPE_B_PANEL_FITTER, 24df0566a6SJani Nikula POWER_DOMAIN_PIPE_C_PANEL_FITTER, 251db27a72SMika Kahola POWER_DOMAIN_PIPE_D_PANEL_FITTER, 26df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_A, 27df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_B, 28df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_C, 291db27a72SMika Kahola POWER_DOMAIN_TRANSCODER_D, 30df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_EDP, 31f7fd2373SJani Nikula /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */ 32276199e6SJosé Roberto de Souza POWER_DOMAIN_TRANSCODER_VDSC_PW2, 33df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_A, 34df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_C, 35df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_A_LANES, 36df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_B_LANES, 37df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_C_LANES, 38df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_D_LANES, 39df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_E_LANES, 40df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_F_LANES, 418a84bacbSImre Deak POWER_DOMAIN_PORT_DDI_G_LANES, 428a84bacbSImre Deak POWER_DOMAIN_PORT_DDI_H_LANES, 438a84bacbSImre Deak POWER_DOMAIN_PORT_DDI_I_LANES, 44df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_A_IO, 45df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_B_IO, 46df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_C_IO, 47df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_D_IO, 48df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_E_IO, 49df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_F_IO, 50656409bbSImre Deak POWER_DOMAIN_PORT_DDI_G_IO, 51656409bbSImre Deak POWER_DOMAIN_PORT_DDI_H_IO, 52656409bbSImre Deak POWER_DOMAIN_PORT_DDI_I_IO, 53df0566a6SJani Nikula POWER_DOMAIN_PORT_DSI, 54df0566a6SJani Nikula POWER_DOMAIN_PORT_CRT, 55df0566a6SJani Nikula POWER_DOMAIN_PORT_OTHER, 56df0566a6SJani Nikula POWER_DOMAIN_VGA, 57df0566a6SJani Nikula POWER_DOMAIN_AUDIO, 58df0566a6SJani Nikula POWER_DOMAIN_AUX_A, 59df0566a6SJani Nikula POWER_DOMAIN_AUX_B, 60df0566a6SJani Nikula POWER_DOMAIN_AUX_C, 61df0566a6SJani Nikula POWER_DOMAIN_AUX_D, 62df0566a6SJani Nikula POWER_DOMAIN_AUX_E, 63df0566a6SJani Nikula POWER_DOMAIN_AUX_F, 648a84bacbSImre Deak POWER_DOMAIN_AUX_G, 658a84bacbSImre Deak POWER_DOMAIN_AUX_H, 668a84bacbSImre Deak POWER_DOMAIN_AUX_I, 67df0566a6SJani Nikula POWER_DOMAIN_AUX_IO_A, 688a84bacbSImre Deak POWER_DOMAIN_AUX_C_TBT, 698a84bacbSImre Deak POWER_DOMAIN_AUX_D_TBT, 708a84bacbSImre Deak POWER_DOMAIN_AUX_E_TBT, 718a84bacbSImre Deak POWER_DOMAIN_AUX_F_TBT, 728a84bacbSImre Deak POWER_DOMAIN_AUX_G_TBT, 738a84bacbSImre Deak POWER_DOMAIN_AUX_H_TBT, 748a84bacbSImre Deak POWER_DOMAIN_AUX_I_TBT, 75df0566a6SJani Nikula POWER_DOMAIN_GMBUS, 76df0566a6SJani Nikula POWER_DOMAIN_MODESET, 77df0566a6SJani Nikula POWER_DOMAIN_GT_IRQ, 78eef037eaSVivek Kasireddy POWER_DOMAIN_DPLL_DC_OFF, 793c02934bSJosé Roberto de Souza POWER_DOMAIN_TC_COLD_OFF, 80df0566a6SJani Nikula POWER_DOMAIN_INIT, 81df0566a6SJani Nikula 82df0566a6SJani Nikula POWER_DOMAIN_NUM, 83df0566a6SJani Nikula }; 84df0566a6SJani Nikula 853e5d0641SDaniele Ceraolo Spurio /* 863e5d0641SDaniele Ceraolo Spurio * i915_power_well_id: 873e5d0641SDaniele Ceraolo Spurio * 883e5d0641SDaniele Ceraolo Spurio * IDs used to look up power wells. Power wells accessed directly bypassing 893e5d0641SDaniele Ceraolo Spurio * the power domains framework must be assigned a unique ID. The rest of power 903e5d0641SDaniele Ceraolo Spurio * wells must be assigned DISP_PW_ID_NONE. 913e5d0641SDaniele Ceraolo Spurio */ 923e5d0641SDaniele Ceraolo Spurio enum i915_power_well_id { 933e5d0641SDaniele Ceraolo Spurio DISP_PW_ID_NONE, 943e5d0641SDaniele Ceraolo Spurio 953e5d0641SDaniele Ceraolo Spurio VLV_DISP_PW_DISP2D, 963e5d0641SDaniele Ceraolo Spurio BXT_DISP_PW_DPIO_CMN_A, 973e5d0641SDaniele Ceraolo Spurio VLV_DISP_PW_DPIO_CMN_BC, 983e5d0641SDaniele Ceraolo Spurio GLK_DISP_PW_DPIO_CMN_C, 993e5d0641SDaniele Ceraolo Spurio CHV_DISP_PW_DPIO_CMN_D, 1003e5d0641SDaniele Ceraolo Spurio HSW_DISP_PW_GLOBAL, 1013e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_MISC_IO, 1023e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_1, 1033e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_2, 10462277f33SLucas De Marchi CNL_DISP_PW_DDI_F_IO, 10562277f33SLucas De Marchi CNL_DISP_PW_DDI_F_AUX, 106fc4a8c16SAnshuman Gupta ICL_DISP_PW_3, 1074645e906SAnshuman Gupta SKL_DISP_DC_OFF, 108240abb3cSLucas De Marchi TGL_DISP_PW_TC_COLD_OFF, 1093e5d0641SDaniele Ceraolo Spurio }; 1103e5d0641SDaniele Ceraolo Spurio 111df0566a6SJani Nikula #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 112df0566a6SJani Nikula #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 113df0566a6SJani Nikula ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 114df0566a6SJani Nikula #define POWER_DOMAIN_TRANSCODER(tran) \ 115df0566a6SJani Nikula ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 116df0566a6SJani Nikula (tran) + POWER_DOMAIN_TRANSCODER_A) 117df0566a6SJani Nikula 118df0566a6SJani Nikula struct i915_power_well; 119df0566a6SJani Nikula 120df0566a6SJani Nikula struct i915_power_well_ops { 121df0566a6SJani Nikula /* 122df0566a6SJani Nikula * Synchronize the well's hw state to match the current sw state, for 123df0566a6SJani Nikula * example enable/disable it based on the current refcount. Called 124df0566a6SJani Nikula * during driver init and resume time, possibly after first calling 125df0566a6SJani Nikula * the enable/disable handlers. 126df0566a6SJani Nikula */ 127df0566a6SJani Nikula void (*sync_hw)(struct drm_i915_private *dev_priv, 128df0566a6SJani Nikula struct i915_power_well *power_well); 129df0566a6SJani Nikula /* 130df0566a6SJani Nikula * Enable the well and resources that depend on it (for example 131df0566a6SJani Nikula * interrupts located on the well). Called after the 0->1 refcount 132df0566a6SJani Nikula * transition. 133df0566a6SJani Nikula */ 134df0566a6SJani Nikula void (*enable)(struct drm_i915_private *dev_priv, 135df0566a6SJani Nikula struct i915_power_well *power_well); 136df0566a6SJani Nikula /* 137df0566a6SJani Nikula * Disable the well and resources that depend on it. Called after 138df0566a6SJani Nikula * the 1->0 refcount transition. 139df0566a6SJani Nikula */ 140df0566a6SJani Nikula void (*disable)(struct drm_i915_private *dev_priv, 141df0566a6SJani Nikula struct i915_power_well *power_well); 142df0566a6SJani Nikula /* Returns the hw enabled state. */ 143df0566a6SJani Nikula bool (*is_enabled)(struct drm_i915_private *dev_priv, 144df0566a6SJani Nikula struct i915_power_well *power_well); 145df0566a6SJani Nikula }; 146df0566a6SJani Nikula 147df0566a6SJani Nikula struct i915_power_well_regs { 148df0566a6SJani Nikula i915_reg_t bios; 149df0566a6SJani Nikula i915_reg_t driver; 150df0566a6SJani Nikula i915_reg_t kvmr; 151df0566a6SJani Nikula i915_reg_t debug; 152df0566a6SJani Nikula }; 153df0566a6SJani Nikula 154df0566a6SJani Nikula /* Power well structure for haswell */ 155df0566a6SJani Nikula struct i915_power_well_desc { 156df0566a6SJani Nikula const char *name; 157df0566a6SJani Nikula bool always_on; 158df0566a6SJani Nikula u64 domains; 159df0566a6SJani Nikula /* unique identifier for this power well */ 160df0566a6SJani Nikula enum i915_power_well_id id; 161df0566a6SJani Nikula /* 162df0566a6SJani Nikula * Arbitraty data associated with this power well. Platform and power 163df0566a6SJani Nikula * well specific. 164df0566a6SJani Nikula */ 165df0566a6SJani Nikula union { 166df0566a6SJani Nikula struct { 167df0566a6SJani Nikula /* 168df0566a6SJani Nikula * request/status flag index in the PUNIT power well 169df0566a6SJani Nikula * control/status registers. 170df0566a6SJani Nikula */ 171df0566a6SJani Nikula u8 idx; 172df0566a6SJani Nikula } vlv; 173df0566a6SJani Nikula struct { 174df0566a6SJani Nikula enum dpio_phy phy; 175df0566a6SJani Nikula } bxt; 176df0566a6SJani Nikula struct { 177df0566a6SJani Nikula const struct i915_power_well_regs *regs; 178df0566a6SJani Nikula /* 179df0566a6SJani Nikula * request/status flag index in the power well 180df0566a6SJani Nikula * constrol/status registers. 181df0566a6SJani Nikula */ 182df0566a6SJani Nikula u8 idx; 183df0566a6SJani Nikula /* Mask of pipes whose IRQ logic is backed by the pw */ 184df0566a6SJani Nikula u8 irq_pipe_mask; 185df0566a6SJani Nikula /* The pw is backing the VGA functionality */ 186df0566a6SJani Nikula bool has_vga:1; 187df0566a6SJani Nikula bool has_fuses:1; 188df0566a6SJani Nikula /* 189df0566a6SJani Nikula * The pw is for an ICL+ TypeC PHY port in 190df0566a6SJani Nikula * Thunderbolt mode. 191df0566a6SJani Nikula */ 192df0566a6SJani Nikula bool is_tc_tbt:1; 193df0566a6SJani Nikula } hsw; 194df0566a6SJani Nikula }; 195df0566a6SJani Nikula const struct i915_power_well_ops *ops; 196df0566a6SJani Nikula }; 197df0566a6SJani Nikula 198df0566a6SJani Nikula struct i915_power_well { 199df0566a6SJani Nikula const struct i915_power_well_desc *desc; 200df0566a6SJani Nikula /* power well enable/disable usage count */ 201df0566a6SJani Nikula int count; 202df0566a6SJani Nikula /* cached hw enabled state */ 203df0566a6SJani Nikula bool hw_enabled; 204df0566a6SJani Nikula }; 205df0566a6SJani Nikula 206df0566a6SJani Nikula struct i915_power_domains { 207df0566a6SJani Nikula /* 208df0566a6SJani Nikula * Power wells needed for initialization at driver init and suspend 209df0566a6SJani Nikula * time are on. They are kept on until after the first modeset. 210df0566a6SJani Nikula */ 211df0566a6SJani Nikula bool initializing; 212df0566a6SJani Nikula bool display_core_suspended; 213df0566a6SJani Nikula int power_well_count; 214df0566a6SJani Nikula 215df0566a6SJani Nikula intel_wakeref_t wakeref; 216df0566a6SJani Nikula 217df0566a6SJani Nikula struct mutex lock; 218df0566a6SJani Nikula int domain_use_count[POWER_DOMAIN_NUM]; 219df0566a6SJani Nikula 220df0566a6SJani Nikula struct delayed_work async_put_work; 221df0566a6SJani Nikula intel_wakeref_t async_put_wakeref; 222df0566a6SJani Nikula u64 async_put_domains[2]; 223df0566a6SJani Nikula 224df0566a6SJani Nikula struct i915_power_well *power_wells; 225df0566a6SJani Nikula }; 226df0566a6SJani Nikula 227*6979cb9aSImre Deak struct intel_display_power_domain_set { 228*6979cb9aSImre Deak u64 mask; 229*6979cb9aSImre Deak #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM 230*6979cb9aSImre Deak intel_wakeref_t wakerefs[POWER_DOMAIN_NUM]; 231*6979cb9aSImre Deak #endif 232*6979cb9aSImre Deak }; 233*6979cb9aSImre Deak 234df0566a6SJani Nikula #define for_each_power_domain(domain, mask) \ 235df0566a6SJani Nikula for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 236df0566a6SJani Nikula for_each_if(BIT_ULL(domain) & (mask)) 237df0566a6SJani Nikula 238df0566a6SJani Nikula #define for_each_power_well(__dev_priv, __power_well) \ 239df0566a6SJani Nikula for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ 240df0566a6SJani Nikula (__power_well) - (__dev_priv)->power_domains.power_wells < \ 241df0566a6SJani Nikula (__dev_priv)->power_domains.power_well_count; \ 242df0566a6SJani Nikula (__power_well)++) 243df0566a6SJani Nikula 244df0566a6SJani Nikula #define for_each_power_well_reverse(__dev_priv, __power_well) \ 245df0566a6SJani Nikula for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ 246df0566a6SJani Nikula (__dev_priv)->power_domains.power_well_count - 1; \ 247df0566a6SJani Nikula (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ 248df0566a6SJani Nikula (__power_well)--) 249df0566a6SJani Nikula 250df0566a6SJani Nikula #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ 251df0566a6SJani Nikula for_each_power_well(__dev_priv, __power_well) \ 252df0566a6SJani Nikula for_each_if((__power_well)->desc->domains & (__domain_mask)) 253df0566a6SJani Nikula 254df0566a6SJani Nikula #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ 255df0566a6SJani Nikula for_each_power_well_reverse(__dev_priv, __power_well) \ 256df0566a6SJani Nikula for_each_if((__power_well)->desc->domains & (__domain_mask)) 257df0566a6SJani Nikula 258df0566a6SJani Nikula int intel_power_domains_init(struct drm_i915_private *dev_priv); 259df0566a6SJani Nikula void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 260df0566a6SJani Nikula void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 26178dae1acSJanusz Krzysztofik void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 262df0566a6SJani Nikula void intel_power_domains_enable(struct drm_i915_private *dev_priv); 263df0566a6SJani Nikula void intel_power_domains_disable(struct drm_i915_private *dev_priv); 264df0566a6SJani Nikula void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 265df0566a6SJani Nikula enum i915_drm_suspend_mode); 266df0566a6SJani Nikula void intel_power_domains_resume(struct drm_i915_private *dev_priv); 267071b68ccSRodrigo Vivi 268071b68ccSRodrigo Vivi void intel_display_power_suspend_late(struct drm_i915_private *i915); 269071b68ccSRodrigo Vivi void intel_display_power_resume_early(struct drm_i915_private *i915); 270071b68ccSRodrigo Vivi void intel_display_power_suspend(struct drm_i915_private *i915); 271071b68ccSRodrigo Vivi void intel_display_power_resume(struct drm_i915_private *i915); 2721c4d821dSAnshuman Gupta void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 2731c4d821dSAnshuman Gupta u32 state); 274df0566a6SJani Nikula 275df0566a6SJani Nikula const char * 2768a84bacbSImre Deak intel_display_power_domain_str(enum intel_display_power_domain domain); 277df0566a6SJani Nikula 278df0566a6SJani Nikula bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 279df0566a6SJani Nikula enum intel_display_power_domain domain); 2809efa0c1aSAnshuman Gupta bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 2819efa0c1aSAnshuman Gupta enum i915_power_well_id power_well_id); 282df0566a6SJani Nikula bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 283df0566a6SJani Nikula enum intel_display_power_domain domain); 284df0566a6SJani Nikula intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 285df0566a6SJani Nikula enum intel_display_power_domain domain); 286df0566a6SJani Nikula intel_wakeref_t 287df0566a6SJani Nikula intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 288df0566a6SJani Nikula enum intel_display_power_domain domain); 289df0566a6SJani Nikula void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 290df0566a6SJani Nikula enum intel_display_power_domain domain); 291df0566a6SJani Nikula void __intel_display_power_put_async(struct drm_i915_private *i915, 292df0566a6SJani Nikula enum intel_display_power_domain domain, 293df0566a6SJani Nikula intel_wakeref_t wakeref); 294df0566a6SJani Nikula void intel_display_power_flush_work(struct drm_i915_private *i915); 295df0566a6SJani Nikula #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 296df0566a6SJani Nikula void intel_display_power_put(struct drm_i915_private *dev_priv, 297df0566a6SJani Nikula enum intel_display_power_domain domain, 298df0566a6SJani Nikula intel_wakeref_t wakeref); 299df0566a6SJani Nikula static inline void 300df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 301df0566a6SJani Nikula enum intel_display_power_domain domain, 302df0566a6SJani Nikula intel_wakeref_t wakeref) 303df0566a6SJani Nikula { 304df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, wakeref); 305df0566a6SJani Nikula } 306df0566a6SJani Nikula #else 307df0566a6SJani Nikula static inline void 308df0566a6SJani Nikula intel_display_power_put(struct drm_i915_private *i915, 309df0566a6SJani Nikula enum intel_display_power_domain domain, 310df0566a6SJani Nikula intel_wakeref_t wakeref) 311df0566a6SJani Nikula { 312df0566a6SJani Nikula intel_display_power_put_unchecked(i915, domain); 313df0566a6SJani Nikula } 314df0566a6SJani Nikula 315df0566a6SJani Nikula static inline void 316df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 317df0566a6SJani Nikula enum intel_display_power_domain domain, 318df0566a6SJani Nikula intel_wakeref_t wakeref) 319df0566a6SJani Nikula { 320df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, -1); 321df0566a6SJani Nikula } 322df0566a6SJani Nikula #endif 323df0566a6SJani Nikula 324*6979cb9aSImre Deak void 325*6979cb9aSImre Deak intel_display_power_get_in_set(struct drm_i915_private *i915, 326*6979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 327*6979cb9aSImre Deak enum intel_display_power_domain domain); 328*6979cb9aSImre Deak 329*6979cb9aSImre Deak bool 330*6979cb9aSImre Deak intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, 331*6979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 332*6979cb9aSImre Deak enum intel_display_power_domain domain); 333*6979cb9aSImre Deak 334*6979cb9aSImre Deak void 335*6979cb9aSImre Deak intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 336*6979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 337*6979cb9aSImre Deak u64 mask); 338*6979cb9aSImre Deak 339*6979cb9aSImre Deak static inline void 340*6979cb9aSImre Deak intel_display_power_put_all_in_set(struct drm_i915_private *i915, 341*6979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set) 342*6979cb9aSImre Deak { 343*6979cb9aSImre Deak intel_display_power_put_mask_in_set(i915, power_domain_set, power_domain_set->mask); 344*6979cb9aSImre Deak } 345*6979cb9aSImre Deak 3462570b7e3SStanislav Lisovskiy enum dbuf_slice { 3472570b7e3SStanislav Lisovskiy DBUF_S1, 3482570b7e3SStanislav Lisovskiy DBUF_S2, 3498435576bSStanislav Lisovskiy I915_MAX_DBUF_SLICES 3502570b7e3SStanislav Lisovskiy }; 3512570b7e3SStanislav Lisovskiy 35256f48c1dSVille Syrjälä void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 35356f48c1dSVille Syrjälä u8 req_slices); 35456f48c1dSVille Syrjälä 355df0566a6SJani Nikula #define with_intel_display_power(i915, domain, wf) \ 356df0566a6SJani Nikula for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 357df0566a6SJani Nikula intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 358df0566a6SJani Nikula 359df0566a6SJani Nikula void chv_phy_powergate_lanes(struct intel_encoder *encoder, 360df0566a6SJani Nikula bool override, unsigned int mask); 361df0566a6SJani Nikula bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 362df0566a6SJani Nikula enum dpio_channel ch, bool override); 363df0566a6SJani Nikula 364df0566a6SJani Nikula #endif /* __INTEL_DISPLAY_POWER_H__ */ 365