1df0566a6SJani Nikula /* SPDX-License-Identifier: MIT */ 2df0566a6SJani Nikula /* 3df0566a6SJani Nikula * Copyright © 2019 Intel Corporation 4df0566a6SJani Nikula */ 5df0566a6SJani Nikula 6df0566a6SJani Nikula #ifndef __INTEL_DISPLAY_POWER_H__ 7df0566a6SJani Nikula #define __INTEL_DISPLAY_POWER_H__ 8df0566a6SJani Nikula 9df0566a6SJani Nikula #include "intel_display.h" 10df0566a6SJani Nikula #include "intel_runtime_pm.h" 11df0566a6SJani Nikula #include "i915_reg.h" 12df0566a6SJani Nikula 13df0566a6SJani Nikula struct drm_i915_private; 14df0566a6SJani Nikula struct intel_encoder; 15df0566a6SJani Nikula 16df0566a6SJani Nikula enum intel_display_power_domain { 17df0566a6SJani Nikula POWER_DOMAIN_DISPLAY_CORE, 18df0566a6SJani Nikula POWER_DOMAIN_PIPE_A, 19df0566a6SJani Nikula POWER_DOMAIN_PIPE_B, 20df0566a6SJani Nikula POWER_DOMAIN_PIPE_C, 211db27a72SMika Kahola POWER_DOMAIN_PIPE_D, 22df0566a6SJani Nikula POWER_DOMAIN_PIPE_A_PANEL_FITTER, 23df0566a6SJani Nikula POWER_DOMAIN_PIPE_B_PANEL_FITTER, 24df0566a6SJani Nikula POWER_DOMAIN_PIPE_C_PANEL_FITTER, 251db27a72SMika Kahola POWER_DOMAIN_PIPE_D_PANEL_FITTER, 26df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_A, 27df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_B, 28df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_C, 291db27a72SMika Kahola POWER_DOMAIN_TRANSCODER_D, 30df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_EDP, 31f7fd2373SJani Nikula /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */ 32276199e6SJosé Roberto de Souza POWER_DOMAIN_TRANSCODER_VDSC_PW2, 33df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_A, 34df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_C, 35df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_A_LANES, 36df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_B_LANES, 37df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_C_LANES, 38df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_D_LANES, 39df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_E_LANES, 40df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_F_LANES, 418a84bacbSImre Deak POWER_DOMAIN_PORT_DDI_G_LANES, 428a84bacbSImre Deak POWER_DOMAIN_PORT_DDI_H_LANES, 438a84bacbSImre Deak POWER_DOMAIN_PORT_DDI_I_LANES, 44c7392718SImre Deak 45c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_D_LANES, /* tgl+ */ 46c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC2, 47c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC3, 48c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC4, 49c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC5, 50c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC6, 51c7392718SImre Deak 52a6922f4aSMatt Roper POWER_DOMAIN_PORT_DDI_LANES_D_XELPD = POWER_DOMAIN_PORT_DDI_LANES_TC5, /* XELPD */ 53a6922f4aSMatt Roper POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, 54a6922f4aSMatt Roper 55df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_A_IO, 56df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_B_IO, 57df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_C_IO, 58df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_D_IO, 59df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_E_IO, 60df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_F_IO, 61656409bbSImre Deak POWER_DOMAIN_PORT_DDI_G_IO, 62656409bbSImre Deak POWER_DOMAIN_PORT_DDI_H_IO, 63656409bbSImre Deak POWER_DOMAIN_PORT_DDI_I_IO, 64c7392718SImre Deak 65c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_D_IO, /* tgl+ */ 66c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC2, 67c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC3, 68c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC4, 69c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC5, 70c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC6, 71c7392718SImre Deak 72a6922f4aSMatt Roper POWER_DOMAIN_PORT_DDI_IO_D_XELPD = POWER_DOMAIN_PORT_DDI_IO_TC5, /* XELPD */ 73a6922f4aSMatt Roper POWER_DOMAIN_PORT_DDI_IO_E_XELPD, 74a6922f4aSMatt Roper 75df0566a6SJani Nikula POWER_DOMAIN_PORT_DSI, 76df0566a6SJani Nikula POWER_DOMAIN_PORT_CRT, 77df0566a6SJani Nikula POWER_DOMAIN_PORT_OTHER, 78df0566a6SJani Nikula POWER_DOMAIN_VGA, 79*615a7724SAnshuman Gupta POWER_DOMAIN_AUDIO_MMIO, 80*615a7724SAnshuman Gupta POWER_DOMAIN_AUDIO_PLAYBACK, 81df0566a6SJani Nikula POWER_DOMAIN_AUX_A, 82df0566a6SJani Nikula POWER_DOMAIN_AUX_B, 83df0566a6SJani Nikula POWER_DOMAIN_AUX_C, 84df0566a6SJani Nikula POWER_DOMAIN_AUX_D, 85df0566a6SJani Nikula POWER_DOMAIN_AUX_E, 86df0566a6SJani Nikula POWER_DOMAIN_AUX_F, 878a84bacbSImre Deak POWER_DOMAIN_AUX_G, 888a84bacbSImre Deak POWER_DOMAIN_AUX_H, 898a84bacbSImre Deak POWER_DOMAIN_AUX_I, 90c7392718SImre Deak 91c7392718SImre Deak POWER_DOMAIN_AUX_USBC1 = POWER_DOMAIN_AUX_D, /* tgl+ */ 92c7392718SImre Deak POWER_DOMAIN_AUX_USBC2, 93c7392718SImre Deak POWER_DOMAIN_AUX_USBC3, 94c7392718SImre Deak POWER_DOMAIN_AUX_USBC4, 95c7392718SImre Deak POWER_DOMAIN_AUX_USBC5, 96c7392718SImre Deak POWER_DOMAIN_AUX_USBC6, 97c7392718SImre Deak 98a6922f4aSMatt Roper POWER_DOMAIN_AUX_D_XELPD = POWER_DOMAIN_AUX_USBC5, /* XELPD */ 99a6922f4aSMatt Roper POWER_DOMAIN_AUX_E_XELPD, 100a6922f4aSMatt Roper 101df0566a6SJani Nikula POWER_DOMAIN_AUX_IO_A, 1028a84bacbSImre Deak POWER_DOMAIN_AUX_C_TBT, 1038a84bacbSImre Deak POWER_DOMAIN_AUX_D_TBT, 1048a84bacbSImre Deak POWER_DOMAIN_AUX_E_TBT, 1058a84bacbSImre Deak POWER_DOMAIN_AUX_F_TBT, 1068a84bacbSImre Deak POWER_DOMAIN_AUX_G_TBT, 1078a84bacbSImre Deak POWER_DOMAIN_AUX_H_TBT, 1088a84bacbSImre Deak POWER_DOMAIN_AUX_I_TBT, 109c7392718SImre Deak 110c7392718SImre Deak POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_D_TBT, /* tgl+ */ 111c7392718SImre Deak POWER_DOMAIN_AUX_TBT2, 112c7392718SImre Deak POWER_DOMAIN_AUX_TBT3, 113c7392718SImre Deak POWER_DOMAIN_AUX_TBT4, 114c7392718SImre Deak POWER_DOMAIN_AUX_TBT5, 115c7392718SImre Deak POWER_DOMAIN_AUX_TBT6, 116c7392718SImre Deak 117df0566a6SJani Nikula POWER_DOMAIN_GMBUS, 118df0566a6SJani Nikula POWER_DOMAIN_MODESET, 119df0566a6SJani Nikula POWER_DOMAIN_GT_IRQ, 120eef037eaSVivek Kasireddy POWER_DOMAIN_DPLL_DC_OFF, 1213c02934bSJosé Roberto de Souza POWER_DOMAIN_TC_COLD_OFF, 122df0566a6SJani Nikula POWER_DOMAIN_INIT, 123df0566a6SJani Nikula 124df0566a6SJani Nikula POWER_DOMAIN_NUM, 125df0566a6SJani Nikula }; 126df0566a6SJani Nikula 1273e5d0641SDaniele Ceraolo Spurio /* 1283e5d0641SDaniele Ceraolo Spurio * i915_power_well_id: 1293e5d0641SDaniele Ceraolo Spurio * 1303e5d0641SDaniele Ceraolo Spurio * IDs used to look up power wells. Power wells accessed directly bypassing 1313e5d0641SDaniele Ceraolo Spurio * the power domains framework must be assigned a unique ID. The rest of power 1323e5d0641SDaniele Ceraolo Spurio * wells must be assigned DISP_PW_ID_NONE. 1333e5d0641SDaniele Ceraolo Spurio */ 1343e5d0641SDaniele Ceraolo Spurio enum i915_power_well_id { 1353e5d0641SDaniele Ceraolo Spurio DISP_PW_ID_NONE, 1363e5d0641SDaniele Ceraolo Spurio 1373e5d0641SDaniele Ceraolo Spurio VLV_DISP_PW_DISP2D, 1383e5d0641SDaniele Ceraolo Spurio BXT_DISP_PW_DPIO_CMN_A, 1393e5d0641SDaniele Ceraolo Spurio VLV_DISP_PW_DPIO_CMN_BC, 1403e5d0641SDaniele Ceraolo Spurio GLK_DISP_PW_DPIO_CMN_C, 1413e5d0641SDaniele Ceraolo Spurio CHV_DISP_PW_DPIO_CMN_D, 1423e5d0641SDaniele Ceraolo Spurio HSW_DISP_PW_GLOBAL, 1433e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_MISC_IO, 1443e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_1, 1453e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_2, 146fc4a8c16SAnshuman Gupta ICL_DISP_PW_3, 1474645e906SAnshuman Gupta SKL_DISP_DC_OFF, 148240abb3cSLucas De Marchi TGL_DISP_PW_TC_COLD_OFF, 1493e5d0641SDaniele Ceraolo Spurio }; 1503e5d0641SDaniele Ceraolo Spurio 151df0566a6SJani Nikula #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 152df0566a6SJani Nikula #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 153df0566a6SJani Nikula ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 154df0566a6SJani Nikula #define POWER_DOMAIN_TRANSCODER(tran) \ 155df0566a6SJani Nikula ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 156df0566a6SJani Nikula (tran) + POWER_DOMAIN_TRANSCODER_A) 157df0566a6SJani Nikula 158df0566a6SJani Nikula struct i915_power_well; 159df0566a6SJani Nikula 160df0566a6SJani Nikula struct i915_power_well_ops { 161df0566a6SJani Nikula /* 162df0566a6SJani Nikula * Synchronize the well's hw state to match the current sw state, for 163df0566a6SJani Nikula * example enable/disable it based on the current refcount. Called 164df0566a6SJani Nikula * during driver init and resume time, possibly after first calling 165df0566a6SJani Nikula * the enable/disable handlers. 166df0566a6SJani Nikula */ 167df0566a6SJani Nikula void (*sync_hw)(struct drm_i915_private *dev_priv, 168df0566a6SJani Nikula struct i915_power_well *power_well); 169df0566a6SJani Nikula /* 170df0566a6SJani Nikula * Enable the well and resources that depend on it (for example 171df0566a6SJani Nikula * interrupts located on the well). Called after the 0->1 refcount 172df0566a6SJani Nikula * transition. 173df0566a6SJani Nikula */ 174df0566a6SJani Nikula void (*enable)(struct drm_i915_private *dev_priv, 175df0566a6SJani Nikula struct i915_power_well *power_well); 176df0566a6SJani Nikula /* 177df0566a6SJani Nikula * Disable the well and resources that depend on it. Called after 178df0566a6SJani Nikula * the 1->0 refcount transition. 179df0566a6SJani Nikula */ 180df0566a6SJani Nikula void (*disable)(struct drm_i915_private *dev_priv, 181df0566a6SJani Nikula struct i915_power_well *power_well); 182df0566a6SJani Nikula /* Returns the hw enabled state. */ 183df0566a6SJani Nikula bool (*is_enabled)(struct drm_i915_private *dev_priv, 184df0566a6SJani Nikula struct i915_power_well *power_well); 185df0566a6SJani Nikula }; 186df0566a6SJani Nikula 187df0566a6SJani Nikula struct i915_power_well_regs { 188df0566a6SJani Nikula i915_reg_t bios; 189df0566a6SJani Nikula i915_reg_t driver; 190df0566a6SJani Nikula i915_reg_t kvmr; 191df0566a6SJani Nikula i915_reg_t debug; 192df0566a6SJani Nikula }; 193df0566a6SJani Nikula 194df0566a6SJani Nikula /* Power well structure for haswell */ 195df0566a6SJani Nikula struct i915_power_well_desc { 196df0566a6SJani Nikula const char *name; 197df0566a6SJani Nikula bool always_on; 198df0566a6SJani Nikula u64 domains; 199df0566a6SJani Nikula /* unique identifier for this power well */ 200df0566a6SJani Nikula enum i915_power_well_id id; 201df0566a6SJani Nikula /* 202df0566a6SJani Nikula * Arbitraty data associated with this power well. Platform and power 203df0566a6SJani Nikula * well specific. 204df0566a6SJani Nikula */ 205df0566a6SJani Nikula union { 206df0566a6SJani Nikula struct { 207df0566a6SJani Nikula /* 208df0566a6SJani Nikula * request/status flag index in the PUNIT power well 209df0566a6SJani Nikula * control/status registers. 210df0566a6SJani Nikula */ 211df0566a6SJani Nikula u8 idx; 212df0566a6SJani Nikula } vlv; 213df0566a6SJani Nikula struct { 214df0566a6SJani Nikula enum dpio_phy phy; 215df0566a6SJani Nikula } bxt; 216df0566a6SJani Nikula struct { 217df0566a6SJani Nikula const struct i915_power_well_regs *regs; 218df0566a6SJani Nikula /* 219df0566a6SJani Nikula * request/status flag index in the power well 220df0566a6SJani Nikula * constrol/status registers. 221df0566a6SJani Nikula */ 222df0566a6SJani Nikula u8 idx; 223df0566a6SJani Nikula /* Mask of pipes whose IRQ logic is backed by the pw */ 224df0566a6SJani Nikula u8 irq_pipe_mask; 22548f8f016SMatt Roper /* 22648f8f016SMatt Roper * Instead of waiting for the status bit to ack enables, 22748f8f016SMatt Roper * just wait a specific amount of time and then consider 22848f8f016SMatt Roper * the well enabled. 22948f8f016SMatt Roper */ 23048f8f016SMatt Roper u16 fixed_enable_delay; 231df0566a6SJani Nikula /* The pw is backing the VGA functionality */ 232df0566a6SJani Nikula bool has_vga:1; 233df0566a6SJani Nikula bool has_fuses:1; 234df0566a6SJani Nikula /* 235df0566a6SJani Nikula * The pw is for an ICL+ TypeC PHY port in 236df0566a6SJani Nikula * Thunderbolt mode. 237df0566a6SJani Nikula */ 238df0566a6SJani Nikula bool is_tc_tbt:1; 239df0566a6SJani Nikula } hsw; 240df0566a6SJani Nikula }; 241df0566a6SJani Nikula const struct i915_power_well_ops *ops; 242df0566a6SJani Nikula }; 243df0566a6SJani Nikula 244df0566a6SJani Nikula struct i915_power_well { 245df0566a6SJani Nikula const struct i915_power_well_desc *desc; 246df0566a6SJani Nikula /* power well enable/disable usage count */ 247df0566a6SJani Nikula int count; 248df0566a6SJani Nikula /* cached hw enabled state */ 249df0566a6SJani Nikula bool hw_enabled; 250df0566a6SJani Nikula }; 251df0566a6SJani Nikula 252df0566a6SJani Nikula struct i915_power_domains { 253df0566a6SJani Nikula /* 254df0566a6SJani Nikula * Power wells needed for initialization at driver init and suspend 255df0566a6SJani Nikula * time are on. They are kept on until after the first modeset. 256df0566a6SJani Nikula */ 257df0566a6SJani Nikula bool initializing; 258df0566a6SJani Nikula bool display_core_suspended; 259df0566a6SJani Nikula int power_well_count; 260df0566a6SJani Nikula 261a0b024edSImre Deak intel_wakeref_t init_wakeref; 26293b916fdSImre Deak intel_wakeref_t disable_wakeref; 263df0566a6SJani Nikula 264df0566a6SJani Nikula struct mutex lock; 265df0566a6SJani Nikula int domain_use_count[POWER_DOMAIN_NUM]; 266df0566a6SJani Nikula 267df0566a6SJani Nikula struct delayed_work async_put_work; 268df0566a6SJani Nikula intel_wakeref_t async_put_wakeref; 269df0566a6SJani Nikula u64 async_put_domains[2]; 270df0566a6SJani Nikula 271df0566a6SJani Nikula struct i915_power_well *power_wells; 272df0566a6SJani Nikula }; 273df0566a6SJani Nikula 2746979cb9aSImre Deak struct intel_display_power_domain_set { 2756979cb9aSImre Deak u64 mask; 2766979cb9aSImre Deak #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM 2776979cb9aSImre Deak intel_wakeref_t wakerefs[POWER_DOMAIN_NUM]; 2786979cb9aSImre Deak #endif 2796979cb9aSImre Deak }; 2806979cb9aSImre Deak 281df0566a6SJani Nikula #define for_each_power_domain(domain, mask) \ 282df0566a6SJani Nikula for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 283df0566a6SJani Nikula for_each_if(BIT_ULL(domain) & (mask)) 284df0566a6SJani Nikula 285df0566a6SJani Nikula #define for_each_power_well(__dev_priv, __power_well) \ 286df0566a6SJani Nikula for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ 287df0566a6SJani Nikula (__power_well) - (__dev_priv)->power_domains.power_wells < \ 288df0566a6SJani Nikula (__dev_priv)->power_domains.power_well_count; \ 289df0566a6SJani Nikula (__power_well)++) 290df0566a6SJani Nikula 291df0566a6SJani Nikula #define for_each_power_well_reverse(__dev_priv, __power_well) \ 292df0566a6SJani Nikula for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ 293df0566a6SJani Nikula (__dev_priv)->power_domains.power_well_count - 1; \ 294df0566a6SJani Nikula (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ 295df0566a6SJani Nikula (__power_well)--) 296df0566a6SJani Nikula 297df0566a6SJani Nikula #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ 298df0566a6SJani Nikula for_each_power_well(__dev_priv, __power_well) \ 299df0566a6SJani Nikula for_each_if((__power_well)->desc->domains & (__domain_mask)) 300df0566a6SJani Nikula 301df0566a6SJani Nikula #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ 302df0566a6SJani Nikula for_each_power_well_reverse(__dev_priv, __power_well) \ 303df0566a6SJani Nikula for_each_if((__power_well)->desc->domains & (__domain_mask)) 304df0566a6SJani Nikula 305df0566a6SJani Nikula int intel_power_domains_init(struct drm_i915_private *dev_priv); 306df0566a6SJani Nikula void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 307df0566a6SJani Nikula void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 30878dae1acSJanusz Krzysztofik void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 309df0566a6SJani Nikula void intel_power_domains_enable(struct drm_i915_private *dev_priv); 310df0566a6SJani Nikula void intel_power_domains_disable(struct drm_i915_private *dev_priv); 311df0566a6SJani Nikula void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 312df0566a6SJani Nikula enum i915_drm_suspend_mode); 313df0566a6SJani Nikula void intel_power_domains_resume(struct drm_i915_private *dev_priv); 314071b68ccSRodrigo Vivi 315071b68ccSRodrigo Vivi void intel_display_power_suspend_late(struct drm_i915_private *i915); 316071b68ccSRodrigo Vivi void intel_display_power_resume_early(struct drm_i915_private *i915); 317071b68ccSRodrigo Vivi void intel_display_power_suspend(struct drm_i915_private *i915); 318071b68ccSRodrigo Vivi void intel_display_power_resume(struct drm_i915_private *i915); 3191c4d821dSAnshuman Gupta void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 3201c4d821dSAnshuman Gupta u32 state); 321df0566a6SJani Nikula 322df0566a6SJani Nikula const char * 3238a84bacbSImre Deak intel_display_power_domain_str(enum intel_display_power_domain domain); 324df0566a6SJani Nikula 325df0566a6SJani Nikula bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 326df0566a6SJani Nikula enum intel_display_power_domain domain); 3279efa0c1aSAnshuman Gupta bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 3289efa0c1aSAnshuman Gupta enum i915_power_well_id power_well_id); 329df0566a6SJani Nikula bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 330df0566a6SJani Nikula enum intel_display_power_domain domain); 331df0566a6SJani Nikula intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 332df0566a6SJani Nikula enum intel_display_power_domain domain); 333df0566a6SJani Nikula intel_wakeref_t 334df0566a6SJani Nikula intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 335df0566a6SJani Nikula enum intel_display_power_domain domain); 336df0566a6SJani Nikula void __intel_display_power_put_async(struct drm_i915_private *i915, 337df0566a6SJani Nikula enum intel_display_power_domain domain, 338df0566a6SJani Nikula intel_wakeref_t wakeref); 339df0566a6SJani Nikula void intel_display_power_flush_work(struct drm_i915_private *i915); 340df0566a6SJani Nikula #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 341df0566a6SJani Nikula void intel_display_power_put(struct drm_i915_private *dev_priv, 342df0566a6SJani Nikula enum intel_display_power_domain domain, 343df0566a6SJani Nikula intel_wakeref_t wakeref); 344df0566a6SJani Nikula static inline void 345df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 346df0566a6SJani Nikula enum intel_display_power_domain domain, 347df0566a6SJani Nikula intel_wakeref_t wakeref) 348df0566a6SJani Nikula { 349df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, wakeref); 350df0566a6SJani Nikula } 351df0566a6SJani Nikula #else 352e3529346SImre Deak void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 353e3529346SImre Deak enum intel_display_power_domain domain); 354e3529346SImre Deak 355df0566a6SJani Nikula static inline void 356df0566a6SJani Nikula intel_display_power_put(struct drm_i915_private *i915, 357df0566a6SJani Nikula enum intel_display_power_domain domain, 358df0566a6SJani Nikula intel_wakeref_t wakeref) 359df0566a6SJani Nikula { 360df0566a6SJani Nikula intel_display_power_put_unchecked(i915, domain); 361df0566a6SJani Nikula } 362df0566a6SJani Nikula 363df0566a6SJani Nikula static inline void 364df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 365df0566a6SJani Nikula enum intel_display_power_domain domain, 366df0566a6SJani Nikula intel_wakeref_t wakeref) 367df0566a6SJani Nikula { 368df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, -1); 369df0566a6SJani Nikula } 370df0566a6SJani Nikula #endif 371df0566a6SJani Nikula 3726979cb9aSImre Deak void 3736979cb9aSImre Deak intel_display_power_get_in_set(struct drm_i915_private *i915, 3746979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 3756979cb9aSImre Deak enum intel_display_power_domain domain); 3766979cb9aSImre Deak 3776979cb9aSImre Deak bool 3786979cb9aSImre Deak intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, 3796979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 3806979cb9aSImre Deak enum intel_display_power_domain domain); 3816979cb9aSImre Deak 3826979cb9aSImre Deak void 3836979cb9aSImre Deak intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 3846979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set, 3856979cb9aSImre Deak u64 mask); 3866979cb9aSImre Deak 3876979cb9aSImre Deak static inline void 3886979cb9aSImre Deak intel_display_power_put_all_in_set(struct drm_i915_private *i915, 3896979cb9aSImre Deak struct intel_display_power_domain_set *power_domain_set) 3906979cb9aSImre Deak { 3916979cb9aSImre Deak intel_display_power_put_mask_in_set(i915, power_domain_set, power_domain_set->mask); 3926979cb9aSImre Deak } 3936979cb9aSImre Deak 39449f75634SMatt Roper /* 39549f75634SMatt Roper * FIXME: We should probably switch this to a 0-based scheme to be consistent 39649f75634SMatt Roper * with how we now name/number DBUF_CTL instances. 39749f75634SMatt Roper */ 3982570b7e3SStanislav Lisovskiy enum dbuf_slice { 3992570b7e3SStanislav Lisovskiy DBUF_S1, 4002570b7e3SStanislav Lisovskiy DBUF_S2, 4018398024bSMatt Roper DBUF_S3, 4028398024bSMatt Roper DBUF_S4, 4038435576bSStanislav Lisovskiy I915_MAX_DBUF_SLICES 4042570b7e3SStanislav Lisovskiy }; 4052570b7e3SStanislav Lisovskiy 40656f48c1dSVille Syrjälä void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 40756f48c1dSVille Syrjälä u8 req_slices); 40856f48c1dSVille Syrjälä 409df0566a6SJani Nikula #define with_intel_display_power(i915, domain, wf) \ 410df0566a6SJani Nikula for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 411df0566a6SJani Nikula intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 412df0566a6SJani Nikula 413df0566a6SJani Nikula void chv_phy_powergate_lanes(struct intel_encoder *encoder, 414df0566a6SJani Nikula bool override, unsigned int mask); 415df0566a6SJani Nikula bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 416df0566a6SJani Nikula enum dpio_channel ch, bool override); 417df0566a6SJani Nikula 418df0566a6SJani Nikula #endif /* __INTEL_DISPLAY_POWER_H__ */ 419