1df0566a6SJani Nikula /* SPDX-License-Identifier: MIT */ 2df0566a6SJani Nikula /* 3df0566a6SJani Nikula * Copyright © 2019 Intel Corporation 4df0566a6SJani Nikula */ 5df0566a6SJani Nikula 6df0566a6SJani Nikula #ifndef __INTEL_DISPLAY_POWER_H__ 7df0566a6SJani Nikula #define __INTEL_DISPLAY_POWER_H__ 8df0566a6SJani Nikula 9df0566a6SJani Nikula #include "intel_display.h" 10df0566a6SJani Nikula #include "intel_runtime_pm.h" 11df0566a6SJani Nikula #include "i915_reg.h" 12df0566a6SJani Nikula 13df0566a6SJani Nikula struct drm_i915_private; 14df0566a6SJani Nikula struct intel_encoder; 15df0566a6SJani Nikula 16df0566a6SJani Nikula enum intel_display_power_domain { 17df0566a6SJani Nikula POWER_DOMAIN_DISPLAY_CORE, 18df0566a6SJani Nikula POWER_DOMAIN_PIPE_A, 19df0566a6SJani Nikula POWER_DOMAIN_PIPE_B, 20df0566a6SJani Nikula POWER_DOMAIN_PIPE_C, 211db27a72SMika Kahola POWER_DOMAIN_PIPE_D, 22df0566a6SJani Nikula POWER_DOMAIN_PIPE_A_PANEL_FITTER, 23df0566a6SJani Nikula POWER_DOMAIN_PIPE_B_PANEL_FITTER, 24df0566a6SJani Nikula POWER_DOMAIN_PIPE_C_PANEL_FITTER, 251db27a72SMika Kahola POWER_DOMAIN_PIPE_D_PANEL_FITTER, 26df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_A, 27df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_B, 28df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_C, 291db27a72SMika Kahola POWER_DOMAIN_TRANSCODER_D, 30df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_EDP, 31276199e6SJosé Roberto de Souza /* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */ 32276199e6SJosé Roberto de Souza POWER_DOMAIN_TRANSCODER_VDSC_PW2, 33df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_A, 34df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_C, 35df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_A_LANES, 36df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_B_LANES, 37df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_C_LANES, 38df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_D_LANES, 39656409bbSImre Deak POWER_DOMAIN_PORT_DDI_TC1_LANES = POWER_DOMAIN_PORT_DDI_D_LANES, 40df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_E_LANES, 41656409bbSImre Deak POWER_DOMAIN_PORT_DDI_TC2_LANES = POWER_DOMAIN_PORT_DDI_E_LANES, 42df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_F_LANES, 43656409bbSImre Deak POWER_DOMAIN_PORT_DDI_TC3_LANES = POWER_DOMAIN_PORT_DDI_F_LANES, 44656409bbSImre Deak POWER_DOMAIN_PORT_DDI_TC4_LANES, 45656409bbSImre Deak POWER_DOMAIN_PORT_DDI_TC5_LANES, 46656409bbSImre Deak POWER_DOMAIN_PORT_DDI_TC6_LANES, 47df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_A_IO, 48df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_B_IO, 49df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_C_IO, 50df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_D_IO, 51656409bbSImre Deak POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO, 52df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_E_IO, 53656409bbSImre Deak POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO, 54df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_F_IO, 55656409bbSImre Deak POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO, 56656409bbSImre Deak POWER_DOMAIN_PORT_DDI_G_IO, 57656409bbSImre Deak POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO, 58656409bbSImre Deak POWER_DOMAIN_PORT_DDI_H_IO, 59656409bbSImre Deak POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO, 60656409bbSImre Deak POWER_DOMAIN_PORT_DDI_I_IO, 61656409bbSImre Deak POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO, 62df0566a6SJani Nikula POWER_DOMAIN_PORT_DSI, 63df0566a6SJani Nikula POWER_DOMAIN_PORT_CRT, 64df0566a6SJani Nikula POWER_DOMAIN_PORT_OTHER, 65df0566a6SJani Nikula POWER_DOMAIN_VGA, 66df0566a6SJani Nikula POWER_DOMAIN_AUDIO, 67df0566a6SJani Nikula POWER_DOMAIN_AUX_A, 68df0566a6SJani Nikula POWER_DOMAIN_AUX_B, 69df0566a6SJani Nikula POWER_DOMAIN_AUX_C, 70df0566a6SJani Nikula POWER_DOMAIN_AUX_D, 71656409bbSImre Deak POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D, 72df0566a6SJani Nikula POWER_DOMAIN_AUX_E, 73656409bbSImre Deak POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E, 74df0566a6SJani Nikula POWER_DOMAIN_AUX_F, 75656409bbSImre Deak POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F, 76656409bbSImre Deak POWER_DOMAIN_AUX_TC4, 77656409bbSImre Deak POWER_DOMAIN_AUX_TC5, 78656409bbSImre Deak POWER_DOMAIN_AUX_TC6, 79df0566a6SJani Nikula POWER_DOMAIN_AUX_IO_A, 80df0566a6SJani Nikula POWER_DOMAIN_AUX_TBT1, 81df0566a6SJani Nikula POWER_DOMAIN_AUX_TBT2, 82df0566a6SJani Nikula POWER_DOMAIN_AUX_TBT3, 83df0566a6SJani Nikula POWER_DOMAIN_AUX_TBT4, 84656409bbSImre Deak POWER_DOMAIN_AUX_TBT5, 85656409bbSImre Deak POWER_DOMAIN_AUX_TBT6, 86df0566a6SJani Nikula POWER_DOMAIN_GMBUS, 87df0566a6SJani Nikula POWER_DOMAIN_MODESET, 88df0566a6SJani Nikula POWER_DOMAIN_GT_IRQ, 89eef037eaSVivek Kasireddy POWER_DOMAIN_DPLL_DC_OFF, 90df0566a6SJani Nikula POWER_DOMAIN_INIT, 91df0566a6SJani Nikula 92df0566a6SJani Nikula POWER_DOMAIN_NUM, 93df0566a6SJani Nikula }; 94df0566a6SJani Nikula 953e5d0641SDaniele Ceraolo Spurio /* 963e5d0641SDaniele Ceraolo Spurio * i915_power_well_id: 973e5d0641SDaniele Ceraolo Spurio * 983e5d0641SDaniele Ceraolo Spurio * IDs used to look up power wells. Power wells accessed directly bypassing 993e5d0641SDaniele Ceraolo Spurio * the power domains framework must be assigned a unique ID. The rest of power 1003e5d0641SDaniele Ceraolo Spurio * wells must be assigned DISP_PW_ID_NONE. 1013e5d0641SDaniele Ceraolo Spurio */ 1023e5d0641SDaniele Ceraolo Spurio enum i915_power_well_id { 1033e5d0641SDaniele Ceraolo Spurio DISP_PW_ID_NONE, 1043e5d0641SDaniele Ceraolo Spurio 1053e5d0641SDaniele Ceraolo Spurio VLV_DISP_PW_DISP2D, 1063e5d0641SDaniele Ceraolo Spurio BXT_DISP_PW_DPIO_CMN_A, 1073e5d0641SDaniele Ceraolo Spurio VLV_DISP_PW_DPIO_CMN_BC, 1083e5d0641SDaniele Ceraolo Spurio GLK_DISP_PW_DPIO_CMN_C, 1093e5d0641SDaniele Ceraolo Spurio CHV_DISP_PW_DPIO_CMN_D, 1103e5d0641SDaniele Ceraolo Spurio HSW_DISP_PW_GLOBAL, 1113e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_MISC_IO, 1123e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_1, 1133e5d0641SDaniele Ceraolo Spurio SKL_DISP_PW_2, 1143e5d0641SDaniele Ceraolo Spurio }; 1153e5d0641SDaniele Ceraolo Spurio 116df0566a6SJani Nikula #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 117df0566a6SJani Nikula #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 118df0566a6SJani Nikula ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 119df0566a6SJani Nikula #define POWER_DOMAIN_TRANSCODER(tran) \ 120df0566a6SJani Nikula ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 121df0566a6SJani Nikula (tran) + POWER_DOMAIN_TRANSCODER_A) 122df0566a6SJani Nikula 123df0566a6SJani Nikula struct i915_power_well; 124df0566a6SJani Nikula 125df0566a6SJani Nikula struct i915_power_well_ops { 126df0566a6SJani Nikula /* 127df0566a6SJani Nikula * Synchronize the well's hw state to match the current sw state, for 128df0566a6SJani Nikula * example enable/disable it based on the current refcount. Called 129df0566a6SJani Nikula * during driver init and resume time, possibly after first calling 130df0566a6SJani Nikula * the enable/disable handlers. 131df0566a6SJani Nikula */ 132df0566a6SJani Nikula void (*sync_hw)(struct drm_i915_private *dev_priv, 133df0566a6SJani Nikula struct i915_power_well *power_well); 134df0566a6SJani Nikula /* 135df0566a6SJani Nikula * Enable the well and resources that depend on it (for example 136df0566a6SJani Nikula * interrupts located on the well). Called after the 0->1 refcount 137df0566a6SJani Nikula * transition. 138df0566a6SJani Nikula */ 139df0566a6SJani Nikula void (*enable)(struct drm_i915_private *dev_priv, 140df0566a6SJani Nikula struct i915_power_well *power_well); 141df0566a6SJani Nikula /* 142df0566a6SJani Nikula * Disable the well and resources that depend on it. Called after 143df0566a6SJani Nikula * the 1->0 refcount transition. 144df0566a6SJani Nikula */ 145df0566a6SJani Nikula void (*disable)(struct drm_i915_private *dev_priv, 146df0566a6SJani Nikula struct i915_power_well *power_well); 147df0566a6SJani Nikula /* Returns the hw enabled state. */ 148df0566a6SJani Nikula bool (*is_enabled)(struct drm_i915_private *dev_priv, 149df0566a6SJani Nikula struct i915_power_well *power_well); 150df0566a6SJani Nikula }; 151df0566a6SJani Nikula 152df0566a6SJani Nikula struct i915_power_well_regs { 153df0566a6SJani Nikula i915_reg_t bios; 154df0566a6SJani Nikula i915_reg_t driver; 155df0566a6SJani Nikula i915_reg_t kvmr; 156df0566a6SJani Nikula i915_reg_t debug; 157df0566a6SJani Nikula }; 158df0566a6SJani Nikula 159df0566a6SJani Nikula /* Power well structure for haswell */ 160df0566a6SJani Nikula struct i915_power_well_desc { 161df0566a6SJani Nikula const char *name; 162df0566a6SJani Nikula bool always_on; 163df0566a6SJani Nikula u64 domains; 164df0566a6SJani Nikula /* unique identifier for this power well */ 165df0566a6SJani Nikula enum i915_power_well_id id; 166df0566a6SJani Nikula /* 167df0566a6SJani Nikula * Arbitraty data associated with this power well. Platform and power 168df0566a6SJani Nikula * well specific. 169df0566a6SJani Nikula */ 170df0566a6SJani Nikula union { 171df0566a6SJani Nikula struct { 172df0566a6SJani Nikula /* 173df0566a6SJani Nikula * request/status flag index in the PUNIT power well 174df0566a6SJani Nikula * control/status registers. 175df0566a6SJani Nikula */ 176df0566a6SJani Nikula u8 idx; 177df0566a6SJani Nikula } vlv; 178df0566a6SJani Nikula struct { 179df0566a6SJani Nikula enum dpio_phy phy; 180df0566a6SJani Nikula } bxt; 181df0566a6SJani Nikula struct { 182df0566a6SJani Nikula const struct i915_power_well_regs *regs; 183df0566a6SJani Nikula /* 184df0566a6SJani Nikula * request/status flag index in the power well 185df0566a6SJani Nikula * constrol/status registers. 186df0566a6SJani Nikula */ 187df0566a6SJani Nikula u8 idx; 188df0566a6SJani Nikula /* Mask of pipes whose IRQ logic is backed by the pw */ 189df0566a6SJani Nikula u8 irq_pipe_mask; 190df0566a6SJani Nikula /* The pw is backing the VGA functionality */ 191df0566a6SJani Nikula bool has_vga:1; 192df0566a6SJani Nikula bool has_fuses:1; 193df0566a6SJani Nikula /* 194df0566a6SJani Nikula * The pw is for an ICL+ TypeC PHY port in 195df0566a6SJani Nikula * Thunderbolt mode. 196df0566a6SJani Nikula */ 197df0566a6SJani Nikula bool is_tc_tbt:1; 198df0566a6SJani Nikula } hsw; 199df0566a6SJani Nikula }; 200df0566a6SJani Nikula const struct i915_power_well_ops *ops; 201df0566a6SJani Nikula }; 202df0566a6SJani Nikula 203df0566a6SJani Nikula struct i915_power_well { 204df0566a6SJani Nikula const struct i915_power_well_desc *desc; 205df0566a6SJani Nikula /* power well enable/disable usage count */ 206df0566a6SJani Nikula int count; 207df0566a6SJani Nikula /* cached hw enabled state */ 208df0566a6SJani Nikula bool hw_enabled; 209df0566a6SJani Nikula }; 210df0566a6SJani Nikula 211df0566a6SJani Nikula struct i915_power_domains { 212df0566a6SJani Nikula /* 213df0566a6SJani Nikula * Power wells needed for initialization at driver init and suspend 214df0566a6SJani Nikula * time are on. They are kept on until after the first modeset. 215df0566a6SJani Nikula */ 216df0566a6SJani Nikula bool initializing; 217df0566a6SJani Nikula bool display_core_suspended; 218df0566a6SJani Nikula int power_well_count; 219df0566a6SJani Nikula 220df0566a6SJani Nikula intel_wakeref_t wakeref; 221df0566a6SJani Nikula 222df0566a6SJani Nikula struct mutex lock; 223df0566a6SJani Nikula int domain_use_count[POWER_DOMAIN_NUM]; 224df0566a6SJani Nikula 225df0566a6SJani Nikula struct delayed_work async_put_work; 226df0566a6SJani Nikula intel_wakeref_t async_put_wakeref; 227df0566a6SJani Nikula u64 async_put_domains[2]; 228df0566a6SJani Nikula 229df0566a6SJani Nikula struct i915_power_well *power_wells; 230df0566a6SJani Nikula }; 231df0566a6SJani Nikula 232df0566a6SJani Nikula #define for_each_power_domain(domain, mask) \ 233df0566a6SJani Nikula for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 234df0566a6SJani Nikula for_each_if(BIT_ULL(domain) & (mask)) 235df0566a6SJani Nikula 236df0566a6SJani Nikula #define for_each_power_well(__dev_priv, __power_well) \ 237df0566a6SJani Nikula for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ 238df0566a6SJani Nikula (__power_well) - (__dev_priv)->power_domains.power_wells < \ 239df0566a6SJani Nikula (__dev_priv)->power_domains.power_well_count; \ 240df0566a6SJani Nikula (__power_well)++) 241df0566a6SJani Nikula 242df0566a6SJani Nikula #define for_each_power_well_reverse(__dev_priv, __power_well) \ 243df0566a6SJani Nikula for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ 244df0566a6SJani Nikula (__dev_priv)->power_domains.power_well_count - 1; \ 245df0566a6SJani Nikula (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ 246df0566a6SJani Nikula (__power_well)--) 247df0566a6SJani Nikula 248df0566a6SJani Nikula #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ 249df0566a6SJani Nikula for_each_power_well(__dev_priv, __power_well) \ 250df0566a6SJani Nikula for_each_if((__power_well)->desc->domains & (__domain_mask)) 251df0566a6SJani Nikula 252df0566a6SJani Nikula #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ 253df0566a6SJani Nikula for_each_power_well_reverse(__dev_priv, __power_well) \ 254df0566a6SJani Nikula for_each_if((__power_well)->desc->domains & (__domain_mask)) 255df0566a6SJani Nikula 256df0566a6SJani Nikula int intel_power_domains_init(struct drm_i915_private *dev_priv); 257df0566a6SJani Nikula void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 258df0566a6SJani Nikula void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 25978dae1acSJanusz Krzysztofik void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 260df0566a6SJani Nikula void intel_power_domains_enable(struct drm_i915_private *dev_priv); 261df0566a6SJani Nikula void intel_power_domains_disable(struct drm_i915_private *dev_priv); 262df0566a6SJani Nikula void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 263df0566a6SJani Nikula enum i915_drm_suspend_mode); 264df0566a6SJani Nikula void intel_power_domains_resume(struct drm_i915_private *dev_priv); 265071b68ccSRodrigo Vivi 266071b68ccSRodrigo Vivi void intel_display_power_suspend_late(struct drm_i915_private *i915); 267071b68ccSRodrigo Vivi void intel_display_power_resume_early(struct drm_i915_private *i915); 268071b68ccSRodrigo Vivi void intel_display_power_suspend(struct drm_i915_private *i915); 269071b68ccSRodrigo Vivi void intel_display_power_resume(struct drm_i915_private *i915); 270df0566a6SJani Nikula 271df0566a6SJani Nikula const char * 272656409bbSImre Deak intel_display_power_domain_str(struct drm_i915_private *i915, 273656409bbSImre Deak enum intel_display_power_domain domain); 274df0566a6SJani Nikula 275df0566a6SJani Nikula bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 276df0566a6SJani Nikula enum intel_display_power_domain domain); 277df0566a6SJani Nikula bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 278df0566a6SJani Nikula enum intel_display_power_domain domain); 279df0566a6SJani Nikula intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 280df0566a6SJani Nikula enum intel_display_power_domain domain); 281df0566a6SJani Nikula intel_wakeref_t 282df0566a6SJani Nikula intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 283df0566a6SJani Nikula enum intel_display_power_domain domain); 284df0566a6SJani Nikula void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 285df0566a6SJani Nikula enum intel_display_power_domain domain); 286df0566a6SJani Nikula void __intel_display_power_put_async(struct drm_i915_private *i915, 287df0566a6SJani Nikula enum intel_display_power_domain domain, 288df0566a6SJani Nikula intel_wakeref_t wakeref); 289df0566a6SJani Nikula void intel_display_power_flush_work(struct drm_i915_private *i915); 290df0566a6SJani Nikula #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 291df0566a6SJani Nikula void intel_display_power_put(struct drm_i915_private *dev_priv, 292df0566a6SJani Nikula enum intel_display_power_domain domain, 293df0566a6SJani Nikula intel_wakeref_t wakeref); 294df0566a6SJani Nikula static inline void 295df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 296df0566a6SJani Nikula enum intel_display_power_domain domain, 297df0566a6SJani Nikula intel_wakeref_t wakeref) 298df0566a6SJani Nikula { 299df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, wakeref); 300df0566a6SJani Nikula } 301df0566a6SJani Nikula #else 302df0566a6SJani Nikula static inline void 303df0566a6SJani Nikula intel_display_power_put(struct drm_i915_private *i915, 304df0566a6SJani Nikula enum intel_display_power_domain domain, 305df0566a6SJani Nikula intel_wakeref_t wakeref) 306df0566a6SJani Nikula { 307df0566a6SJani Nikula intel_display_power_put_unchecked(i915, domain); 308df0566a6SJani Nikula } 309df0566a6SJani Nikula 310df0566a6SJani Nikula static inline void 311df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 312df0566a6SJani Nikula enum intel_display_power_domain domain, 313df0566a6SJani Nikula intel_wakeref_t wakeref) 314df0566a6SJani Nikula { 315df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, -1); 316df0566a6SJani Nikula } 317df0566a6SJani Nikula #endif 318df0566a6SJani Nikula 319df0566a6SJani Nikula #define with_intel_display_power(i915, domain, wf) \ 320df0566a6SJani Nikula for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 321df0566a6SJani Nikula intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 322df0566a6SJani Nikula 323df0566a6SJani Nikula void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, 324df0566a6SJani Nikula u8 req_slices); 325df0566a6SJani Nikula 326df0566a6SJani Nikula void chv_phy_powergate_lanes(struct intel_encoder *encoder, 327df0566a6SJani Nikula bool override, unsigned int mask); 328df0566a6SJani Nikula bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 329df0566a6SJani Nikula enum dpio_channel ch, bool override); 330df0566a6SJani Nikula 331df0566a6SJani Nikula #endif /* __INTEL_DISPLAY_POWER_H__ */ 332