1df0566a6SJani Nikula /* SPDX-License-Identifier: MIT */ 2df0566a6SJani Nikula /* 3df0566a6SJani Nikula * Copyright © 2019 Intel Corporation 4df0566a6SJani Nikula */ 5df0566a6SJani Nikula 6df0566a6SJani Nikula #ifndef __INTEL_DISPLAY_POWER_H__ 7df0566a6SJani Nikula #define __INTEL_DISPLAY_POWER_H__ 8df0566a6SJani Nikula 9df0566a6SJani Nikula #include "intel_display.h" 10df0566a6SJani Nikula #include "intel_runtime_pm.h" 11df0566a6SJani Nikula #include "i915_reg.h" 12df0566a6SJani Nikula 13df0566a6SJani Nikula struct drm_i915_private; 14df0566a6SJani Nikula struct intel_encoder; 15df0566a6SJani Nikula 16df0566a6SJani Nikula enum intel_display_power_domain { 17df0566a6SJani Nikula POWER_DOMAIN_DISPLAY_CORE, 18df0566a6SJani Nikula POWER_DOMAIN_PIPE_A, 19df0566a6SJani Nikula POWER_DOMAIN_PIPE_B, 20df0566a6SJani Nikula POWER_DOMAIN_PIPE_C, 21df0566a6SJani Nikula POWER_DOMAIN_PIPE_A_PANEL_FITTER, 22df0566a6SJani Nikula POWER_DOMAIN_PIPE_B_PANEL_FITTER, 23df0566a6SJani Nikula POWER_DOMAIN_PIPE_C_PANEL_FITTER, 24df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_A, 25df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_B, 26df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_C, 27df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_EDP, 28276199e6SJosé Roberto de Souza /* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */ 29276199e6SJosé Roberto de Souza POWER_DOMAIN_TRANSCODER_VDSC_PW2, 30df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_A, 31df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_C, 32df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_A_LANES, 33df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_B_LANES, 34df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_C_LANES, 35df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_D_LANES, 36df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_E_LANES, 37df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_F_LANES, 38df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_A_IO, 39df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_B_IO, 40df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_C_IO, 41df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_D_IO, 42df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_E_IO, 43df0566a6SJani Nikula POWER_DOMAIN_PORT_DDI_F_IO, 44df0566a6SJani Nikula POWER_DOMAIN_PORT_DSI, 45df0566a6SJani Nikula POWER_DOMAIN_PORT_CRT, 46df0566a6SJani Nikula POWER_DOMAIN_PORT_OTHER, 47df0566a6SJani Nikula POWER_DOMAIN_VGA, 48df0566a6SJani Nikula POWER_DOMAIN_AUDIO, 49df0566a6SJani Nikula POWER_DOMAIN_AUX_A, 50df0566a6SJani Nikula POWER_DOMAIN_AUX_B, 51df0566a6SJani Nikula POWER_DOMAIN_AUX_C, 52df0566a6SJani Nikula POWER_DOMAIN_AUX_D, 53df0566a6SJani Nikula POWER_DOMAIN_AUX_E, 54df0566a6SJani Nikula POWER_DOMAIN_AUX_F, 55df0566a6SJani Nikula POWER_DOMAIN_AUX_IO_A, 56df0566a6SJani Nikula POWER_DOMAIN_AUX_TBT1, 57df0566a6SJani Nikula POWER_DOMAIN_AUX_TBT2, 58df0566a6SJani Nikula POWER_DOMAIN_AUX_TBT3, 59df0566a6SJani Nikula POWER_DOMAIN_AUX_TBT4, 60df0566a6SJani Nikula POWER_DOMAIN_GMBUS, 61df0566a6SJani Nikula POWER_DOMAIN_MODESET, 62df0566a6SJani Nikula POWER_DOMAIN_GT_IRQ, 63eef037eaSVivek Kasireddy POWER_DOMAIN_DPLL_DC_OFF, 64df0566a6SJani Nikula POWER_DOMAIN_INIT, 65df0566a6SJani Nikula 66df0566a6SJani Nikula POWER_DOMAIN_NUM, 67df0566a6SJani Nikula }; 68df0566a6SJani Nikula 69df0566a6SJani Nikula #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 70df0566a6SJani Nikula #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 71df0566a6SJani Nikula ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 72df0566a6SJani Nikula #define POWER_DOMAIN_TRANSCODER(tran) \ 73df0566a6SJani Nikula ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 74df0566a6SJani Nikula (tran) + POWER_DOMAIN_TRANSCODER_A) 75df0566a6SJani Nikula 76df0566a6SJani Nikula struct i915_power_well; 77df0566a6SJani Nikula 78df0566a6SJani Nikula struct i915_power_well_ops { 79df0566a6SJani Nikula /* 80df0566a6SJani Nikula * Synchronize the well's hw state to match the current sw state, for 81df0566a6SJani Nikula * example enable/disable it based on the current refcount. Called 82df0566a6SJani Nikula * during driver init and resume time, possibly after first calling 83df0566a6SJani Nikula * the enable/disable handlers. 84df0566a6SJani Nikula */ 85df0566a6SJani Nikula void (*sync_hw)(struct drm_i915_private *dev_priv, 86df0566a6SJani Nikula struct i915_power_well *power_well); 87df0566a6SJani Nikula /* 88df0566a6SJani Nikula * Enable the well and resources that depend on it (for example 89df0566a6SJani Nikula * interrupts located on the well). Called after the 0->1 refcount 90df0566a6SJani Nikula * transition. 91df0566a6SJani Nikula */ 92df0566a6SJani Nikula void (*enable)(struct drm_i915_private *dev_priv, 93df0566a6SJani Nikula struct i915_power_well *power_well); 94df0566a6SJani Nikula /* 95df0566a6SJani Nikula * Disable the well and resources that depend on it. Called after 96df0566a6SJani Nikula * the 1->0 refcount transition. 97df0566a6SJani Nikula */ 98df0566a6SJani Nikula void (*disable)(struct drm_i915_private *dev_priv, 99df0566a6SJani Nikula struct i915_power_well *power_well); 100df0566a6SJani Nikula /* Returns the hw enabled state. */ 101df0566a6SJani Nikula bool (*is_enabled)(struct drm_i915_private *dev_priv, 102df0566a6SJani Nikula struct i915_power_well *power_well); 103df0566a6SJani Nikula }; 104df0566a6SJani Nikula 105df0566a6SJani Nikula struct i915_power_well_regs { 106df0566a6SJani Nikula i915_reg_t bios; 107df0566a6SJani Nikula i915_reg_t driver; 108df0566a6SJani Nikula i915_reg_t kvmr; 109df0566a6SJani Nikula i915_reg_t debug; 110df0566a6SJani Nikula }; 111df0566a6SJani Nikula 112df0566a6SJani Nikula /* Power well structure for haswell */ 113df0566a6SJani Nikula struct i915_power_well_desc { 114df0566a6SJani Nikula const char *name; 115df0566a6SJani Nikula bool always_on; 116df0566a6SJani Nikula u64 domains; 117df0566a6SJani Nikula /* unique identifier for this power well */ 118df0566a6SJani Nikula enum i915_power_well_id id; 119df0566a6SJani Nikula /* 120df0566a6SJani Nikula * Arbitraty data associated with this power well. Platform and power 121df0566a6SJani Nikula * well specific. 122df0566a6SJani Nikula */ 123df0566a6SJani Nikula union { 124df0566a6SJani Nikula struct { 125df0566a6SJani Nikula /* 126df0566a6SJani Nikula * request/status flag index in the PUNIT power well 127df0566a6SJani Nikula * control/status registers. 128df0566a6SJani Nikula */ 129df0566a6SJani Nikula u8 idx; 130df0566a6SJani Nikula } vlv; 131df0566a6SJani Nikula struct { 132df0566a6SJani Nikula enum dpio_phy phy; 133df0566a6SJani Nikula } bxt; 134df0566a6SJani Nikula struct { 135df0566a6SJani Nikula const struct i915_power_well_regs *regs; 136df0566a6SJani Nikula /* 137df0566a6SJani Nikula * request/status flag index in the power well 138df0566a6SJani Nikula * constrol/status registers. 139df0566a6SJani Nikula */ 140df0566a6SJani Nikula u8 idx; 141df0566a6SJani Nikula /* Mask of pipes whose IRQ logic is backed by the pw */ 142df0566a6SJani Nikula u8 irq_pipe_mask; 143df0566a6SJani Nikula /* The pw is backing the VGA functionality */ 144df0566a6SJani Nikula bool has_vga:1; 145df0566a6SJani Nikula bool has_fuses:1; 146df0566a6SJani Nikula /* 147df0566a6SJani Nikula * The pw is for an ICL+ TypeC PHY port in 148df0566a6SJani Nikula * Thunderbolt mode. 149df0566a6SJani Nikula */ 150df0566a6SJani Nikula bool is_tc_tbt:1; 151df0566a6SJani Nikula } hsw; 152df0566a6SJani Nikula }; 153df0566a6SJani Nikula const struct i915_power_well_ops *ops; 154df0566a6SJani Nikula }; 155df0566a6SJani Nikula 156df0566a6SJani Nikula struct i915_power_well { 157df0566a6SJani Nikula const struct i915_power_well_desc *desc; 158df0566a6SJani Nikula /* power well enable/disable usage count */ 159df0566a6SJani Nikula int count; 160df0566a6SJani Nikula /* cached hw enabled state */ 161df0566a6SJani Nikula bool hw_enabled; 162df0566a6SJani Nikula }; 163df0566a6SJani Nikula 164df0566a6SJani Nikula struct i915_power_domains { 165df0566a6SJani Nikula /* 166df0566a6SJani Nikula * Power wells needed for initialization at driver init and suspend 167df0566a6SJani Nikula * time are on. They are kept on until after the first modeset. 168df0566a6SJani Nikula */ 169df0566a6SJani Nikula bool initializing; 170df0566a6SJani Nikula bool display_core_suspended; 171df0566a6SJani Nikula int power_well_count; 172df0566a6SJani Nikula 173df0566a6SJani Nikula intel_wakeref_t wakeref; 174df0566a6SJani Nikula 175df0566a6SJani Nikula struct mutex lock; 176df0566a6SJani Nikula int domain_use_count[POWER_DOMAIN_NUM]; 177df0566a6SJani Nikula 178df0566a6SJani Nikula struct delayed_work async_put_work; 179df0566a6SJani Nikula intel_wakeref_t async_put_wakeref; 180df0566a6SJani Nikula u64 async_put_domains[2]; 181df0566a6SJani Nikula 182df0566a6SJani Nikula struct i915_power_well *power_wells; 183df0566a6SJani Nikula }; 184df0566a6SJani Nikula 185df0566a6SJani Nikula #define for_each_power_domain(domain, mask) \ 186df0566a6SJani Nikula for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 187df0566a6SJani Nikula for_each_if(BIT_ULL(domain) & (mask)) 188df0566a6SJani Nikula 189df0566a6SJani Nikula #define for_each_power_well(__dev_priv, __power_well) \ 190df0566a6SJani Nikula for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ 191df0566a6SJani Nikula (__power_well) - (__dev_priv)->power_domains.power_wells < \ 192df0566a6SJani Nikula (__dev_priv)->power_domains.power_well_count; \ 193df0566a6SJani Nikula (__power_well)++) 194df0566a6SJani Nikula 195df0566a6SJani Nikula #define for_each_power_well_reverse(__dev_priv, __power_well) \ 196df0566a6SJani Nikula for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ 197df0566a6SJani Nikula (__dev_priv)->power_domains.power_well_count - 1; \ 198df0566a6SJani Nikula (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ 199df0566a6SJani Nikula (__power_well)--) 200df0566a6SJani Nikula 201df0566a6SJani Nikula #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ 202df0566a6SJani Nikula for_each_power_well(__dev_priv, __power_well) \ 203df0566a6SJani Nikula for_each_if((__power_well)->desc->domains & (__domain_mask)) 204df0566a6SJani Nikula 205df0566a6SJani Nikula #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ 206df0566a6SJani Nikula for_each_power_well_reverse(__dev_priv, __power_well) \ 207df0566a6SJani Nikula for_each_if((__power_well)->desc->domains & (__domain_mask)) 208df0566a6SJani Nikula 209df0566a6SJani Nikula void skl_enable_dc6(struct drm_i915_private *dev_priv); 210df0566a6SJani Nikula void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv); 211df0566a6SJani Nikula void bxt_enable_dc9(struct drm_i915_private *dev_priv); 212df0566a6SJani Nikula void bxt_disable_dc9(struct drm_i915_private *dev_priv); 213df0566a6SJani Nikula void gen9_enable_dc5(struct drm_i915_private *dev_priv); 214df0566a6SJani Nikula 215df0566a6SJani Nikula int intel_power_domains_init(struct drm_i915_private *dev_priv); 216df0566a6SJani Nikula void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 217df0566a6SJani Nikula void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 218df0566a6SJani Nikula void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv); 219df0566a6SJani Nikula void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume); 220df0566a6SJani Nikula void icl_display_core_uninit(struct drm_i915_private *dev_priv); 221df0566a6SJani Nikula void intel_power_domains_enable(struct drm_i915_private *dev_priv); 222df0566a6SJani Nikula void intel_power_domains_disable(struct drm_i915_private *dev_priv); 223df0566a6SJani Nikula void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 224df0566a6SJani Nikula enum i915_drm_suspend_mode); 225df0566a6SJani Nikula void intel_power_domains_resume(struct drm_i915_private *dev_priv); 226df0566a6SJani Nikula void hsw_enable_pc8(struct drm_i915_private *dev_priv); 227df0566a6SJani Nikula void hsw_disable_pc8(struct drm_i915_private *dev_priv); 228df0566a6SJani Nikula void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume); 229df0566a6SJani Nikula void bxt_display_core_uninit(struct drm_i915_private *dev_priv); 230df0566a6SJani Nikula 231df0566a6SJani Nikula const char * 232df0566a6SJani Nikula intel_display_power_domain_str(enum intel_display_power_domain domain); 233df0566a6SJani Nikula 234df0566a6SJani Nikula bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 235df0566a6SJani Nikula enum intel_display_power_domain domain); 236df0566a6SJani Nikula bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 237df0566a6SJani Nikula enum intel_display_power_domain domain); 238df0566a6SJani Nikula intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 239df0566a6SJani Nikula enum intel_display_power_domain domain); 240df0566a6SJani Nikula intel_wakeref_t 241df0566a6SJani Nikula intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 242df0566a6SJani Nikula enum intel_display_power_domain domain); 243df0566a6SJani Nikula void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 244df0566a6SJani Nikula enum intel_display_power_domain domain); 245df0566a6SJani Nikula void __intel_display_power_put_async(struct drm_i915_private *i915, 246df0566a6SJani Nikula enum intel_display_power_domain domain, 247df0566a6SJani Nikula intel_wakeref_t wakeref); 248df0566a6SJani Nikula void intel_display_power_flush_work(struct drm_i915_private *i915); 249df0566a6SJani Nikula #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 250df0566a6SJani Nikula void intel_display_power_put(struct drm_i915_private *dev_priv, 251df0566a6SJani Nikula enum intel_display_power_domain domain, 252df0566a6SJani Nikula intel_wakeref_t wakeref); 253df0566a6SJani Nikula static inline void 254df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 255df0566a6SJani Nikula enum intel_display_power_domain domain, 256df0566a6SJani Nikula intel_wakeref_t wakeref) 257df0566a6SJani Nikula { 258df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, wakeref); 259df0566a6SJani Nikula } 260df0566a6SJani Nikula #else 261df0566a6SJani Nikula static inline void 262df0566a6SJani Nikula intel_display_power_put(struct drm_i915_private *i915, 263df0566a6SJani Nikula enum intel_display_power_domain domain, 264df0566a6SJani Nikula intel_wakeref_t wakeref) 265df0566a6SJani Nikula { 266df0566a6SJani Nikula intel_display_power_put_unchecked(i915, domain); 267df0566a6SJani Nikula } 268df0566a6SJani Nikula 269df0566a6SJani Nikula static inline void 270df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915, 271df0566a6SJani Nikula enum intel_display_power_domain domain, 272df0566a6SJani Nikula intel_wakeref_t wakeref) 273df0566a6SJani Nikula { 274df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, -1); 275df0566a6SJani Nikula } 276df0566a6SJani Nikula #endif 277df0566a6SJani Nikula 278df0566a6SJani Nikula #define with_intel_display_power(i915, domain, wf) \ 279df0566a6SJani Nikula for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 280df0566a6SJani Nikula intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 281df0566a6SJani Nikula 282df0566a6SJani Nikula void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, 283df0566a6SJani Nikula u8 req_slices); 284df0566a6SJani Nikula 285df0566a6SJani Nikula void chv_phy_powergate_lanes(struct intel_encoder *encoder, 286df0566a6SJani Nikula bool override, unsigned int mask); 287df0566a6SJani Nikula bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 288df0566a6SJani Nikula enum dpio_channel ch, bool override); 289df0566a6SJani Nikula 290df0566a6SJani Nikula #endif /* __INTEL_DISPLAY_POWER_H__ */ 291