1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include "i915_drv.h" 9 #include "i915_irq.h" 10 #include "i915_reg.h" 11 #include "intel_backlight_regs.h" 12 #include "intel_cdclk.h" 13 #include "intel_combo_phy.h" 14 #include "intel_de.h" 15 #include "intel_display_power.h" 16 #include "intel_display_power_map.h" 17 #include "intel_display_power_well.h" 18 #include "intel_display_types.h" 19 #include "intel_dmc.h" 20 #include "intel_mchbar_regs.h" 21 #include "intel_pch_refclk.h" 22 #include "intel_pcode.h" 23 #include "intel_pmdemand.h" 24 #include "intel_pps_regs.h" 25 #include "intel_snps_phy.h" 26 #include "skl_watermark.h" 27 #include "skl_watermark_regs.h" 28 #include "vlv_sideband.h" 29 30 #define for_each_power_domain_well(__dev_priv, __power_well, __domain) \ 31 for_each_power_well(__dev_priv, __power_well) \ 32 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 33 34 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \ 35 for_each_power_well_reverse(__dev_priv, __power_well) \ 36 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 37 38 const char * 39 intel_display_power_domain_str(enum intel_display_power_domain domain) 40 { 41 switch (domain) { 42 case POWER_DOMAIN_DISPLAY_CORE: 43 return "DISPLAY_CORE"; 44 case POWER_DOMAIN_PIPE_A: 45 return "PIPE_A"; 46 case POWER_DOMAIN_PIPE_B: 47 return "PIPE_B"; 48 case POWER_DOMAIN_PIPE_C: 49 return "PIPE_C"; 50 case POWER_DOMAIN_PIPE_D: 51 return "PIPE_D"; 52 case POWER_DOMAIN_PIPE_PANEL_FITTER_A: 53 return "PIPE_PANEL_FITTER_A"; 54 case POWER_DOMAIN_PIPE_PANEL_FITTER_B: 55 return "PIPE_PANEL_FITTER_B"; 56 case POWER_DOMAIN_PIPE_PANEL_FITTER_C: 57 return "PIPE_PANEL_FITTER_C"; 58 case POWER_DOMAIN_PIPE_PANEL_FITTER_D: 59 return "PIPE_PANEL_FITTER_D"; 60 case POWER_DOMAIN_TRANSCODER_A: 61 return "TRANSCODER_A"; 62 case POWER_DOMAIN_TRANSCODER_B: 63 return "TRANSCODER_B"; 64 case POWER_DOMAIN_TRANSCODER_C: 65 return "TRANSCODER_C"; 66 case POWER_DOMAIN_TRANSCODER_D: 67 return "TRANSCODER_D"; 68 case POWER_DOMAIN_TRANSCODER_EDP: 69 return "TRANSCODER_EDP"; 70 case POWER_DOMAIN_TRANSCODER_DSI_A: 71 return "TRANSCODER_DSI_A"; 72 case POWER_DOMAIN_TRANSCODER_DSI_C: 73 return "TRANSCODER_DSI_C"; 74 case POWER_DOMAIN_TRANSCODER_VDSC_PW2: 75 return "TRANSCODER_VDSC_PW2"; 76 case POWER_DOMAIN_PORT_DDI_LANES_A: 77 return "PORT_DDI_LANES_A"; 78 case POWER_DOMAIN_PORT_DDI_LANES_B: 79 return "PORT_DDI_LANES_B"; 80 case POWER_DOMAIN_PORT_DDI_LANES_C: 81 return "PORT_DDI_LANES_C"; 82 case POWER_DOMAIN_PORT_DDI_LANES_D: 83 return "PORT_DDI_LANES_D"; 84 case POWER_DOMAIN_PORT_DDI_LANES_E: 85 return "PORT_DDI_LANES_E"; 86 case POWER_DOMAIN_PORT_DDI_LANES_F: 87 return "PORT_DDI_LANES_F"; 88 case POWER_DOMAIN_PORT_DDI_LANES_TC1: 89 return "PORT_DDI_LANES_TC1"; 90 case POWER_DOMAIN_PORT_DDI_LANES_TC2: 91 return "PORT_DDI_LANES_TC2"; 92 case POWER_DOMAIN_PORT_DDI_LANES_TC3: 93 return "PORT_DDI_LANES_TC3"; 94 case POWER_DOMAIN_PORT_DDI_LANES_TC4: 95 return "PORT_DDI_LANES_TC4"; 96 case POWER_DOMAIN_PORT_DDI_LANES_TC5: 97 return "PORT_DDI_LANES_TC5"; 98 case POWER_DOMAIN_PORT_DDI_LANES_TC6: 99 return "PORT_DDI_LANES_TC6"; 100 case POWER_DOMAIN_PORT_DDI_IO_A: 101 return "PORT_DDI_IO_A"; 102 case POWER_DOMAIN_PORT_DDI_IO_B: 103 return "PORT_DDI_IO_B"; 104 case POWER_DOMAIN_PORT_DDI_IO_C: 105 return "PORT_DDI_IO_C"; 106 case POWER_DOMAIN_PORT_DDI_IO_D: 107 return "PORT_DDI_IO_D"; 108 case POWER_DOMAIN_PORT_DDI_IO_E: 109 return "PORT_DDI_IO_E"; 110 case POWER_DOMAIN_PORT_DDI_IO_F: 111 return "PORT_DDI_IO_F"; 112 case POWER_DOMAIN_PORT_DDI_IO_TC1: 113 return "PORT_DDI_IO_TC1"; 114 case POWER_DOMAIN_PORT_DDI_IO_TC2: 115 return "PORT_DDI_IO_TC2"; 116 case POWER_DOMAIN_PORT_DDI_IO_TC3: 117 return "PORT_DDI_IO_TC3"; 118 case POWER_DOMAIN_PORT_DDI_IO_TC4: 119 return "PORT_DDI_IO_TC4"; 120 case POWER_DOMAIN_PORT_DDI_IO_TC5: 121 return "PORT_DDI_IO_TC5"; 122 case POWER_DOMAIN_PORT_DDI_IO_TC6: 123 return "PORT_DDI_IO_TC6"; 124 case POWER_DOMAIN_PORT_DSI: 125 return "PORT_DSI"; 126 case POWER_DOMAIN_PORT_CRT: 127 return "PORT_CRT"; 128 case POWER_DOMAIN_PORT_OTHER: 129 return "PORT_OTHER"; 130 case POWER_DOMAIN_VGA: 131 return "VGA"; 132 case POWER_DOMAIN_AUDIO_MMIO: 133 return "AUDIO_MMIO"; 134 case POWER_DOMAIN_AUDIO_PLAYBACK: 135 return "AUDIO_PLAYBACK"; 136 case POWER_DOMAIN_AUX_IO_A: 137 return "AUX_IO_A"; 138 case POWER_DOMAIN_AUX_IO_B: 139 return "AUX_IO_B"; 140 case POWER_DOMAIN_AUX_IO_C: 141 return "AUX_IO_C"; 142 case POWER_DOMAIN_AUX_IO_D: 143 return "AUX_IO_D"; 144 case POWER_DOMAIN_AUX_IO_E: 145 return "AUX_IO_E"; 146 case POWER_DOMAIN_AUX_IO_F: 147 return "AUX_IO_F"; 148 case POWER_DOMAIN_AUX_A: 149 return "AUX_A"; 150 case POWER_DOMAIN_AUX_B: 151 return "AUX_B"; 152 case POWER_DOMAIN_AUX_C: 153 return "AUX_C"; 154 case POWER_DOMAIN_AUX_D: 155 return "AUX_D"; 156 case POWER_DOMAIN_AUX_E: 157 return "AUX_E"; 158 case POWER_DOMAIN_AUX_F: 159 return "AUX_F"; 160 case POWER_DOMAIN_AUX_USBC1: 161 return "AUX_USBC1"; 162 case POWER_DOMAIN_AUX_USBC2: 163 return "AUX_USBC2"; 164 case POWER_DOMAIN_AUX_USBC3: 165 return "AUX_USBC3"; 166 case POWER_DOMAIN_AUX_USBC4: 167 return "AUX_USBC4"; 168 case POWER_DOMAIN_AUX_USBC5: 169 return "AUX_USBC5"; 170 case POWER_DOMAIN_AUX_USBC6: 171 return "AUX_USBC6"; 172 case POWER_DOMAIN_AUX_TBT1: 173 return "AUX_TBT1"; 174 case POWER_DOMAIN_AUX_TBT2: 175 return "AUX_TBT2"; 176 case POWER_DOMAIN_AUX_TBT3: 177 return "AUX_TBT3"; 178 case POWER_DOMAIN_AUX_TBT4: 179 return "AUX_TBT4"; 180 case POWER_DOMAIN_AUX_TBT5: 181 return "AUX_TBT5"; 182 case POWER_DOMAIN_AUX_TBT6: 183 return "AUX_TBT6"; 184 case POWER_DOMAIN_GMBUS: 185 return "GMBUS"; 186 case POWER_DOMAIN_INIT: 187 return "INIT"; 188 case POWER_DOMAIN_MODESET: 189 return "MODESET"; 190 case POWER_DOMAIN_GT_IRQ: 191 return "GT_IRQ"; 192 case POWER_DOMAIN_DC_OFF: 193 return "DC_OFF"; 194 case POWER_DOMAIN_TC_COLD_OFF: 195 return "TC_COLD_OFF"; 196 default: 197 MISSING_CASE(domain); 198 return "?"; 199 } 200 } 201 202 /** 203 * __intel_display_power_is_enabled - unlocked check for a power domain 204 * @dev_priv: i915 device instance 205 * @domain: power domain to check 206 * 207 * This is the unlocked version of intel_display_power_is_enabled() and should 208 * only be used from error capture and recovery code where deadlocks are 209 * possible. 210 * 211 * Returns: 212 * True when the power domain is enabled, false otherwise. 213 */ 214 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 215 enum intel_display_power_domain domain) 216 { 217 struct i915_power_well *power_well; 218 bool is_enabled; 219 220 if (dev_priv->runtime_pm.suspended) 221 return false; 222 223 is_enabled = true; 224 225 for_each_power_domain_well_reverse(dev_priv, power_well, domain) { 226 if (intel_power_well_is_always_on(power_well)) 227 continue; 228 229 if (!intel_power_well_is_enabled_cached(power_well)) { 230 is_enabled = false; 231 break; 232 } 233 } 234 235 return is_enabled; 236 } 237 238 /** 239 * intel_display_power_is_enabled - check for a power domain 240 * @dev_priv: i915 device instance 241 * @domain: power domain to check 242 * 243 * This function can be used to check the hw power domain state. It is mostly 244 * used in hardware state readout functions. Everywhere else code should rely 245 * upon explicit power domain reference counting to ensure that the hardware 246 * block is powered up before accessing it. 247 * 248 * Callers must hold the relevant modesetting locks to ensure that concurrent 249 * threads can't disable the power well while the caller tries to read a few 250 * registers. 251 * 252 * Returns: 253 * True when the power domain is enabled, false otherwise. 254 */ 255 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 256 enum intel_display_power_domain domain) 257 { 258 struct i915_power_domains *power_domains; 259 bool ret; 260 261 power_domains = &dev_priv->display.power.domains; 262 263 mutex_lock(&power_domains->lock); 264 ret = __intel_display_power_is_enabled(dev_priv, domain); 265 mutex_unlock(&power_domains->lock); 266 267 return ret; 268 } 269 270 static u32 271 sanitize_target_dc_state(struct drm_i915_private *i915, 272 u32 target_dc_state) 273 { 274 struct i915_power_domains *power_domains = &i915->display.power.domains; 275 static const u32 states[] = { 276 DC_STATE_EN_UPTO_DC6, 277 DC_STATE_EN_UPTO_DC5, 278 DC_STATE_EN_DC3CO, 279 DC_STATE_DISABLE, 280 }; 281 int i; 282 283 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) { 284 if (target_dc_state != states[i]) 285 continue; 286 287 if (power_domains->allowed_dc_mask & target_dc_state) 288 break; 289 290 target_dc_state = states[i + 1]; 291 } 292 293 return target_dc_state; 294 } 295 296 /** 297 * intel_display_power_set_target_dc_state - Set target dc state. 298 * @dev_priv: i915 device 299 * @state: state which needs to be set as target_dc_state. 300 * 301 * This function set the "DC off" power well target_dc_state, 302 * based upon this target_dc_stste, "DC off" power well will 303 * enable desired DC state. 304 */ 305 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 306 u32 state) 307 { 308 struct i915_power_well *power_well; 309 bool dc_off_enabled; 310 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 311 312 mutex_lock(&power_domains->lock); 313 power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF); 314 315 if (drm_WARN_ON(&dev_priv->drm, !power_well)) 316 goto unlock; 317 318 state = sanitize_target_dc_state(dev_priv, state); 319 320 if (state == power_domains->target_dc_state) 321 goto unlock; 322 323 dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well); 324 /* 325 * If DC off power well is disabled, need to enable and disable the 326 * DC off power well to effect target DC state. 327 */ 328 if (!dc_off_enabled) 329 intel_power_well_enable(dev_priv, power_well); 330 331 power_domains->target_dc_state = state; 332 333 if (!dc_off_enabled) 334 intel_power_well_disable(dev_priv, power_well); 335 336 unlock: 337 mutex_unlock(&power_domains->lock); 338 } 339 340 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0)) 341 342 static void __async_put_domains_mask(struct i915_power_domains *power_domains, 343 struct intel_power_domain_mask *mask) 344 { 345 bitmap_or(mask->bits, 346 power_domains->async_put_domains[0].bits, 347 power_domains->async_put_domains[1].bits, 348 POWER_DOMAIN_NUM); 349 } 350 351 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 352 353 static bool 354 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 355 { 356 struct drm_i915_private *i915 = container_of(power_domains, 357 struct drm_i915_private, 358 display.power.domains); 359 360 return !drm_WARN_ON(&i915->drm, 361 bitmap_intersects(power_domains->async_put_domains[0].bits, 362 power_domains->async_put_domains[1].bits, 363 POWER_DOMAIN_NUM)); 364 } 365 366 static bool 367 __async_put_domains_state_ok(struct i915_power_domains *power_domains) 368 { 369 struct drm_i915_private *i915 = container_of(power_domains, 370 struct drm_i915_private, 371 display.power.domains); 372 struct intel_power_domain_mask async_put_mask; 373 enum intel_display_power_domain domain; 374 bool err = false; 375 376 err |= !assert_async_put_domain_masks_disjoint(power_domains); 377 __async_put_domains_mask(power_domains, &async_put_mask); 378 err |= drm_WARN_ON(&i915->drm, 379 !!power_domains->async_put_wakeref != 380 !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)); 381 382 for_each_power_domain(domain, &async_put_mask) 383 err |= drm_WARN_ON(&i915->drm, 384 power_domains->domain_use_count[domain] != 1); 385 386 return !err; 387 } 388 389 static void print_power_domains(struct i915_power_domains *power_domains, 390 const char *prefix, struct intel_power_domain_mask *mask) 391 { 392 struct drm_i915_private *i915 = container_of(power_domains, 393 struct drm_i915_private, 394 display.power.domains); 395 enum intel_display_power_domain domain; 396 397 drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM)); 398 for_each_power_domain(domain, mask) 399 drm_dbg(&i915->drm, "%s use_count %d\n", 400 intel_display_power_domain_str(domain), 401 power_domains->domain_use_count[domain]); 402 } 403 404 static void 405 print_async_put_domains_state(struct i915_power_domains *power_domains) 406 { 407 struct drm_i915_private *i915 = container_of(power_domains, 408 struct drm_i915_private, 409 display.power.domains); 410 411 drm_dbg(&i915->drm, "async_put_wakeref %u\n", 412 power_domains->async_put_wakeref); 413 414 print_power_domains(power_domains, "async_put_domains[0]", 415 &power_domains->async_put_domains[0]); 416 print_power_domains(power_domains, "async_put_domains[1]", 417 &power_domains->async_put_domains[1]); 418 } 419 420 static void 421 verify_async_put_domains_state(struct i915_power_domains *power_domains) 422 { 423 if (!__async_put_domains_state_ok(power_domains)) 424 print_async_put_domains_state(power_domains); 425 } 426 427 #else 428 429 static void 430 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 431 { 432 } 433 434 static void 435 verify_async_put_domains_state(struct i915_power_domains *power_domains) 436 { 437 } 438 439 #endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */ 440 441 static void async_put_domains_mask(struct i915_power_domains *power_domains, 442 struct intel_power_domain_mask *mask) 443 444 { 445 assert_async_put_domain_masks_disjoint(power_domains); 446 447 __async_put_domains_mask(power_domains, mask); 448 } 449 450 static void 451 async_put_domains_clear_domain(struct i915_power_domains *power_domains, 452 enum intel_display_power_domain domain) 453 { 454 assert_async_put_domain_masks_disjoint(power_domains); 455 456 clear_bit(domain, power_domains->async_put_domains[0].bits); 457 clear_bit(domain, power_domains->async_put_domains[1].bits); 458 } 459 460 static bool 461 intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv, 462 enum intel_display_power_domain domain) 463 { 464 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 465 struct intel_power_domain_mask async_put_mask; 466 bool ret = false; 467 468 async_put_domains_mask(power_domains, &async_put_mask); 469 if (!test_bit(domain, async_put_mask.bits)) 470 goto out_verify; 471 472 async_put_domains_clear_domain(power_domains, domain); 473 474 ret = true; 475 476 async_put_domains_mask(power_domains, &async_put_mask); 477 if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)) 478 goto out_verify; 479 480 cancel_delayed_work(&power_domains->async_put_work); 481 intel_runtime_pm_put_raw(&dev_priv->runtime_pm, 482 fetch_and_zero(&power_domains->async_put_wakeref)); 483 out_verify: 484 verify_async_put_domains_state(power_domains); 485 486 return ret; 487 } 488 489 static void 490 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, 491 enum intel_display_power_domain domain) 492 { 493 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 494 struct i915_power_well *power_well; 495 496 if (intel_display_power_grab_async_put_ref(dev_priv, domain)) 497 return; 498 499 for_each_power_domain_well(dev_priv, power_well, domain) 500 intel_power_well_get(dev_priv, power_well); 501 502 power_domains->domain_use_count[domain]++; 503 } 504 505 /** 506 * intel_display_power_get - grab a power domain reference 507 * @dev_priv: i915 device instance 508 * @domain: power domain to reference 509 * 510 * This function grabs a power domain reference for @domain and ensures that the 511 * power domain and all its parents are powered up. Therefore users should only 512 * grab a reference to the innermost power domain they need. 513 * 514 * Any power domain reference obtained by this function must have a symmetric 515 * call to intel_display_power_put() to release the reference again. 516 */ 517 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 518 enum intel_display_power_domain domain) 519 { 520 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 521 intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 522 523 mutex_lock(&power_domains->lock); 524 __intel_display_power_get_domain(dev_priv, domain); 525 mutex_unlock(&power_domains->lock); 526 527 return wakeref; 528 } 529 530 /** 531 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 532 * @dev_priv: i915 device instance 533 * @domain: power domain to reference 534 * 535 * This function grabs a power domain reference for @domain and ensures that the 536 * power domain and all its parents are powered up. Therefore users should only 537 * grab a reference to the innermost power domain they need. 538 * 539 * Any power domain reference obtained by this function must have a symmetric 540 * call to intel_display_power_put() to release the reference again. 541 */ 542 intel_wakeref_t 543 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 544 enum intel_display_power_domain domain) 545 { 546 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 547 intel_wakeref_t wakeref; 548 bool is_enabled; 549 550 wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm); 551 if (!wakeref) 552 return false; 553 554 mutex_lock(&power_domains->lock); 555 556 if (__intel_display_power_is_enabled(dev_priv, domain)) { 557 __intel_display_power_get_domain(dev_priv, domain); 558 is_enabled = true; 559 } else { 560 is_enabled = false; 561 } 562 563 mutex_unlock(&power_domains->lock); 564 565 if (!is_enabled) { 566 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 567 wakeref = 0; 568 } 569 570 return wakeref; 571 } 572 573 static void 574 __intel_display_power_put_domain(struct drm_i915_private *dev_priv, 575 enum intel_display_power_domain domain) 576 { 577 struct i915_power_domains *power_domains; 578 struct i915_power_well *power_well; 579 const char *name = intel_display_power_domain_str(domain); 580 struct intel_power_domain_mask async_put_mask; 581 582 power_domains = &dev_priv->display.power.domains; 583 584 drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain], 585 "Use count on domain %s is already zero\n", 586 name); 587 async_put_domains_mask(power_domains, &async_put_mask); 588 drm_WARN(&dev_priv->drm, 589 test_bit(domain, async_put_mask.bits), 590 "Async disabling of domain %s is pending\n", 591 name); 592 593 power_domains->domain_use_count[domain]--; 594 595 for_each_power_domain_well_reverse(dev_priv, power_well, domain) 596 intel_power_well_put(dev_priv, power_well); 597 } 598 599 static void __intel_display_power_put(struct drm_i915_private *dev_priv, 600 enum intel_display_power_domain domain) 601 { 602 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 603 604 mutex_lock(&power_domains->lock); 605 __intel_display_power_put_domain(dev_priv, domain); 606 mutex_unlock(&power_domains->lock); 607 } 608 609 static void 610 queue_async_put_domains_work(struct i915_power_domains *power_domains, 611 intel_wakeref_t wakeref) 612 { 613 struct drm_i915_private *i915 = container_of(power_domains, 614 struct drm_i915_private, 615 display.power.domains); 616 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref); 617 power_domains->async_put_wakeref = wakeref; 618 drm_WARN_ON(&i915->drm, !queue_delayed_work(system_unbound_wq, 619 &power_domains->async_put_work, 620 msecs_to_jiffies(100))); 621 } 622 623 static void 624 release_async_put_domains(struct i915_power_domains *power_domains, 625 struct intel_power_domain_mask *mask) 626 { 627 struct drm_i915_private *dev_priv = 628 container_of(power_domains, struct drm_i915_private, 629 display.power.domains); 630 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 631 enum intel_display_power_domain domain; 632 intel_wakeref_t wakeref; 633 634 /* 635 * The caller must hold already raw wakeref, upgrade that to a proper 636 * wakeref to make the state checker happy about the HW access during 637 * power well disabling. 638 */ 639 assert_rpm_raw_wakeref_held(rpm); 640 wakeref = intel_runtime_pm_get(rpm); 641 642 for_each_power_domain(domain, mask) { 643 /* Clear before put, so put's sanity check is happy. */ 644 async_put_domains_clear_domain(power_domains, domain); 645 __intel_display_power_put_domain(dev_priv, domain); 646 } 647 648 intel_runtime_pm_put(rpm, wakeref); 649 } 650 651 static void 652 intel_display_power_put_async_work(struct work_struct *work) 653 { 654 struct drm_i915_private *dev_priv = 655 container_of(work, struct drm_i915_private, 656 display.power.domains.async_put_work.work); 657 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 658 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 659 intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(rpm); 660 intel_wakeref_t old_work_wakeref = 0; 661 662 mutex_lock(&power_domains->lock); 663 664 /* 665 * Bail out if all the domain refs pending to be released were grabbed 666 * by subsequent gets or a flush_work. 667 */ 668 old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); 669 if (!old_work_wakeref) 670 goto out_verify; 671 672 release_async_put_domains(power_domains, 673 &power_domains->async_put_domains[0]); 674 675 /* Requeue the work if more domains were async put meanwhile. */ 676 if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) { 677 bitmap_copy(power_domains->async_put_domains[0].bits, 678 power_domains->async_put_domains[1].bits, 679 POWER_DOMAIN_NUM); 680 bitmap_zero(power_domains->async_put_domains[1].bits, 681 POWER_DOMAIN_NUM); 682 queue_async_put_domains_work(power_domains, 683 fetch_and_zero(&new_work_wakeref)); 684 } else { 685 /* 686 * Cancel the work that got queued after this one got dequeued, 687 * since here we released the corresponding async-put reference. 688 */ 689 cancel_delayed_work(&power_domains->async_put_work); 690 } 691 692 out_verify: 693 verify_async_put_domains_state(power_domains); 694 695 mutex_unlock(&power_domains->lock); 696 697 if (old_work_wakeref) 698 intel_runtime_pm_put_raw(rpm, old_work_wakeref); 699 if (new_work_wakeref) 700 intel_runtime_pm_put_raw(rpm, new_work_wakeref); 701 } 702 703 /** 704 * __intel_display_power_put_async - release a power domain reference asynchronously 705 * @i915: i915 device instance 706 * @domain: power domain to reference 707 * @wakeref: wakeref acquired for the reference that is being released 708 * 709 * This function drops the power domain reference obtained by 710 * intel_display_power_get*() and schedules a work to power down the 711 * corresponding hardware block if this is the last reference. 712 */ 713 void __intel_display_power_put_async(struct drm_i915_private *i915, 714 enum intel_display_power_domain domain, 715 intel_wakeref_t wakeref) 716 { 717 struct i915_power_domains *power_domains = &i915->display.power.domains; 718 struct intel_runtime_pm *rpm = &i915->runtime_pm; 719 intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm); 720 721 mutex_lock(&power_domains->lock); 722 723 if (power_domains->domain_use_count[domain] > 1) { 724 __intel_display_power_put_domain(i915, domain); 725 726 goto out_verify; 727 } 728 729 drm_WARN_ON(&i915->drm, power_domains->domain_use_count[domain] != 1); 730 731 /* Let a pending work requeue itself or queue a new one. */ 732 if (power_domains->async_put_wakeref) { 733 set_bit(domain, power_domains->async_put_domains[1].bits); 734 } else { 735 set_bit(domain, power_domains->async_put_domains[0].bits); 736 queue_async_put_domains_work(power_domains, 737 fetch_and_zero(&work_wakeref)); 738 } 739 740 out_verify: 741 verify_async_put_domains_state(power_domains); 742 743 mutex_unlock(&power_domains->lock); 744 745 if (work_wakeref) 746 intel_runtime_pm_put_raw(rpm, work_wakeref); 747 748 intel_runtime_pm_put(rpm, wakeref); 749 } 750 751 /** 752 * intel_display_power_flush_work - flushes the async display power disabling work 753 * @i915: i915 device instance 754 * 755 * Flushes any pending work that was scheduled by a preceding 756 * intel_display_power_put_async() call, completing the disabling of the 757 * corresponding power domains. 758 * 759 * Note that the work handler function may still be running after this 760 * function returns; to ensure that the work handler isn't running use 761 * intel_display_power_flush_work_sync() instead. 762 */ 763 void intel_display_power_flush_work(struct drm_i915_private *i915) 764 { 765 struct i915_power_domains *power_domains = &i915->display.power.domains; 766 struct intel_power_domain_mask async_put_mask; 767 intel_wakeref_t work_wakeref; 768 769 mutex_lock(&power_domains->lock); 770 771 work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); 772 if (!work_wakeref) 773 goto out_verify; 774 775 async_put_domains_mask(power_domains, &async_put_mask); 776 release_async_put_domains(power_domains, &async_put_mask); 777 cancel_delayed_work(&power_domains->async_put_work); 778 779 out_verify: 780 verify_async_put_domains_state(power_domains); 781 782 mutex_unlock(&power_domains->lock); 783 784 if (work_wakeref) 785 intel_runtime_pm_put_raw(&i915->runtime_pm, work_wakeref); 786 } 787 788 /** 789 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work 790 * @i915: i915 device instance 791 * 792 * Like intel_display_power_flush_work(), but also ensure that the work 793 * handler function is not running any more when this function returns. 794 */ 795 static void 796 intel_display_power_flush_work_sync(struct drm_i915_private *i915) 797 { 798 struct i915_power_domains *power_domains = &i915->display.power.domains; 799 800 intel_display_power_flush_work(i915); 801 cancel_delayed_work_sync(&power_domains->async_put_work); 802 803 verify_async_put_domains_state(power_domains); 804 805 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref); 806 } 807 808 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 809 /** 810 * intel_display_power_put - release a power domain reference 811 * @dev_priv: i915 device instance 812 * @domain: power domain to reference 813 * @wakeref: wakeref acquired for the reference that is being released 814 * 815 * This function drops the power domain reference obtained by 816 * intel_display_power_get() and might power down the corresponding hardware 817 * block right away if this is the last reference. 818 */ 819 void intel_display_power_put(struct drm_i915_private *dev_priv, 820 enum intel_display_power_domain domain, 821 intel_wakeref_t wakeref) 822 { 823 __intel_display_power_put(dev_priv, domain); 824 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 825 } 826 #else 827 /** 828 * intel_display_power_put_unchecked - release an unchecked power domain reference 829 * @dev_priv: i915 device instance 830 * @domain: power domain to reference 831 * 832 * This function drops the power domain reference obtained by 833 * intel_display_power_get() and might power down the corresponding hardware 834 * block right away if this is the last reference. 835 * 836 * This function is only for the power domain code's internal use to suppress wakeref 837 * tracking when the correspondig debug kconfig option is disabled, should not 838 * be used otherwise. 839 */ 840 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 841 enum intel_display_power_domain domain) 842 { 843 __intel_display_power_put(dev_priv, domain); 844 intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); 845 } 846 #endif 847 848 void 849 intel_display_power_get_in_set(struct drm_i915_private *i915, 850 struct intel_display_power_domain_set *power_domain_set, 851 enum intel_display_power_domain domain) 852 { 853 intel_wakeref_t __maybe_unused wf; 854 855 drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits)); 856 857 wf = intel_display_power_get(i915, domain); 858 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 859 power_domain_set->wakerefs[domain] = wf; 860 #endif 861 set_bit(domain, power_domain_set->mask.bits); 862 } 863 864 bool 865 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, 866 struct intel_display_power_domain_set *power_domain_set, 867 enum intel_display_power_domain domain) 868 { 869 intel_wakeref_t wf; 870 871 drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits)); 872 873 wf = intel_display_power_get_if_enabled(i915, domain); 874 if (!wf) 875 return false; 876 877 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 878 power_domain_set->wakerefs[domain] = wf; 879 #endif 880 set_bit(domain, power_domain_set->mask.bits); 881 882 return true; 883 } 884 885 void 886 intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 887 struct intel_display_power_domain_set *power_domain_set, 888 struct intel_power_domain_mask *mask) 889 { 890 enum intel_display_power_domain domain; 891 892 drm_WARN_ON(&i915->drm, 893 !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM)); 894 895 for_each_power_domain(domain, mask) { 896 intel_wakeref_t __maybe_unused wf = -1; 897 898 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 899 wf = fetch_and_zero(&power_domain_set->wakerefs[domain]); 900 #endif 901 intel_display_power_put(i915, domain, wf); 902 clear_bit(domain, power_domain_set->mask.bits); 903 } 904 } 905 906 static int 907 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 908 int disable_power_well) 909 { 910 if (disable_power_well >= 0) 911 return !!disable_power_well; 912 913 return 1; 914 } 915 916 static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, 917 int enable_dc) 918 { 919 u32 mask; 920 int requested_dc; 921 int max_dc; 922 923 if (!HAS_DISPLAY(dev_priv)) 924 return 0; 925 926 if (IS_DG2(dev_priv)) 927 max_dc = 1; 928 else if (IS_DG1(dev_priv)) 929 max_dc = 3; 930 else if (DISPLAY_VER(dev_priv) >= 12) 931 max_dc = 4; 932 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 933 max_dc = 1; 934 else if (DISPLAY_VER(dev_priv) >= 9) 935 max_dc = 2; 936 else 937 max_dc = 0; 938 939 /* 940 * DC9 has a separate HW flow from the rest of the DC states, 941 * not depending on the DMC firmware. It's needed by system 942 * suspend/resume, so allow it unconditionally. 943 */ 944 mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || 945 DISPLAY_VER(dev_priv) >= 11 ? 946 DC_STATE_EN_DC9 : 0; 947 948 if (!dev_priv->params.disable_power_well) 949 max_dc = 0; 950 951 if (enable_dc >= 0 && enable_dc <= max_dc) { 952 requested_dc = enable_dc; 953 } else if (enable_dc == -1) { 954 requested_dc = max_dc; 955 } else if (enable_dc > max_dc && enable_dc <= 4) { 956 drm_dbg_kms(&dev_priv->drm, 957 "Adjusting requested max DC state (%d->%d)\n", 958 enable_dc, max_dc); 959 requested_dc = max_dc; 960 } else { 961 drm_err(&dev_priv->drm, 962 "Unexpected value for enable_dc (%d)\n", enable_dc); 963 requested_dc = max_dc; 964 } 965 966 switch (requested_dc) { 967 case 4: 968 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6; 969 break; 970 case 3: 971 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5; 972 break; 973 case 2: 974 mask |= DC_STATE_EN_UPTO_DC6; 975 break; 976 case 1: 977 mask |= DC_STATE_EN_UPTO_DC5; 978 break; 979 } 980 981 drm_dbg_kms(&dev_priv->drm, "Allowed DC state mask %02x\n", mask); 982 983 return mask; 984 } 985 986 /** 987 * intel_power_domains_init - initializes the power domain structures 988 * @dev_priv: i915 device instance 989 * 990 * Initializes the power domain structures for @dev_priv depending upon the 991 * supported platform. 992 */ 993 int intel_power_domains_init(struct drm_i915_private *dev_priv) 994 { 995 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 996 997 dev_priv->params.disable_power_well = 998 sanitize_disable_power_well_option(dev_priv, 999 dev_priv->params.disable_power_well); 1000 power_domains->allowed_dc_mask = 1001 get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc); 1002 1003 power_domains->target_dc_state = 1004 sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 1005 1006 mutex_init(&power_domains->lock); 1007 1008 INIT_DELAYED_WORK(&power_domains->async_put_work, 1009 intel_display_power_put_async_work); 1010 1011 return intel_display_power_map_init(power_domains); 1012 } 1013 1014 /** 1015 * intel_power_domains_cleanup - clean up power domains resources 1016 * @dev_priv: i915 device instance 1017 * 1018 * Release any resources acquired by intel_power_domains_init() 1019 */ 1020 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv) 1021 { 1022 intel_display_power_map_cleanup(&dev_priv->display.power.domains); 1023 } 1024 1025 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 1026 { 1027 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1028 struct i915_power_well *power_well; 1029 1030 mutex_lock(&power_domains->lock); 1031 for_each_power_well(dev_priv, power_well) 1032 intel_power_well_sync_hw(dev_priv, power_well); 1033 mutex_unlock(&power_domains->lock); 1034 } 1035 1036 static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv, 1037 enum dbuf_slice slice, bool enable) 1038 { 1039 i915_reg_t reg = DBUF_CTL_S(slice); 1040 bool state; 1041 1042 intel_de_rmw(dev_priv, reg, DBUF_POWER_REQUEST, 1043 enable ? DBUF_POWER_REQUEST : 0); 1044 intel_de_posting_read(dev_priv, reg); 1045 udelay(10); 1046 1047 state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE; 1048 drm_WARN(&dev_priv->drm, enable != state, 1049 "DBuf slice %d power %s timeout!\n", 1050 slice, str_enable_disable(enable)); 1051 } 1052 1053 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 1054 u8 req_slices) 1055 { 1056 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1057 u8 slice_mask = DISPLAY_INFO(dev_priv)->dbuf.slice_mask; 1058 enum dbuf_slice slice; 1059 1060 drm_WARN(&dev_priv->drm, req_slices & ~slice_mask, 1061 "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n", 1062 req_slices, slice_mask); 1063 1064 drm_dbg_kms(&dev_priv->drm, "Updating dbuf slices to 0x%x\n", 1065 req_slices); 1066 1067 /* 1068 * Might be running this in parallel to gen9_dc_off_power_well_enable 1069 * being called from intel_dp_detect for instance, 1070 * which causes assertion triggered by race condition, 1071 * as gen9_assert_dbuf_enabled might preempt this when registers 1072 * were already updated, while dev_priv was not. 1073 */ 1074 mutex_lock(&power_domains->lock); 1075 1076 for_each_dbuf_slice(dev_priv, slice) 1077 gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice)); 1078 1079 dev_priv->display.dbuf.enabled_slices = req_slices; 1080 1081 mutex_unlock(&power_domains->lock); 1082 } 1083 1084 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) 1085 { 1086 u8 slices_mask; 1087 1088 dev_priv->display.dbuf.enabled_slices = 1089 intel_enabled_dbuf_slices_mask(dev_priv); 1090 1091 slices_mask = BIT(DBUF_S1) | dev_priv->display.dbuf.enabled_slices; 1092 1093 if (DISPLAY_VER(dev_priv) >= 14) 1094 intel_pmdemand_program_dbuf(dev_priv, slices_mask); 1095 1096 /* 1097 * Just power up at least 1 slice, we will 1098 * figure out later which slices we have and what we need. 1099 */ 1100 gen9_dbuf_slices_update(dev_priv, slices_mask); 1101 } 1102 1103 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) 1104 { 1105 gen9_dbuf_slices_update(dev_priv, 0); 1106 1107 if (DISPLAY_VER(dev_priv) >= 14) 1108 intel_pmdemand_program_dbuf(dev_priv, 0); 1109 } 1110 1111 static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv) 1112 { 1113 enum dbuf_slice slice; 1114 1115 if (IS_ALDERLAKE_P(dev_priv)) 1116 return; 1117 1118 for_each_dbuf_slice(dev_priv, slice) 1119 intel_de_rmw(dev_priv, DBUF_CTL_S(slice), 1120 DBUF_TRACKER_STATE_SERVICE_MASK, 1121 DBUF_TRACKER_STATE_SERVICE(8)); 1122 } 1123 1124 static void icl_mbus_init(struct drm_i915_private *dev_priv) 1125 { 1126 unsigned long abox_regs = DISPLAY_INFO(dev_priv)->abox_mask; 1127 u32 mask, val, i; 1128 1129 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 1130 return; 1131 1132 mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | 1133 MBUS_ABOX_BT_CREDIT_POOL2_MASK | 1134 MBUS_ABOX_B_CREDIT_MASK | 1135 MBUS_ABOX_BW_CREDIT_MASK; 1136 val = MBUS_ABOX_BT_CREDIT_POOL1(16) | 1137 MBUS_ABOX_BT_CREDIT_POOL2(16) | 1138 MBUS_ABOX_B_CREDIT(1) | 1139 MBUS_ABOX_BW_CREDIT(1); 1140 1141 /* 1142 * gen12 platforms that use abox1 and abox2 for pixel data reads still 1143 * expect us to program the abox_ctl0 register as well, even though 1144 * we don't have to program other instance-0 registers like BW_BUDDY. 1145 */ 1146 if (DISPLAY_VER(dev_priv) == 12) 1147 abox_regs |= BIT(0); 1148 1149 for_each_set_bit(i, &abox_regs, sizeof(abox_regs)) 1150 intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val); 1151 } 1152 1153 static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) 1154 { 1155 u32 val = intel_de_read(dev_priv, LCPLL_CTL); 1156 1157 /* 1158 * The LCPLL register should be turned on by the BIOS. For now 1159 * let's just check its state and print errors in case 1160 * something is wrong. Don't even try to turn it on. 1161 */ 1162 1163 if (val & LCPLL_CD_SOURCE_FCLK) 1164 drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n"); 1165 1166 if (val & LCPLL_PLL_DISABLE) 1167 drm_err(&dev_priv->drm, "LCPLL is disabled\n"); 1168 1169 if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC) 1170 drm_err(&dev_priv->drm, "LCPLL not using non-SSC reference\n"); 1171 } 1172 1173 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) 1174 { 1175 struct intel_crtc *crtc; 1176 1177 for_each_intel_crtc(&dev_priv->drm, crtc) 1178 I915_STATE_WARN(dev_priv, crtc->active, 1179 "CRTC for pipe %c enabled\n", 1180 pipe_name(crtc->pipe)); 1181 1182 I915_STATE_WARN(dev_priv, intel_de_read(dev_priv, HSW_PWR_WELL_CTL2), 1183 "Display power well on\n"); 1184 I915_STATE_WARN(dev_priv, 1185 intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE, 1186 "SPLL enabled\n"); 1187 I915_STATE_WARN(dev_priv, 1188 intel_de_read(dev_priv, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, 1189 "WRPLL1 enabled\n"); 1190 I915_STATE_WARN(dev_priv, 1191 intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, 1192 "WRPLL2 enabled\n"); 1193 I915_STATE_WARN(dev_priv, 1194 intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON, 1195 "Panel power on\n"); 1196 I915_STATE_WARN(dev_priv, 1197 intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, 1198 "CPU PWM1 enabled\n"); 1199 if (IS_HASWELL(dev_priv)) 1200 I915_STATE_WARN(dev_priv, 1201 intel_de_read(dev_priv, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, 1202 "CPU PWM2 enabled\n"); 1203 I915_STATE_WARN(dev_priv, 1204 intel_de_read(dev_priv, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, 1205 "PCH PWM1 enabled\n"); 1206 I915_STATE_WARN(dev_priv, 1207 (intel_de_read(dev_priv, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 1208 "Utility pin enabled in PWM mode\n"); 1209 I915_STATE_WARN(dev_priv, 1210 intel_de_read(dev_priv, PCH_GTC_CTL) & PCH_GTC_ENABLE, 1211 "PCH GTC enabled\n"); 1212 1213 /* 1214 * In theory we can still leave IRQs enabled, as long as only the HPD 1215 * interrupts remain enabled. We used to check for that, but since it's 1216 * gen-specific and since we only disable LCPLL after we fully disable 1217 * the interrupts, the check below should be enough. 1218 */ 1219 I915_STATE_WARN(dev_priv, intel_irqs_enabled(dev_priv), 1220 "IRQs enabled\n"); 1221 } 1222 1223 static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv) 1224 { 1225 if (IS_HASWELL(dev_priv)) 1226 return intel_de_read(dev_priv, D_COMP_HSW); 1227 else 1228 return intel_de_read(dev_priv, D_COMP_BDW); 1229 } 1230 1231 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val) 1232 { 1233 if (IS_HASWELL(dev_priv)) { 1234 if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val)) 1235 drm_dbg_kms(&dev_priv->drm, 1236 "Failed to write to D_COMP\n"); 1237 } else { 1238 intel_de_write(dev_priv, D_COMP_BDW, val); 1239 intel_de_posting_read(dev_priv, D_COMP_BDW); 1240 } 1241 } 1242 1243 /* 1244 * This function implements pieces of two sequences from BSpec: 1245 * - Sequence for display software to disable LCPLL 1246 * - Sequence for display software to allow package C8+ 1247 * The steps implemented here are just the steps that actually touch the LCPLL 1248 * register. Callers should take care of disabling all the display engine 1249 * functions, doing the mode unset, fixing interrupts, etc. 1250 */ 1251 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, 1252 bool switch_to_fclk, bool allow_power_down) 1253 { 1254 u32 val; 1255 1256 assert_can_disable_lcpll(dev_priv); 1257 1258 val = intel_de_read(dev_priv, LCPLL_CTL); 1259 1260 if (switch_to_fclk) { 1261 val |= LCPLL_CD_SOURCE_FCLK; 1262 intel_de_write(dev_priv, LCPLL_CTL, val); 1263 1264 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & 1265 LCPLL_CD_SOURCE_FCLK_DONE, 1)) 1266 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); 1267 1268 val = intel_de_read(dev_priv, LCPLL_CTL); 1269 } 1270 1271 val |= LCPLL_PLL_DISABLE; 1272 intel_de_write(dev_priv, LCPLL_CTL, val); 1273 intel_de_posting_read(dev_priv, LCPLL_CTL); 1274 1275 if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) 1276 drm_err(&dev_priv->drm, "LCPLL still locked\n"); 1277 1278 val = hsw_read_dcomp(dev_priv); 1279 val |= D_COMP_COMP_DISABLE; 1280 hsw_write_dcomp(dev_priv, val); 1281 ndelay(100); 1282 1283 if (wait_for((hsw_read_dcomp(dev_priv) & 1284 D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) 1285 drm_err(&dev_priv->drm, "D_COMP RCOMP still in progress\n"); 1286 1287 if (allow_power_down) { 1288 intel_de_rmw(dev_priv, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW); 1289 intel_de_posting_read(dev_priv, LCPLL_CTL); 1290 } 1291 } 1292 1293 /* 1294 * Fully restores LCPLL, disallowing power down and switching back to LCPLL 1295 * source. 1296 */ 1297 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) 1298 { 1299 u32 val; 1300 1301 val = intel_de_read(dev_priv, LCPLL_CTL); 1302 1303 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | 1304 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) 1305 return; 1306 1307 /* 1308 * Make sure we're not on PC8 state before disabling PC8, otherwise 1309 * we'll hang the machine. To prevent PC8 state, just enable force_wake. 1310 */ 1311 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); 1312 1313 if (val & LCPLL_POWER_DOWN_ALLOW) { 1314 val &= ~LCPLL_POWER_DOWN_ALLOW; 1315 intel_de_write(dev_priv, LCPLL_CTL, val); 1316 intel_de_posting_read(dev_priv, LCPLL_CTL); 1317 } 1318 1319 val = hsw_read_dcomp(dev_priv); 1320 val |= D_COMP_COMP_FORCE; 1321 val &= ~D_COMP_COMP_DISABLE; 1322 hsw_write_dcomp(dev_priv, val); 1323 1324 val = intel_de_read(dev_priv, LCPLL_CTL); 1325 val &= ~LCPLL_PLL_DISABLE; 1326 intel_de_write(dev_priv, LCPLL_CTL, val); 1327 1328 if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) 1329 drm_err(&dev_priv->drm, "LCPLL not locked yet\n"); 1330 1331 if (val & LCPLL_CD_SOURCE_FCLK) { 1332 intel_de_rmw(dev_priv, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); 1333 1334 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & 1335 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 1336 drm_err(&dev_priv->drm, 1337 "Switching back to LCPLL failed\n"); 1338 } 1339 1340 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); 1341 1342 intel_update_cdclk(dev_priv); 1343 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 1344 } 1345 1346 /* 1347 * Package states C8 and deeper are really deep PC states that can only be 1348 * reached when all the devices on the system allow it, so even if the graphics 1349 * device allows PC8+, it doesn't mean the system will actually get to these 1350 * states. Our driver only allows PC8+ when going into runtime PM. 1351 * 1352 * The requirements for PC8+ are that all the outputs are disabled, the power 1353 * well is disabled and most interrupts are disabled, and these are also 1354 * requirements for runtime PM. When these conditions are met, we manually do 1355 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk 1356 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard 1357 * hang the machine. 1358 * 1359 * When we really reach PC8 or deeper states (not just when we allow it) we lose 1360 * the state of some registers, so when we come back from PC8+ we need to 1361 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't 1362 * need to take care of the registers kept by RC6. Notice that this happens even 1363 * if we don't put the device in PCI D3 state (which is what currently happens 1364 * because of the runtime PM support). 1365 * 1366 * For more, read "Display Sequences for Package C8" on the hardware 1367 * documentation. 1368 */ 1369 static void hsw_enable_pc8(struct drm_i915_private *dev_priv) 1370 { 1371 drm_dbg_kms(&dev_priv->drm, "Enabling package C8+\n"); 1372 1373 if (HAS_PCH_LPT_LP(dev_priv)) 1374 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 1375 PCH_LP_PARTITION_LEVEL_DISABLE, 0); 1376 1377 lpt_disable_clkout_dp(dev_priv); 1378 hsw_disable_lcpll(dev_priv, true, true); 1379 } 1380 1381 static void hsw_disable_pc8(struct drm_i915_private *dev_priv) 1382 { 1383 drm_dbg_kms(&dev_priv->drm, "Disabling package C8+\n"); 1384 1385 hsw_restore_lcpll(dev_priv); 1386 intel_init_pch_refclk(dev_priv); 1387 1388 if (HAS_PCH_LPT_LP(dev_priv)) 1389 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 1390 0, PCH_LP_PARTITION_LEVEL_DISABLE); 1391 } 1392 1393 static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, 1394 bool enable) 1395 { 1396 i915_reg_t reg; 1397 u32 reset_bits; 1398 1399 if (IS_IVYBRIDGE(dev_priv)) { 1400 reg = GEN7_MSG_CTL; 1401 reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK; 1402 } else { 1403 reg = HSW_NDE_RSTWRN_OPT; 1404 reset_bits = RESET_PCH_HANDSHAKE_ENABLE; 1405 } 1406 1407 if (DISPLAY_VER(dev_priv) >= 14) 1408 reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN; 1409 1410 intel_de_rmw(dev_priv, reg, reset_bits, enable ? reset_bits : 0); 1411 } 1412 1413 static void skl_display_core_init(struct drm_i915_private *dev_priv, 1414 bool resume) 1415 { 1416 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1417 struct i915_power_well *well; 1418 1419 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 1420 1421 /* enable PCH reset handshake */ 1422 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); 1423 1424 if (!HAS_DISPLAY(dev_priv)) 1425 return; 1426 1427 /* enable PG1 and Misc I/O */ 1428 mutex_lock(&power_domains->lock); 1429 1430 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1431 intel_power_well_enable(dev_priv, well); 1432 1433 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 1434 intel_power_well_enable(dev_priv, well); 1435 1436 mutex_unlock(&power_domains->lock); 1437 1438 intel_cdclk_init_hw(dev_priv); 1439 1440 gen9_dbuf_enable(dev_priv); 1441 1442 if (resume) 1443 intel_dmc_load_program(dev_priv); 1444 } 1445 1446 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 1447 { 1448 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1449 struct i915_power_well *well; 1450 1451 if (!HAS_DISPLAY(dev_priv)) 1452 return; 1453 1454 gen9_disable_dc_states(dev_priv); 1455 /* TODO: disable DMC program */ 1456 1457 gen9_dbuf_disable(dev_priv); 1458 1459 intel_cdclk_uninit_hw(dev_priv); 1460 1461 /* The spec doesn't call for removing the reset handshake flag */ 1462 /* disable PG1 and Misc I/O */ 1463 1464 mutex_lock(&power_domains->lock); 1465 1466 /* 1467 * BSpec says to keep the MISC IO power well enabled here, only 1468 * remove our request for power well 1. 1469 * Note that even though the driver's request is removed power well 1 1470 * may stay enabled after this due to DMC's own request on it. 1471 */ 1472 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1473 intel_power_well_disable(dev_priv, well); 1474 1475 mutex_unlock(&power_domains->lock); 1476 1477 usleep_range(10, 30); /* 10 us delay per Bspec */ 1478 } 1479 1480 static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume) 1481 { 1482 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1483 struct i915_power_well *well; 1484 1485 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 1486 1487 /* 1488 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 1489 * or else the reset will hang because there is no PCH to respond. 1490 * Move the handshake programming to initialization sequence. 1491 * Previously was left up to BIOS. 1492 */ 1493 intel_pch_reset_handshake(dev_priv, false); 1494 1495 if (!HAS_DISPLAY(dev_priv)) 1496 return; 1497 1498 /* Enable PG1 */ 1499 mutex_lock(&power_domains->lock); 1500 1501 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1502 intel_power_well_enable(dev_priv, well); 1503 1504 mutex_unlock(&power_domains->lock); 1505 1506 intel_cdclk_init_hw(dev_priv); 1507 1508 gen9_dbuf_enable(dev_priv); 1509 1510 if (resume) 1511 intel_dmc_load_program(dev_priv); 1512 } 1513 1514 static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) 1515 { 1516 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1517 struct i915_power_well *well; 1518 1519 if (!HAS_DISPLAY(dev_priv)) 1520 return; 1521 1522 gen9_disable_dc_states(dev_priv); 1523 /* TODO: disable DMC program */ 1524 1525 gen9_dbuf_disable(dev_priv); 1526 1527 intel_cdclk_uninit_hw(dev_priv); 1528 1529 /* The spec doesn't call for removing the reset handshake flag */ 1530 1531 /* 1532 * Disable PW1 (PG1). 1533 * Note that even though the driver's request is removed power well 1 1534 * may stay enabled after this due to DMC's own request on it. 1535 */ 1536 mutex_lock(&power_domains->lock); 1537 1538 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1539 intel_power_well_disable(dev_priv, well); 1540 1541 mutex_unlock(&power_domains->lock); 1542 1543 usleep_range(10, 30); /* 10 us delay per Bspec */ 1544 } 1545 1546 struct buddy_page_mask { 1547 u32 page_mask; 1548 u8 type; 1549 u8 num_channels; 1550 }; 1551 1552 static const struct buddy_page_mask tgl_buddy_page_masks[] = { 1553 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF }, 1554 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0xF }, 1555 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C }, 1556 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1C }, 1557 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F }, 1558 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x1E }, 1559 { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 }, 1560 { .num_channels = 4, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x38 }, 1561 {} 1562 }; 1563 1564 static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = { 1565 { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 }, 1566 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0x1 }, 1567 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0x1 }, 1568 { .num_channels = 1, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1 }, 1569 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 }, 1570 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x3 }, 1571 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x3 }, 1572 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x3 }, 1573 {} 1574 }; 1575 1576 static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) 1577 { 1578 enum intel_dram_type type = dev_priv->dram_info.type; 1579 u8 num_channels = dev_priv->dram_info.num_channels; 1580 const struct buddy_page_mask *table; 1581 unsigned long abox_mask = DISPLAY_INFO(dev_priv)->abox_mask; 1582 int config, i; 1583 1584 /* BW_BUDDY registers are not used on dgpu's beyond DG1 */ 1585 if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv)) 1586 return; 1587 1588 if (IS_ALDERLAKE_S(dev_priv) || 1589 IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1590 /* Wa_1409767108 */ 1591 table = wa_1409767108_buddy_page_masks; 1592 else 1593 table = tgl_buddy_page_masks; 1594 1595 for (config = 0; table[config].page_mask != 0; config++) 1596 if (table[config].num_channels == num_channels && 1597 table[config].type == type) 1598 break; 1599 1600 if (table[config].page_mask == 0) { 1601 drm_dbg(&dev_priv->drm, 1602 "Unknown memory configuration; disabling address buddy logic.\n"); 1603 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) 1604 intel_de_write(dev_priv, BW_BUDDY_CTL(i), 1605 BW_BUDDY_DISABLE); 1606 } else { 1607 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) { 1608 intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), 1609 table[config].page_mask); 1610 1611 /* Wa_22010178259:tgl,dg1,rkl,adl-s */ 1612 if (DISPLAY_VER(dev_priv) == 12) 1613 intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), 1614 BW_BUDDY_TLB_REQ_TIMER_MASK, 1615 BW_BUDDY_TLB_REQ_TIMER(0x8)); 1616 } 1617 } 1618 } 1619 1620 static void icl_display_core_init(struct drm_i915_private *dev_priv, 1621 bool resume) 1622 { 1623 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1624 struct i915_power_well *well; 1625 1626 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 1627 1628 /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */ 1629 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && 1630 INTEL_PCH_TYPE(dev_priv) < PCH_DG1) 1631 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, 1632 PCH_DPMGUNIT_CLOCK_GATE_DISABLE); 1633 1634 /* 1. Enable PCH reset handshake. */ 1635 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); 1636 1637 if (!HAS_DISPLAY(dev_priv)) 1638 return; 1639 1640 /* 2. Initialize all combo phys */ 1641 intel_combo_phy_init(dev_priv); 1642 1643 /* 1644 * 3. Enable Power Well 1 (PG1). 1645 * The AUX IO power wells will be enabled on demand. 1646 */ 1647 mutex_lock(&power_domains->lock); 1648 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1649 intel_power_well_enable(dev_priv, well); 1650 mutex_unlock(&power_domains->lock); 1651 1652 if (DISPLAY_VER(dev_priv) == 14) 1653 intel_de_rmw(dev_priv, DC_STATE_EN, 1654 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0); 1655 1656 /* 4. Enable CDCLK. */ 1657 intel_cdclk_init_hw(dev_priv); 1658 1659 if (DISPLAY_VER(dev_priv) >= 12) 1660 gen12_dbuf_slices_config(dev_priv); 1661 1662 /* 5. Enable DBUF. */ 1663 gen9_dbuf_enable(dev_priv); 1664 1665 /* 6. Setup MBUS. */ 1666 icl_mbus_init(dev_priv); 1667 1668 /* 7. Program arbiter BW_BUDDY registers */ 1669 if (DISPLAY_VER(dev_priv) >= 12) 1670 tgl_bw_buddy_init(dev_priv); 1671 1672 /* 8. Ensure PHYs have completed calibration and adaptation */ 1673 if (IS_DG2(dev_priv)) 1674 intel_snps_phy_wait_for_calibration(dev_priv); 1675 1676 if (resume) 1677 intel_dmc_load_program(dev_priv); 1678 1679 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p */ 1680 if (DISPLAY_VER(dev_priv) >= 12) 1681 intel_de_rmw(dev_priv, GEN11_CHICKEN_DCPR_2, 0, 1682 DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | 1683 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR); 1684 1685 /* Wa_14011503030:xelpd */ 1686 if (DISPLAY_VER(dev_priv) >= 13) 1687 intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0); 1688 } 1689 1690 static void icl_display_core_uninit(struct drm_i915_private *dev_priv) 1691 { 1692 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1693 struct i915_power_well *well; 1694 1695 if (!HAS_DISPLAY(dev_priv)) 1696 return; 1697 1698 gen9_disable_dc_states(dev_priv); 1699 intel_dmc_disable_program(dev_priv); 1700 1701 /* 1. Disable all display engine functions -> aready done */ 1702 1703 /* 2. Disable DBUF */ 1704 gen9_dbuf_disable(dev_priv); 1705 1706 /* 3. Disable CD clock */ 1707 intel_cdclk_uninit_hw(dev_priv); 1708 1709 if (DISPLAY_VER(dev_priv) == 14) 1710 intel_de_rmw(dev_priv, DC_STATE_EN, 0, 1711 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH); 1712 1713 /* 1714 * 4. Disable Power Well 1 (PG1). 1715 * The AUX IO power wells are toggled on demand, so they are already 1716 * disabled at this point. 1717 */ 1718 mutex_lock(&power_domains->lock); 1719 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1720 intel_power_well_disable(dev_priv, well); 1721 mutex_unlock(&power_domains->lock); 1722 1723 /* 5. */ 1724 intel_combo_phy_uninit(dev_priv); 1725 } 1726 1727 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 1728 { 1729 struct i915_power_well *cmn_bc = 1730 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 1731 struct i915_power_well *cmn_d = 1732 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D); 1733 1734 /* 1735 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 1736 * workaround never ever read DISPLAY_PHY_CONTROL, and 1737 * instead maintain a shadow copy ourselves. Use the actual 1738 * power well state and lane status to reconstruct the 1739 * expected initial value. 1740 */ 1741 dev_priv->display.power.chv_phy_control = 1742 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 1743 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 1744 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 1745 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 1746 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 1747 1748 /* 1749 * If all lanes are disabled we leave the override disabled 1750 * with all power down bits cleared to match the state we 1751 * would use after disabling the port. Otherwise enable the 1752 * override and set the lane powerdown bits accding to the 1753 * current lane status. 1754 */ 1755 if (intel_power_well_is_enabled(dev_priv, cmn_bc)) { 1756 u32 status = intel_de_read(dev_priv, DPLL(PIPE_A)); 1757 unsigned int mask; 1758 1759 mask = status & DPLL_PORTB_READY_MASK; 1760 if (mask == 0xf) 1761 mask = 0x0; 1762 else 1763 dev_priv->display.power.chv_phy_control |= 1764 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 1765 1766 dev_priv->display.power.chv_phy_control |= 1767 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 1768 1769 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 1770 if (mask == 0xf) 1771 mask = 0x0; 1772 else 1773 dev_priv->display.power.chv_phy_control |= 1774 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 1775 1776 dev_priv->display.power.chv_phy_control |= 1777 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 1778 1779 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 1780 1781 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = false; 1782 } else { 1783 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true; 1784 } 1785 1786 if (intel_power_well_is_enabled(dev_priv, cmn_d)) { 1787 u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS); 1788 unsigned int mask; 1789 1790 mask = status & DPLL_PORTD_READY_MASK; 1791 1792 if (mask == 0xf) 1793 mask = 0x0; 1794 else 1795 dev_priv->display.power.chv_phy_control |= 1796 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 1797 1798 dev_priv->display.power.chv_phy_control |= 1799 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 1800 1801 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 1802 1803 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = false; 1804 } else { 1805 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = true; 1806 } 1807 1808 drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n", 1809 dev_priv->display.power.chv_phy_control); 1810 1811 /* Defer application of initial phy_control to enabling the powerwell */ 1812 } 1813 1814 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 1815 { 1816 struct i915_power_well *cmn = 1817 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 1818 struct i915_power_well *disp2d = 1819 lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D); 1820 1821 /* If the display might be already active skip this */ 1822 if (intel_power_well_is_enabled(dev_priv, cmn) && 1823 intel_power_well_is_enabled(dev_priv, disp2d) && 1824 intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST) 1825 return; 1826 1827 drm_dbg_kms(&dev_priv->drm, "toggling display PHY side reset\n"); 1828 1829 /* cmnlane needs DPLL registers */ 1830 intel_power_well_enable(dev_priv, disp2d); 1831 1832 /* 1833 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 1834 * Need to assert and de-assert PHY SB reset by gating the 1835 * common lane power, then un-gating it. 1836 * Simply ungating isn't enough to reset the PHY enough to get 1837 * ports and lanes running. 1838 */ 1839 intel_power_well_disable(dev_priv, cmn); 1840 } 1841 1842 static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0) 1843 { 1844 bool ret; 1845 1846 vlv_punit_get(dev_priv); 1847 ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; 1848 vlv_punit_put(dev_priv); 1849 1850 return ret; 1851 } 1852 1853 static void assert_ved_power_gated(struct drm_i915_private *dev_priv) 1854 { 1855 drm_WARN(&dev_priv->drm, 1856 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0), 1857 "VED not power gated\n"); 1858 } 1859 1860 static void assert_isp_power_gated(struct drm_i915_private *dev_priv) 1861 { 1862 static const struct pci_device_id isp_ids[] = { 1863 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)}, 1864 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)}, 1865 {} 1866 }; 1867 1868 drm_WARN(&dev_priv->drm, !pci_dev_present(isp_ids) && 1869 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0), 1870 "ISP not power gated\n"); 1871 } 1872 1873 static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv); 1874 1875 /** 1876 * intel_power_domains_init_hw - initialize hardware power domain state 1877 * @i915: i915 device instance 1878 * @resume: Called from resume code paths or not 1879 * 1880 * This function initializes the hardware power domain state and enables all 1881 * power wells belonging to the INIT power domain. Power wells in other 1882 * domains (and not in the INIT domain) are referenced or disabled by 1883 * intel_modeset_readout_hw_state(). After that the reference count of each 1884 * power well must match its HW enabled state, see 1885 * intel_power_domains_verify_state(). 1886 * 1887 * It will return with power domains disabled (to be enabled later by 1888 * intel_power_domains_enable()) and must be paired with 1889 * intel_power_domains_driver_remove(). 1890 */ 1891 void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) 1892 { 1893 struct i915_power_domains *power_domains = &i915->display.power.domains; 1894 1895 power_domains->initializing = true; 1896 1897 if (DISPLAY_VER(i915) >= 11) { 1898 icl_display_core_init(i915, resume); 1899 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 1900 bxt_display_core_init(i915, resume); 1901 } else if (DISPLAY_VER(i915) == 9) { 1902 skl_display_core_init(i915, resume); 1903 } else if (IS_CHERRYVIEW(i915)) { 1904 mutex_lock(&power_domains->lock); 1905 chv_phy_control_init(i915); 1906 mutex_unlock(&power_domains->lock); 1907 assert_isp_power_gated(i915); 1908 } else if (IS_VALLEYVIEW(i915)) { 1909 mutex_lock(&power_domains->lock); 1910 vlv_cmnlane_wa(i915); 1911 mutex_unlock(&power_domains->lock); 1912 assert_ved_power_gated(i915); 1913 assert_isp_power_gated(i915); 1914 } else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) { 1915 hsw_assert_cdclk(i915); 1916 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915)); 1917 } else if (IS_IVYBRIDGE(i915)) { 1918 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915)); 1919 } 1920 1921 /* 1922 * Keep all power wells enabled for any dependent HW access during 1923 * initialization and to make sure we keep BIOS enabled display HW 1924 * resources powered until display HW readout is complete. We drop 1925 * this reference in intel_power_domains_enable(). 1926 */ 1927 drm_WARN_ON(&i915->drm, power_domains->init_wakeref); 1928 power_domains->init_wakeref = 1929 intel_display_power_get(i915, POWER_DOMAIN_INIT); 1930 1931 /* Disable power support if the user asked so. */ 1932 if (!i915->params.disable_power_well) { 1933 drm_WARN_ON(&i915->drm, power_domains->disable_wakeref); 1934 i915->display.power.domains.disable_wakeref = intel_display_power_get(i915, 1935 POWER_DOMAIN_INIT); 1936 } 1937 intel_power_domains_sync_hw(i915); 1938 1939 power_domains->initializing = false; 1940 } 1941 1942 /** 1943 * intel_power_domains_driver_remove - deinitialize hw power domain state 1944 * @i915: i915 device instance 1945 * 1946 * De-initializes the display power domain HW state. It also ensures that the 1947 * device stays powered up so that the driver can be reloaded. 1948 * 1949 * It must be called with power domains already disabled (after a call to 1950 * intel_power_domains_disable()) and must be paired with 1951 * intel_power_domains_init_hw(). 1952 */ 1953 void intel_power_domains_driver_remove(struct drm_i915_private *i915) 1954 { 1955 intel_wakeref_t wakeref __maybe_unused = 1956 fetch_and_zero(&i915->display.power.domains.init_wakeref); 1957 1958 /* Remove the refcount we took to keep power well support disabled. */ 1959 if (!i915->params.disable_power_well) 1960 intel_display_power_put(i915, POWER_DOMAIN_INIT, 1961 fetch_and_zero(&i915->display.power.domains.disable_wakeref)); 1962 1963 intel_display_power_flush_work_sync(i915); 1964 1965 intel_power_domains_verify_state(i915); 1966 1967 /* Keep the power well enabled, but cancel its rpm wakeref. */ 1968 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1969 } 1970 1971 /** 1972 * intel_power_domains_sanitize_state - sanitize power domains state 1973 * @i915: i915 device instance 1974 * 1975 * Sanitize the power domains state during driver loading and system resume. 1976 * The function will disable all display power wells that BIOS has enabled 1977 * without a user for it (any user for a power well has taken a reference 1978 * on it by the time this function is called, after the state of all the 1979 * pipe, encoder, etc. HW resources have been sanitized). 1980 */ 1981 void intel_power_domains_sanitize_state(struct drm_i915_private *i915) 1982 { 1983 struct i915_power_domains *power_domains = &i915->display.power.domains; 1984 struct i915_power_well *power_well; 1985 1986 mutex_lock(&power_domains->lock); 1987 1988 for_each_power_well_reverse(i915, power_well) { 1989 if (power_well->desc->always_on || power_well->count || 1990 !intel_power_well_is_enabled(i915, power_well)) 1991 continue; 1992 1993 drm_dbg_kms(&i915->drm, 1994 "BIOS left unused %s power well enabled, disabling it\n", 1995 intel_power_well_name(power_well)); 1996 intel_power_well_disable(i915, power_well); 1997 } 1998 1999 mutex_unlock(&power_domains->lock); 2000 } 2001 2002 /** 2003 * intel_power_domains_enable - enable toggling of display power wells 2004 * @i915: i915 device instance 2005 * 2006 * Enable the ondemand enabling/disabling of the display power wells. Note that 2007 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled 2008 * only at specific points of the display modeset sequence, thus they are not 2009 * affected by the intel_power_domains_enable()/disable() calls. The purpose 2010 * of these function is to keep the rest of power wells enabled until the end 2011 * of display HW readout (which will acquire the power references reflecting 2012 * the current HW state). 2013 */ 2014 void intel_power_domains_enable(struct drm_i915_private *i915) 2015 { 2016 intel_wakeref_t wakeref __maybe_unused = 2017 fetch_and_zero(&i915->display.power.domains.init_wakeref); 2018 2019 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 2020 intel_power_domains_verify_state(i915); 2021 } 2022 2023 /** 2024 * intel_power_domains_disable - disable toggling of display power wells 2025 * @i915: i915 device instance 2026 * 2027 * Disable the ondemand enabling/disabling of the display power wells. See 2028 * intel_power_domains_enable() for which power wells this call controls. 2029 */ 2030 void intel_power_domains_disable(struct drm_i915_private *i915) 2031 { 2032 struct i915_power_domains *power_domains = &i915->display.power.domains; 2033 2034 drm_WARN_ON(&i915->drm, power_domains->init_wakeref); 2035 power_domains->init_wakeref = 2036 intel_display_power_get(i915, POWER_DOMAIN_INIT); 2037 2038 intel_power_domains_verify_state(i915); 2039 } 2040 2041 /** 2042 * intel_power_domains_suspend - suspend power domain state 2043 * @i915: i915 device instance 2044 * @s2idle: specifies whether we go to idle, or deeper sleep 2045 * 2046 * This function prepares the hardware power domain state before entering 2047 * system suspend. 2048 * 2049 * It must be called with power domains already disabled (after a call to 2050 * intel_power_domains_disable()) and paired with intel_power_domains_resume(). 2051 */ 2052 void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle) 2053 { 2054 struct i915_power_domains *power_domains = &i915->display.power.domains; 2055 intel_wakeref_t wakeref __maybe_unused = 2056 fetch_and_zero(&power_domains->init_wakeref); 2057 2058 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 2059 2060 /* 2061 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9 2062 * support don't manually deinit the power domains. This also means the 2063 * DMC firmware will stay active, it will power down any HW 2064 * resources as required and also enable deeper system power states 2065 * that would be blocked if the firmware was inactive. 2066 */ 2067 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle && 2068 intel_dmc_has_payload(i915)) { 2069 intel_display_power_flush_work(i915); 2070 intel_power_domains_verify_state(i915); 2071 return; 2072 } 2073 2074 /* 2075 * Even if power well support was disabled we still want to disable 2076 * power wells if power domains must be deinitialized for suspend. 2077 */ 2078 if (!i915->params.disable_power_well) 2079 intel_display_power_put(i915, POWER_DOMAIN_INIT, 2080 fetch_and_zero(&i915->display.power.domains.disable_wakeref)); 2081 2082 intel_display_power_flush_work(i915); 2083 intel_power_domains_verify_state(i915); 2084 2085 if (DISPLAY_VER(i915) >= 11) 2086 icl_display_core_uninit(i915); 2087 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 2088 bxt_display_core_uninit(i915); 2089 else if (DISPLAY_VER(i915) == 9) 2090 skl_display_core_uninit(i915); 2091 2092 power_domains->display_core_suspended = true; 2093 } 2094 2095 /** 2096 * intel_power_domains_resume - resume power domain state 2097 * @i915: i915 device instance 2098 * 2099 * This function resume the hardware power domain state during system resume. 2100 * 2101 * It will return with power domain support disabled (to be enabled later by 2102 * intel_power_domains_enable()) and must be paired with 2103 * intel_power_domains_suspend(). 2104 */ 2105 void intel_power_domains_resume(struct drm_i915_private *i915) 2106 { 2107 struct i915_power_domains *power_domains = &i915->display.power.domains; 2108 2109 if (power_domains->display_core_suspended) { 2110 intel_power_domains_init_hw(i915, true); 2111 power_domains->display_core_suspended = false; 2112 } else { 2113 drm_WARN_ON(&i915->drm, power_domains->init_wakeref); 2114 power_domains->init_wakeref = 2115 intel_display_power_get(i915, POWER_DOMAIN_INIT); 2116 } 2117 2118 intel_power_domains_verify_state(i915); 2119 } 2120 2121 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 2122 2123 static void intel_power_domains_dump_info(struct drm_i915_private *i915) 2124 { 2125 struct i915_power_domains *power_domains = &i915->display.power.domains; 2126 struct i915_power_well *power_well; 2127 2128 for_each_power_well(i915, power_well) { 2129 enum intel_display_power_domain domain; 2130 2131 drm_dbg(&i915->drm, "%-25s %d\n", 2132 intel_power_well_name(power_well), intel_power_well_refcount(power_well)); 2133 2134 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2135 drm_dbg(&i915->drm, " %-23s %d\n", 2136 intel_display_power_domain_str(domain), 2137 power_domains->domain_use_count[domain]); 2138 } 2139 } 2140 2141 /** 2142 * intel_power_domains_verify_state - verify the HW/SW state for all power wells 2143 * @i915: i915 device instance 2144 * 2145 * Verify if the reference count of each power well matches its HW enabled 2146 * state and the total refcount of the domains it belongs to. This must be 2147 * called after modeset HW state sanitization, which is responsible for 2148 * acquiring reference counts for any power wells in use and disabling the 2149 * ones left on by BIOS but not required by any active output. 2150 */ 2151 static void intel_power_domains_verify_state(struct drm_i915_private *i915) 2152 { 2153 struct i915_power_domains *power_domains = &i915->display.power.domains; 2154 struct i915_power_well *power_well; 2155 bool dump_domain_info; 2156 2157 mutex_lock(&power_domains->lock); 2158 2159 verify_async_put_domains_state(power_domains); 2160 2161 dump_domain_info = false; 2162 for_each_power_well(i915, power_well) { 2163 enum intel_display_power_domain domain; 2164 int domains_count; 2165 bool enabled; 2166 2167 enabled = intel_power_well_is_enabled(i915, power_well); 2168 if ((intel_power_well_refcount(power_well) || 2169 intel_power_well_is_always_on(power_well)) != 2170 enabled) 2171 drm_err(&i915->drm, 2172 "power well %s state mismatch (refcount %d/enabled %d)", 2173 intel_power_well_name(power_well), 2174 intel_power_well_refcount(power_well), enabled); 2175 2176 domains_count = 0; 2177 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2178 domains_count += power_domains->domain_use_count[domain]; 2179 2180 if (intel_power_well_refcount(power_well) != domains_count) { 2181 drm_err(&i915->drm, 2182 "power well %s refcount/domain refcount mismatch " 2183 "(refcount %d/domains refcount %d)\n", 2184 intel_power_well_name(power_well), 2185 intel_power_well_refcount(power_well), 2186 domains_count); 2187 dump_domain_info = true; 2188 } 2189 } 2190 2191 if (dump_domain_info) { 2192 static bool dumped; 2193 2194 if (!dumped) { 2195 intel_power_domains_dump_info(i915); 2196 dumped = true; 2197 } 2198 } 2199 2200 mutex_unlock(&power_domains->lock); 2201 } 2202 2203 #else 2204 2205 static void intel_power_domains_verify_state(struct drm_i915_private *i915) 2206 { 2207 } 2208 2209 #endif 2210 2211 void intel_display_power_suspend_late(struct drm_i915_private *i915) 2212 { 2213 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || 2214 IS_BROXTON(i915)) { 2215 bxt_enable_dc9(i915); 2216 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2217 hsw_enable_pc8(i915); 2218 } 2219 2220 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2221 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) 2222 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); 2223 } 2224 2225 void intel_display_power_resume_early(struct drm_i915_private *i915) 2226 { 2227 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || 2228 IS_BROXTON(i915)) { 2229 gen9_sanitize_dc_state(i915); 2230 bxt_disable_dc9(i915); 2231 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2232 hsw_disable_pc8(i915); 2233 } 2234 2235 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2236 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) 2237 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); 2238 } 2239 2240 void intel_display_power_suspend(struct drm_i915_private *i915) 2241 { 2242 if (DISPLAY_VER(i915) >= 11) { 2243 icl_display_core_uninit(i915); 2244 bxt_enable_dc9(i915); 2245 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 2246 bxt_display_core_uninit(i915); 2247 bxt_enable_dc9(i915); 2248 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2249 hsw_enable_pc8(i915); 2250 } 2251 } 2252 2253 void intel_display_power_resume(struct drm_i915_private *i915) 2254 { 2255 struct i915_power_domains *power_domains = &i915->display.power.domains; 2256 2257 if (DISPLAY_VER(i915) >= 11) { 2258 bxt_disable_dc9(i915); 2259 icl_display_core_init(i915, true); 2260 if (intel_dmc_has_payload(i915)) { 2261 if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 2262 skl_enable_dc6(i915); 2263 else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 2264 gen9_enable_dc5(i915); 2265 } 2266 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 2267 bxt_disable_dc9(i915); 2268 bxt_display_core_init(i915, true); 2269 if (intel_dmc_has_payload(i915) && 2270 (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) 2271 gen9_enable_dc5(i915); 2272 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2273 hsw_disable_pc8(i915); 2274 } 2275 } 2276 2277 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m) 2278 { 2279 struct i915_power_domains *power_domains = &i915->display.power.domains; 2280 int i; 2281 2282 mutex_lock(&power_domains->lock); 2283 2284 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); 2285 for (i = 0; i < power_domains->power_well_count; i++) { 2286 struct i915_power_well *power_well; 2287 enum intel_display_power_domain power_domain; 2288 2289 power_well = &power_domains->power_wells[i]; 2290 seq_printf(m, "%-25s %d\n", intel_power_well_name(power_well), 2291 intel_power_well_refcount(power_well)); 2292 2293 for_each_power_domain(power_domain, intel_power_well_domains(power_well)) 2294 seq_printf(m, " %-23s %d\n", 2295 intel_display_power_domain_str(power_domain), 2296 power_domains->domain_use_count[power_domain]); 2297 } 2298 2299 mutex_unlock(&power_domains->lock); 2300 } 2301 2302 struct intel_ddi_port_domains { 2303 enum port port_start; 2304 enum port port_end; 2305 enum aux_ch aux_ch_start; 2306 enum aux_ch aux_ch_end; 2307 2308 enum intel_display_power_domain ddi_lanes; 2309 enum intel_display_power_domain ddi_io; 2310 enum intel_display_power_domain aux_io; 2311 enum intel_display_power_domain aux_legacy_usbc; 2312 enum intel_display_power_domain aux_tbt; 2313 }; 2314 2315 static const struct intel_ddi_port_domains 2316 i9xx_port_domains[] = { 2317 { 2318 .port_start = PORT_A, 2319 .port_end = PORT_F, 2320 .aux_ch_start = AUX_CH_A, 2321 .aux_ch_end = AUX_CH_F, 2322 2323 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2324 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2325 .aux_io = POWER_DOMAIN_AUX_IO_A, 2326 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2327 .aux_tbt = POWER_DOMAIN_INVALID, 2328 }, 2329 }; 2330 2331 static const struct intel_ddi_port_domains 2332 d11_port_domains[] = { 2333 { 2334 .port_start = PORT_A, 2335 .port_end = PORT_B, 2336 .aux_ch_start = AUX_CH_A, 2337 .aux_ch_end = AUX_CH_B, 2338 2339 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2340 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2341 .aux_io = POWER_DOMAIN_AUX_IO_A, 2342 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2343 .aux_tbt = POWER_DOMAIN_INVALID, 2344 }, { 2345 .port_start = PORT_C, 2346 .port_end = PORT_F, 2347 .aux_ch_start = AUX_CH_C, 2348 .aux_ch_end = AUX_CH_F, 2349 2350 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C, 2351 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_C, 2352 .aux_io = POWER_DOMAIN_AUX_IO_C, 2353 .aux_legacy_usbc = POWER_DOMAIN_AUX_C, 2354 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2355 }, 2356 }; 2357 2358 static const struct intel_ddi_port_domains 2359 d12_port_domains[] = { 2360 { 2361 .port_start = PORT_A, 2362 .port_end = PORT_C, 2363 .aux_ch_start = AUX_CH_A, 2364 .aux_ch_end = AUX_CH_C, 2365 2366 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2367 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2368 .aux_io = POWER_DOMAIN_AUX_IO_A, 2369 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2370 .aux_tbt = POWER_DOMAIN_INVALID, 2371 }, { 2372 .port_start = PORT_TC1, 2373 .port_end = PORT_TC6, 2374 .aux_ch_start = AUX_CH_USBC1, 2375 .aux_ch_end = AUX_CH_USBC6, 2376 2377 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1, 2378 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1, 2379 .aux_io = POWER_DOMAIN_INVALID, 2380 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1, 2381 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2382 }, 2383 }; 2384 2385 static const struct intel_ddi_port_domains 2386 d13_port_domains[] = { 2387 { 2388 .port_start = PORT_A, 2389 .port_end = PORT_C, 2390 .aux_ch_start = AUX_CH_A, 2391 .aux_ch_end = AUX_CH_C, 2392 2393 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2394 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2395 .aux_io = POWER_DOMAIN_AUX_IO_A, 2396 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2397 .aux_tbt = POWER_DOMAIN_INVALID, 2398 }, { 2399 .port_start = PORT_TC1, 2400 .port_end = PORT_TC4, 2401 .aux_ch_start = AUX_CH_USBC1, 2402 .aux_ch_end = AUX_CH_USBC4, 2403 2404 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1, 2405 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1, 2406 .aux_io = POWER_DOMAIN_INVALID, 2407 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1, 2408 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2409 }, { 2410 .port_start = PORT_D_XELPD, 2411 .port_end = PORT_E_XELPD, 2412 .aux_ch_start = AUX_CH_D_XELPD, 2413 .aux_ch_end = AUX_CH_E_XELPD, 2414 2415 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D, 2416 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D, 2417 .aux_io = POWER_DOMAIN_AUX_IO_D, 2418 .aux_legacy_usbc = POWER_DOMAIN_AUX_D, 2419 .aux_tbt = POWER_DOMAIN_INVALID, 2420 }, 2421 }; 2422 2423 static void 2424 intel_port_domains_for_platform(struct drm_i915_private *i915, 2425 const struct intel_ddi_port_domains **domains, 2426 int *domains_size) 2427 { 2428 if (DISPLAY_VER(i915) >= 13) { 2429 *domains = d13_port_domains; 2430 *domains_size = ARRAY_SIZE(d13_port_domains); 2431 } else if (DISPLAY_VER(i915) >= 12) { 2432 *domains = d12_port_domains; 2433 *domains_size = ARRAY_SIZE(d12_port_domains); 2434 } else if (DISPLAY_VER(i915) >= 11) { 2435 *domains = d11_port_domains; 2436 *domains_size = ARRAY_SIZE(d11_port_domains); 2437 } else { 2438 *domains = i9xx_port_domains; 2439 *domains_size = ARRAY_SIZE(i9xx_port_domains); 2440 } 2441 } 2442 2443 static const struct intel_ddi_port_domains * 2444 intel_port_domains_for_port(struct drm_i915_private *i915, enum port port) 2445 { 2446 const struct intel_ddi_port_domains *domains; 2447 int domains_size; 2448 int i; 2449 2450 intel_port_domains_for_platform(i915, &domains, &domains_size); 2451 for (i = 0; i < domains_size; i++) 2452 if (port >= domains[i].port_start && port <= domains[i].port_end) 2453 return &domains[i]; 2454 2455 return NULL; 2456 } 2457 2458 enum intel_display_power_domain 2459 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port) 2460 { 2461 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port); 2462 2463 if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID)) 2464 return POWER_DOMAIN_PORT_DDI_IO_A; 2465 2466 return domains->ddi_io + (int)(port - domains->port_start); 2467 } 2468 2469 enum intel_display_power_domain 2470 intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port) 2471 { 2472 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port); 2473 2474 if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)) 2475 return POWER_DOMAIN_PORT_DDI_LANES_A; 2476 2477 return domains->ddi_lanes + (int)(port - domains->port_start); 2478 } 2479 2480 static const struct intel_ddi_port_domains * 2481 intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch) 2482 { 2483 const struct intel_ddi_port_domains *domains; 2484 int domains_size; 2485 int i; 2486 2487 intel_port_domains_for_platform(i915, &domains, &domains_size); 2488 for (i = 0; i < domains_size; i++) 2489 if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end) 2490 return &domains[i]; 2491 2492 return NULL; 2493 } 2494 2495 enum intel_display_power_domain 2496 intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2497 { 2498 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch); 2499 2500 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID)) 2501 return POWER_DOMAIN_AUX_IO_A; 2502 2503 return domains->aux_io + (int)(aux_ch - domains->aux_ch_start); 2504 } 2505 2506 enum intel_display_power_domain 2507 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2508 { 2509 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch); 2510 2511 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)) 2512 return POWER_DOMAIN_AUX_A; 2513 2514 return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start); 2515 } 2516 2517 enum intel_display_power_domain 2518 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2519 { 2520 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch); 2521 2522 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID)) 2523 return POWER_DOMAIN_AUX_TBT1; 2524 2525 return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start); 2526 } 2527