1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include "i915_drv.h" 9 #include "i915_irq.h" 10 #include "intel_backlight_regs.h" 11 #include "intel_cdclk.h" 12 #include "intel_combo_phy.h" 13 #include "intel_de.h" 14 #include "intel_display_power.h" 15 #include "intel_display_power_map.h" 16 #include "intel_display_power_well.h" 17 #include "intel_display_types.h" 18 #include "intel_dmc.h" 19 #include "intel_mchbar_regs.h" 20 #include "intel_pch_refclk.h" 21 #include "intel_pcode.h" 22 #include "intel_pps_regs.h" 23 #include "intel_snps_phy.h" 24 #include "skl_watermark.h" 25 #include "skl_watermark_regs.h" 26 #include "vlv_sideband.h" 27 28 #define for_each_power_domain_well(__dev_priv, __power_well, __domain) \ 29 for_each_power_well(__dev_priv, __power_well) \ 30 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 31 32 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \ 33 for_each_power_well_reverse(__dev_priv, __power_well) \ 34 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 35 36 const char * 37 intel_display_power_domain_str(enum intel_display_power_domain domain) 38 { 39 switch (domain) { 40 case POWER_DOMAIN_DISPLAY_CORE: 41 return "DISPLAY_CORE"; 42 case POWER_DOMAIN_PIPE_A: 43 return "PIPE_A"; 44 case POWER_DOMAIN_PIPE_B: 45 return "PIPE_B"; 46 case POWER_DOMAIN_PIPE_C: 47 return "PIPE_C"; 48 case POWER_DOMAIN_PIPE_D: 49 return "PIPE_D"; 50 case POWER_DOMAIN_PIPE_PANEL_FITTER_A: 51 return "PIPE_PANEL_FITTER_A"; 52 case POWER_DOMAIN_PIPE_PANEL_FITTER_B: 53 return "PIPE_PANEL_FITTER_B"; 54 case POWER_DOMAIN_PIPE_PANEL_FITTER_C: 55 return "PIPE_PANEL_FITTER_C"; 56 case POWER_DOMAIN_PIPE_PANEL_FITTER_D: 57 return "PIPE_PANEL_FITTER_D"; 58 case POWER_DOMAIN_TRANSCODER_A: 59 return "TRANSCODER_A"; 60 case POWER_DOMAIN_TRANSCODER_B: 61 return "TRANSCODER_B"; 62 case POWER_DOMAIN_TRANSCODER_C: 63 return "TRANSCODER_C"; 64 case POWER_DOMAIN_TRANSCODER_D: 65 return "TRANSCODER_D"; 66 case POWER_DOMAIN_TRANSCODER_EDP: 67 return "TRANSCODER_EDP"; 68 case POWER_DOMAIN_TRANSCODER_DSI_A: 69 return "TRANSCODER_DSI_A"; 70 case POWER_DOMAIN_TRANSCODER_DSI_C: 71 return "TRANSCODER_DSI_C"; 72 case POWER_DOMAIN_TRANSCODER_VDSC_PW2: 73 return "TRANSCODER_VDSC_PW2"; 74 case POWER_DOMAIN_PORT_DDI_LANES_A: 75 return "PORT_DDI_LANES_A"; 76 case POWER_DOMAIN_PORT_DDI_LANES_B: 77 return "PORT_DDI_LANES_B"; 78 case POWER_DOMAIN_PORT_DDI_LANES_C: 79 return "PORT_DDI_LANES_C"; 80 case POWER_DOMAIN_PORT_DDI_LANES_D: 81 return "PORT_DDI_LANES_D"; 82 case POWER_DOMAIN_PORT_DDI_LANES_E: 83 return "PORT_DDI_LANES_E"; 84 case POWER_DOMAIN_PORT_DDI_LANES_F: 85 return "PORT_DDI_LANES_F"; 86 case POWER_DOMAIN_PORT_DDI_LANES_TC1: 87 return "PORT_DDI_LANES_TC1"; 88 case POWER_DOMAIN_PORT_DDI_LANES_TC2: 89 return "PORT_DDI_LANES_TC2"; 90 case POWER_DOMAIN_PORT_DDI_LANES_TC3: 91 return "PORT_DDI_LANES_TC3"; 92 case POWER_DOMAIN_PORT_DDI_LANES_TC4: 93 return "PORT_DDI_LANES_TC4"; 94 case POWER_DOMAIN_PORT_DDI_LANES_TC5: 95 return "PORT_DDI_LANES_TC5"; 96 case POWER_DOMAIN_PORT_DDI_LANES_TC6: 97 return "PORT_DDI_LANES_TC6"; 98 case POWER_DOMAIN_PORT_DDI_IO_A: 99 return "PORT_DDI_IO_A"; 100 case POWER_DOMAIN_PORT_DDI_IO_B: 101 return "PORT_DDI_IO_B"; 102 case POWER_DOMAIN_PORT_DDI_IO_C: 103 return "PORT_DDI_IO_C"; 104 case POWER_DOMAIN_PORT_DDI_IO_D: 105 return "PORT_DDI_IO_D"; 106 case POWER_DOMAIN_PORT_DDI_IO_E: 107 return "PORT_DDI_IO_E"; 108 case POWER_DOMAIN_PORT_DDI_IO_F: 109 return "PORT_DDI_IO_F"; 110 case POWER_DOMAIN_PORT_DDI_IO_TC1: 111 return "PORT_DDI_IO_TC1"; 112 case POWER_DOMAIN_PORT_DDI_IO_TC2: 113 return "PORT_DDI_IO_TC2"; 114 case POWER_DOMAIN_PORT_DDI_IO_TC3: 115 return "PORT_DDI_IO_TC3"; 116 case POWER_DOMAIN_PORT_DDI_IO_TC4: 117 return "PORT_DDI_IO_TC4"; 118 case POWER_DOMAIN_PORT_DDI_IO_TC5: 119 return "PORT_DDI_IO_TC5"; 120 case POWER_DOMAIN_PORT_DDI_IO_TC6: 121 return "PORT_DDI_IO_TC6"; 122 case POWER_DOMAIN_PORT_DSI: 123 return "PORT_DSI"; 124 case POWER_DOMAIN_PORT_CRT: 125 return "PORT_CRT"; 126 case POWER_DOMAIN_PORT_OTHER: 127 return "PORT_OTHER"; 128 case POWER_DOMAIN_VGA: 129 return "VGA"; 130 case POWER_DOMAIN_AUDIO_MMIO: 131 return "AUDIO_MMIO"; 132 case POWER_DOMAIN_AUDIO_PLAYBACK: 133 return "AUDIO_PLAYBACK"; 134 case POWER_DOMAIN_AUX_IO_A: 135 return "AUX_IO_A"; 136 case POWER_DOMAIN_AUX_IO_B: 137 return "AUX_IO_B"; 138 case POWER_DOMAIN_AUX_IO_C: 139 return "AUX_IO_C"; 140 case POWER_DOMAIN_AUX_IO_D: 141 return "AUX_IO_D"; 142 case POWER_DOMAIN_AUX_IO_E: 143 return "AUX_IO_E"; 144 case POWER_DOMAIN_AUX_IO_F: 145 return "AUX_IO_F"; 146 case POWER_DOMAIN_AUX_A: 147 return "AUX_A"; 148 case POWER_DOMAIN_AUX_B: 149 return "AUX_B"; 150 case POWER_DOMAIN_AUX_C: 151 return "AUX_C"; 152 case POWER_DOMAIN_AUX_D: 153 return "AUX_D"; 154 case POWER_DOMAIN_AUX_E: 155 return "AUX_E"; 156 case POWER_DOMAIN_AUX_F: 157 return "AUX_F"; 158 case POWER_DOMAIN_AUX_USBC1: 159 return "AUX_USBC1"; 160 case POWER_DOMAIN_AUX_USBC2: 161 return "AUX_USBC2"; 162 case POWER_DOMAIN_AUX_USBC3: 163 return "AUX_USBC3"; 164 case POWER_DOMAIN_AUX_USBC4: 165 return "AUX_USBC4"; 166 case POWER_DOMAIN_AUX_USBC5: 167 return "AUX_USBC5"; 168 case POWER_DOMAIN_AUX_USBC6: 169 return "AUX_USBC6"; 170 case POWER_DOMAIN_AUX_TBT1: 171 return "AUX_TBT1"; 172 case POWER_DOMAIN_AUX_TBT2: 173 return "AUX_TBT2"; 174 case POWER_DOMAIN_AUX_TBT3: 175 return "AUX_TBT3"; 176 case POWER_DOMAIN_AUX_TBT4: 177 return "AUX_TBT4"; 178 case POWER_DOMAIN_AUX_TBT5: 179 return "AUX_TBT5"; 180 case POWER_DOMAIN_AUX_TBT6: 181 return "AUX_TBT6"; 182 case POWER_DOMAIN_GMBUS: 183 return "GMBUS"; 184 case POWER_DOMAIN_INIT: 185 return "INIT"; 186 case POWER_DOMAIN_MODESET: 187 return "MODESET"; 188 case POWER_DOMAIN_GT_IRQ: 189 return "GT_IRQ"; 190 case POWER_DOMAIN_DC_OFF: 191 return "DC_OFF"; 192 case POWER_DOMAIN_TC_COLD_OFF: 193 return "TC_COLD_OFF"; 194 default: 195 MISSING_CASE(domain); 196 return "?"; 197 } 198 } 199 200 /** 201 * __intel_display_power_is_enabled - unlocked check for a power domain 202 * @dev_priv: i915 device instance 203 * @domain: power domain to check 204 * 205 * This is the unlocked version of intel_display_power_is_enabled() and should 206 * only be used from error capture and recovery code where deadlocks are 207 * possible. 208 * 209 * Returns: 210 * True when the power domain is enabled, false otherwise. 211 */ 212 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 213 enum intel_display_power_domain domain) 214 { 215 struct i915_power_well *power_well; 216 bool is_enabled; 217 218 if (dev_priv->runtime_pm.suspended) 219 return false; 220 221 is_enabled = true; 222 223 for_each_power_domain_well_reverse(dev_priv, power_well, domain) { 224 if (intel_power_well_is_always_on(power_well)) 225 continue; 226 227 if (!intel_power_well_is_enabled_cached(power_well)) { 228 is_enabled = false; 229 break; 230 } 231 } 232 233 return is_enabled; 234 } 235 236 /** 237 * intel_display_power_is_enabled - check for a power domain 238 * @dev_priv: i915 device instance 239 * @domain: power domain to check 240 * 241 * This function can be used to check the hw power domain state. It is mostly 242 * used in hardware state readout functions. Everywhere else code should rely 243 * upon explicit power domain reference counting to ensure that the hardware 244 * block is powered up before accessing it. 245 * 246 * Callers must hold the relevant modesetting locks to ensure that concurrent 247 * threads can't disable the power well while the caller tries to read a few 248 * registers. 249 * 250 * Returns: 251 * True when the power domain is enabled, false otherwise. 252 */ 253 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 254 enum intel_display_power_domain domain) 255 { 256 struct i915_power_domains *power_domains; 257 bool ret; 258 259 power_domains = &dev_priv->display.power.domains; 260 261 mutex_lock(&power_domains->lock); 262 ret = __intel_display_power_is_enabled(dev_priv, domain); 263 mutex_unlock(&power_domains->lock); 264 265 return ret; 266 } 267 268 static u32 269 sanitize_target_dc_state(struct drm_i915_private *i915, 270 u32 target_dc_state) 271 { 272 struct i915_power_domains *power_domains = &i915->display.power.domains; 273 static const u32 states[] = { 274 DC_STATE_EN_UPTO_DC6, 275 DC_STATE_EN_UPTO_DC5, 276 DC_STATE_EN_DC3CO, 277 DC_STATE_DISABLE, 278 }; 279 int i; 280 281 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) { 282 if (target_dc_state != states[i]) 283 continue; 284 285 if (power_domains->allowed_dc_mask & target_dc_state) 286 break; 287 288 target_dc_state = states[i + 1]; 289 } 290 291 return target_dc_state; 292 } 293 294 /** 295 * intel_display_power_set_target_dc_state - Set target dc state. 296 * @dev_priv: i915 device 297 * @state: state which needs to be set as target_dc_state. 298 * 299 * This function set the "DC off" power well target_dc_state, 300 * based upon this target_dc_stste, "DC off" power well will 301 * enable desired DC state. 302 */ 303 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 304 u32 state) 305 { 306 struct i915_power_well *power_well; 307 bool dc_off_enabled; 308 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 309 310 mutex_lock(&power_domains->lock); 311 power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF); 312 313 if (drm_WARN_ON(&dev_priv->drm, !power_well)) 314 goto unlock; 315 316 state = sanitize_target_dc_state(dev_priv, state); 317 318 if (state == power_domains->target_dc_state) 319 goto unlock; 320 321 dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well); 322 /* 323 * If DC off power well is disabled, need to enable and disable the 324 * DC off power well to effect target DC state. 325 */ 326 if (!dc_off_enabled) 327 intel_power_well_enable(dev_priv, power_well); 328 329 power_domains->target_dc_state = state; 330 331 if (!dc_off_enabled) 332 intel_power_well_disable(dev_priv, power_well); 333 334 unlock: 335 mutex_unlock(&power_domains->lock); 336 } 337 338 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0)) 339 340 static void __async_put_domains_mask(struct i915_power_domains *power_domains, 341 struct intel_power_domain_mask *mask) 342 { 343 bitmap_or(mask->bits, 344 power_domains->async_put_domains[0].bits, 345 power_domains->async_put_domains[1].bits, 346 POWER_DOMAIN_NUM); 347 } 348 349 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 350 351 static bool 352 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 353 { 354 struct drm_i915_private *i915 = container_of(power_domains, 355 struct drm_i915_private, 356 display.power.domains); 357 358 return !drm_WARN_ON(&i915->drm, 359 bitmap_intersects(power_domains->async_put_domains[0].bits, 360 power_domains->async_put_domains[1].bits, 361 POWER_DOMAIN_NUM)); 362 } 363 364 static bool 365 __async_put_domains_state_ok(struct i915_power_domains *power_domains) 366 { 367 struct drm_i915_private *i915 = container_of(power_domains, 368 struct drm_i915_private, 369 display.power.domains); 370 struct intel_power_domain_mask async_put_mask; 371 enum intel_display_power_domain domain; 372 bool err = false; 373 374 err |= !assert_async_put_domain_masks_disjoint(power_domains); 375 __async_put_domains_mask(power_domains, &async_put_mask); 376 err |= drm_WARN_ON(&i915->drm, 377 !!power_domains->async_put_wakeref != 378 !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)); 379 380 for_each_power_domain(domain, &async_put_mask) 381 err |= drm_WARN_ON(&i915->drm, 382 power_domains->domain_use_count[domain] != 1); 383 384 return !err; 385 } 386 387 static void print_power_domains(struct i915_power_domains *power_domains, 388 const char *prefix, struct intel_power_domain_mask *mask) 389 { 390 struct drm_i915_private *i915 = container_of(power_domains, 391 struct drm_i915_private, 392 display.power.domains); 393 enum intel_display_power_domain domain; 394 395 drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM)); 396 for_each_power_domain(domain, mask) 397 drm_dbg(&i915->drm, "%s use_count %d\n", 398 intel_display_power_domain_str(domain), 399 power_domains->domain_use_count[domain]); 400 } 401 402 static void 403 print_async_put_domains_state(struct i915_power_domains *power_domains) 404 { 405 struct drm_i915_private *i915 = container_of(power_domains, 406 struct drm_i915_private, 407 display.power.domains); 408 409 drm_dbg(&i915->drm, "async_put_wakeref %u\n", 410 power_domains->async_put_wakeref); 411 412 print_power_domains(power_domains, "async_put_domains[0]", 413 &power_domains->async_put_domains[0]); 414 print_power_domains(power_domains, "async_put_domains[1]", 415 &power_domains->async_put_domains[1]); 416 } 417 418 static void 419 verify_async_put_domains_state(struct i915_power_domains *power_domains) 420 { 421 if (!__async_put_domains_state_ok(power_domains)) 422 print_async_put_domains_state(power_domains); 423 } 424 425 #else 426 427 static void 428 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 429 { 430 } 431 432 static void 433 verify_async_put_domains_state(struct i915_power_domains *power_domains) 434 { 435 } 436 437 #endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */ 438 439 static void async_put_domains_mask(struct i915_power_domains *power_domains, 440 struct intel_power_domain_mask *mask) 441 442 { 443 assert_async_put_domain_masks_disjoint(power_domains); 444 445 __async_put_domains_mask(power_domains, mask); 446 } 447 448 static void 449 async_put_domains_clear_domain(struct i915_power_domains *power_domains, 450 enum intel_display_power_domain domain) 451 { 452 assert_async_put_domain_masks_disjoint(power_domains); 453 454 clear_bit(domain, power_domains->async_put_domains[0].bits); 455 clear_bit(domain, power_domains->async_put_domains[1].bits); 456 } 457 458 static bool 459 intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv, 460 enum intel_display_power_domain domain) 461 { 462 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 463 struct intel_power_domain_mask async_put_mask; 464 bool ret = false; 465 466 async_put_domains_mask(power_domains, &async_put_mask); 467 if (!test_bit(domain, async_put_mask.bits)) 468 goto out_verify; 469 470 async_put_domains_clear_domain(power_domains, domain); 471 472 ret = true; 473 474 async_put_domains_mask(power_domains, &async_put_mask); 475 if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)) 476 goto out_verify; 477 478 cancel_delayed_work(&power_domains->async_put_work); 479 intel_runtime_pm_put_raw(&dev_priv->runtime_pm, 480 fetch_and_zero(&power_domains->async_put_wakeref)); 481 out_verify: 482 verify_async_put_domains_state(power_domains); 483 484 return ret; 485 } 486 487 static void 488 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, 489 enum intel_display_power_domain domain) 490 { 491 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 492 struct i915_power_well *power_well; 493 494 if (intel_display_power_grab_async_put_ref(dev_priv, domain)) 495 return; 496 497 for_each_power_domain_well(dev_priv, power_well, domain) 498 intel_power_well_get(dev_priv, power_well); 499 500 power_domains->domain_use_count[domain]++; 501 } 502 503 /** 504 * intel_display_power_get - grab a power domain reference 505 * @dev_priv: i915 device instance 506 * @domain: power domain to reference 507 * 508 * This function grabs a power domain reference for @domain and ensures that the 509 * power domain and all its parents are powered up. Therefore users should only 510 * grab a reference to the innermost power domain they need. 511 * 512 * Any power domain reference obtained by this function must have a symmetric 513 * call to intel_display_power_put() to release the reference again. 514 */ 515 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 516 enum intel_display_power_domain domain) 517 { 518 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 519 intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 520 521 mutex_lock(&power_domains->lock); 522 __intel_display_power_get_domain(dev_priv, domain); 523 mutex_unlock(&power_domains->lock); 524 525 return wakeref; 526 } 527 528 /** 529 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 530 * @dev_priv: i915 device instance 531 * @domain: power domain to reference 532 * 533 * This function grabs a power domain reference for @domain and ensures that the 534 * power domain and all its parents are powered up. Therefore users should only 535 * grab a reference to the innermost power domain they need. 536 * 537 * Any power domain reference obtained by this function must have a symmetric 538 * call to intel_display_power_put() to release the reference again. 539 */ 540 intel_wakeref_t 541 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 542 enum intel_display_power_domain domain) 543 { 544 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 545 intel_wakeref_t wakeref; 546 bool is_enabled; 547 548 wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm); 549 if (!wakeref) 550 return false; 551 552 mutex_lock(&power_domains->lock); 553 554 if (__intel_display_power_is_enabled(dev_priv, domain)) { 555 __intel_display_power_get_domain(dev_priv, domain); 556 is_enabled = true; 557 } else { 558 is_enabled = false; 559 } 560 561 mutex_unlock(&power_domains->lock); 562 563 if (!is_enabled) { 564 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 565 wakeref = 0; 566 } 567 568 return wakeref; 569 } 570 571 static void 572 __intel_display_power_put_domain(struct drm_i915_private *dev_priv, 573 enum intel_display_power_domain domain) 574 { 575 struct i915_power_domains *power_domains; 576 struct i915_power_well *power_well; 577 const char *name = intel_display_power_domain_str(domain); 578 struct intel_power_domain_mask async_put_mask; 579 580 power_domains = &dev_priv->display.power.domains; 581 582 drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain], 583 "Use count on domain %s is already zero\n", 584 name); 585 async_put_domains_mask(power_domains, &async_put_mask); 586 drm_WARN(&dev_priv->drm, 587 test_bit(domain, async_put_mask.bits), 588 "Async disabling of domain %s is pending\n", 589 name); 590 591 power_domains->domain_use_count[domain]--; 592 593 for_each_power_domain_well_reverse(dev_priv, power_well, domain) 594 intel_power_well_put(dev_priv, power_well); 595 } 596 597 static void __intel_display_power_put(struct drm_i915_private *dev_priv, 598 enum intel_display_power_domain domain) 599 { 600 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 601 602 mutex_lock(&power_domains->lock); 603 __intel_display_power_put_domain(dev_priv, domain); 604 mutex_unlock(&power_domains->lock); 605 } 606 607 static void 608 queue_async_put_domains_work(struct i915_power_domains *power_domains, 609 intel_wakeref_t wakeref) 610 { 611 struct drm_i915_private *i915 = container_of(power_domains, 612 struct drm_i915_private, 613 display.power.domains); 614 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref); 615 power_domains->async_put_wakeref = wakeref; 616 drm_WARN_ON(&i915->drm, !queue_delayed_work(system_unbound_wq, 617 &power_domains->async_put_work, 618 msecs_to_jiffies(100))); 619 } 620 621 static void 622 release_async_put_domains(struct i915_power_domains *power_domains, 623 struct intel_power_domain_mask *mask) 624 { 625 struct drm_i915_private *dev_priv = 626 container_of(power_domains, struct drm_i915_private, 627 display.power.domains); 628 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 629 enum intel_display_power_domain domain; 630 intel_wakeref_t wakeref; 631 632 /* 633 * The caller must hold already raw wakeref, upgrade that to a proper 634 * wakeref to make the state checker happy about the HW access during 635 * power well disabling. 636 */ 637 assert_rpm_raw_wakeref_held(rpm); 638 wakeref = intel_runtime_pm_get(rpm); 639 640 for_each_power_domain(domain, mask) { 641 /* Clear before put, so put's sanity check is happy. */ 642 async_put_domains_clear_domain(power_domains, domain); 643 __intel_display_power_put_domain(dev_priv, domain); 644 } 645 646 intel_runtime_pm_put(rpm, wakeref); 647 } 648 649 static void 650 intel_display_power_put_async_work(struct work_struct *work) 651 { 652 struct drm_i915_private *dev_priv = 653 container_of(work, struct drm_i915_private, 654 display.power.domains.async_put_work.work); 655 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 656 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 657 intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(rpm); 658 intel_wakeref_t old_work_wakeref = 0; 659 660 mutex_lock(&power_domains->lock); 661 662 /* 663 * Bail out if all the domain refs pending to be released were grabbed 664 * by subsequent gets or a flush_work. 665 */ 666 old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); 667 if (!old_work_wakeref) 668 goto out_verify; 669 670 release_async_put_domains(power_domains, 671 &power_domains->async_put_domains[0]); 672 673 /* Requeue the work if more domains were async put meanwhile. */ 674 if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) { 675 bitmap_copy(power_domains->async_put_domains[0].bits, 676 power_domains->async_put_domains[1].bits, 677 POWER_DOMAIN_NUM); 678 bitmap_zero(power_domains->async_put_domains[1].bits, 679 POWER_DOMAIN_NUM); 680 queue_async_put_domains_work(power_domains, 681 fetch_and_zero(&new_work_wakeref)); 682 } else { 683 /* 684 * Cancel the work that got queued after this one got dequeued, 685 * since here we released the corresponding async-put reference. 686 */ 687 cancel_delayed_work(&power_domains->async_put_work); 688 } 689 690 out_verify: 691 verify_async_put_domains_state(power_domains); 692 693 mutex_unlock(&power_domains->lock); 694 695 if (old_work_wakeref) 696 intel_runtime_pm_put_raw(rpm, old_work_wakeref); 697 if (new_work_wakeref) 698 intel_runtime_pm_put_raw(rpm, new_work_wakeref); 699 } 700 701 /** 702 * __intel_display_power_put_async - release a power domain reference asynchronously 703 * @i915: i915 device instance 704 * @domain: power domain to reference 705 * @wakeref: wakeref acquired for the reference that is being released 706 * 707 * This function drops the power domain reference obtained by 708 * intel_display_power_get*() and schedules a work to power down the 709 * corresponding hardware block if this is the last reference. 710 */ 711 void __intel_display_power_put_async(struct drm_i915_private *i915, 712 enum intel_display_power_domain domain, 713 intel_wakeref_t wakeref) 714 { 715 struct i915_power_domains *power_domains = &i915->display.power.domains; 716 struct intel_runtime_pm *rpm = &i915->runtime_pm; 717 intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm); 718 719 mutex_lock(&power_domains->lock); 720 721 if (power_domains->domain_use_count[domain] > 1) { 722 __intel_display_power_put_domain(i915, domain); 723 724 goto out_verify; 725 } 726 727 drm_WARN_ON(&i915->drm, power_domains->domain_use_count[domain] != 1); 728 729 /* Let a pending work requeue itself or queue a new one. */ 730 if (power_domains->async_put_wakeref) { 731 set_bit(domain, power_domains->async_put_domains[1].bits); 732 } else { 733 set_bit(domain, power_domains->async_put_domains[0].bits); 734 queue_async_put_domains_work(power_domains, 735 fetch_and_zero(&work_wakeref)); 736 } 737 738 out_verify: 739 verify_async_put_domains_state(power_domains); 740 741 mutex_unlock(&power_domains->lock); 742 743 if (work_wakeref) 744 intel_runtime_pm_put_raw(rpm, work_wakeref); 745 746 intel_runtime_pm_put(rpm, wakeref); 747 } 748 749 /** 750 * intel_display_power_flush_work - flushes the async display power disabling work 751 * @i915: i915 device instance 752 * 753 * Flushes any pending work that was scheduled by a preceding 754 * intel_display_power_put_async() call, completing the disabling of the 755 * corresponding power domains. 756 * 757 * Note that the work handler function may still be running after this 758 * function returns; to ensure that the work handler isn't running use 759 * intel_display_power_flush_work_sync() instead. 760 */ 761 void intel_display_power_flush_work(struct drm_i915_private *i915) 762 { 763 struct i915_power_domains *power_domains = &i915->display.power.domains; 764 struct intel_power_domain_mask async_put_mask; 765 intel_wakeref_t work_wakeref; 766 767 mutex_lock(&power_domains->lock); 768 769 work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); 770 if (!work_wakeref) 771 goto out_verify; 772 773 async_put_domains_mask(power_domains, &async_put_mask); 774 release_async_put_domains(power_domains, &async_put_mask); 775 cancel_delayed_work(&power_domains->async_put_work); 776 777 out_verify: 778 verify_async_put_domains_state(power_domains); 779 780 mutex_unlock(&power_domains->lock); 781 782 if (work_wakeref) 783 intel_runtime_pm_put_raw(&i915->runtime_pm, work_wakeref); 784 } 785 786 /** 787 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work 788 * @i915: i915 device instance 789 * 790 * Like intel_display_power_flush_work(), but also ensure that the work 791 * handler function is not running any more when this function returns. 792 */ 793 static void 794 intel_display_power_flush_work_sync(struct drm_i915_private *i915) 795 { 796 struct i915_power_domains *power_domains = &i915->display.power.domains; 797 798 intel_display_power_flush_work(i915); 799 cancel_delayed_work_sync(&power_domains->async_put_work); 800 801 verify_async_put_domains_state(power_domains); 802 803 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref); 804 } 805 806 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 807 /** 808 * intel_display_power_put - release a power domain reference 809 * @dev_priv: i915 device instance 810 * @domain: power domain to reference 811 * @wakeref: wakeref acquired for the reference that is being released 812 * 813 * This function drops the power domain reference obtained by 814 * intel_display_power_get() and might power down the corresponding hardware 815 * block right away if this is the last reference. 816 */ 817 void intel_display_power_put(struct drm_i915_private *dev_priv, 818 enum intel_display_power_domain domain, 819 intel_wakeref_t wakeref) 820 { 821 __intel_display_power_put(dev_priv, domain); 822 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 823 } 824 #else 825 /** 826 * intel_display_power_put_unchecked - release an unchecked power domain reference 827 * @dev_priv: i915 device instance 828 * @domain: power domain to reference 829 * 830 * This function drops the power domain reference obtained by 831 * intel_display_power_get() and might power down the corresponding hardware 832 * block right away if this is the last reference. 833 * 834 * This function is only for the power domain code's internal use to suppress wakeref 835 * tracking when the correspondig debug kconfig option is disabled, should not 836 * be used otherwise. 837 */ 838 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 839 enum intel_display_power_domain domain) 840 { 841 __intel_display_power_put(dev_priv, domain); 842 intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); 843 } 844 #endif 845 846 void 847 intel_display_power_get_in_set(struct drm_i915_private *i915, 848 struct intel_display_power_domain_set *power_domain_set, 849 enum intel_display_power_domain domain) 850 { 851 intel_wakeref_t __maybe_unused wf; 852 853 drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits)); 854 855 wf = intel_display_power_get(i915, domain); 856 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 857 power_domain_set->wakerefs[domain] = wf; 858 #endif 859 set_bit(domain, power_domain_set->mask.bits); 860 } 861 862 bool 863 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, 864 struct intel_display_power_domain_set *power_domain_set, 865 enum intel_display_power_domain domain) 866 { 867 intel_wakeref_t wf; 868 869 drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits)); 870 871 wf = intel_display_power_get_if_enabled(i915, domain); 872 if (!wf) 873 return false; 874 875 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 876 power_domain_set->wakerefs[domain] = wf; 877 #endif 878 set_bit(domain, power_domain_set->mask.bits); 879 880 return true; 881 } 882 883 void 884 intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 885 struct intel_display_power_domain_set *power_domain_set, 886 struct intel_power_domain_mask *mask) 887 { 888 enum intel_display_power_domain domain; 889 890 drm_WARN_ON(&i915->drm, 891 !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM)); 892 893 for_each_power_domain(domain, mask) { 894 intel_wakeref_t __maybe_unused wf = -1; 895 896 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 897 wf = fetch_and_zero(&power_domain_set->wakerefs[domain]); 898 #endif 899 intel_display_power_put(i915, domain, wf); 900 clear_bit(domain, power_domain_set->mask.bits); 901 } 902 } 903 904 static int 905 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 906 int disable_power_well) 907 { 908 if (disable_power_well >= 0) 909 return !!disable_power_well; 910 911 return 1; 912 } 913 914 static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, 915 int enable_dc) 916 { 917 u32 mask; 918 int requested_dc; 919 int max_dc; 920 921 if (!HAS_DISPLAY(dev_priv)) 922 return 0; 923 924 if (IS_DG2(dev_priv)) 925 max_dc = 1; 926 else if (IS_DG1(dev_priv)) 927 max_dc = 3; 928 else if (DISPLAY_VER(dev_priv) >= 12) 929 max_dc = 4; 930 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 931 max_dc = 1; 932 else if (DISPLAY_VER(dev_priv) >= 9) 933 max_dc = 2; 934 else 935 max_dc = 0; 936 937 /* 938 * DC9 has a separate HW flow from the rest of the DC states, 939 * not depending on the DMC firmware. It's needed by system 940 * suspend/resume, so allow it unconditionally. 941 */ 942 mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || 943 DISPLAY_VER(dev_priv) >= 11 ? 944 DC_STATE_EN_DC9 : 0; 945 946 if (!dev_priv->params.disable_power_well) 947 max_dc = 0; 948 949 if (enable_dc >= 0 && enable_dc <= max_dc) { 950 requested_dc = enable_dc; 951 } else if (enable_dc == -1) { 952 requested_dc = max_dc; 953 } else if (enable_dc > max_dc && enable_dc <= 4) { 954 drm_dbg_kms(&dev_priv->drm, 955 "Adjusting requested max DC state (%d->%d)\n", 956 enable_dc, max_dc); 957 requested_dc = max_dc; 958 } else { 959 drm_err(&dev_priv->drm, 960 "Unexpected value for enable_dc (%d)\n", enable_dc); 961 requested_dc = max_dc; 962 } 963 964 switch (requested_dc) { 965 case 4: 966 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6; 967 break; 968 case 3: 969 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5; 970 break; 971 case 2: 972 mask |= DC_STATE_EN_UPTO_DC6; 973 break; 974 case 1: 975 mask |= DC_STATE_EN_UPTO_DC5; 976 break; 977 } 978 979 drm_dbg_kms(&dev_priv->drm, "Allowed DC state mask %02x\n", mask); 980 981 return mask; 982 } 983 984 /** 985 * intel_power_domains_init - initializes the power domain structures 986 * @dev_priv: i915 device instance 987 * 988 * Initializes the power domain structures for @dev_priv depending upon the 989 * supported platform. 990 */ 991 int intel_power_domains_init(struct drm_i915_private *dev_priv) 992 { 993 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 994 995 dev_priv->params.disable_power_well = 996 sanitize_disable_power_well_option(dev_priv, 997 dev_priv->params.disable_power_well); 998 power_domains->allowed_dc_mask = 999 get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc); 1000 1001 power_domains->target_dc_state = 1002 sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 1003 1004 mutex_init(&power_domains->lock); 1005 1006 INIT_DELAYED_WORK(&power_domains->async_put_work, 1007 intel_display_power_put_async_work); 1008 1009 return intel_display_power_map_init(power_domains); 1010 } 1011 1012 /** 1013 * intel_power_domains_cleanup - clean up power domains resources 1014 * @dev_priv: i915 device instance 1015 * 1016 * Release any resources acquired by intel_power_domains_init() 1017 */ 1018 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv) 1019 { 1020 intel_display_power_map_cleanup(&dev_priv->display.power.domains); 1021 } 1022 1023 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 1024 { 1025 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1026 struct i915_power_well *power_well; 1027 1028 mutex_lock(&power_domains->lock); 1029 for_each_power_well(dev_priv, power_well) 1030 intel_power_well_sync_hw(dev_priv, power_well); 1031 mutex_unlock(&power_domains->lock); 1032 } 1033 1034 static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv, 1035 enum dbuf_slice slice, bool enable) 1036 { 1037 i915_reg_t reg = DBUF_CTL_S(slice); 1038 bool state; 1039 1040 intel_de_rmw(dev_priv, reg, DBUF_POWER_REQUEST, 1041 enable ? DBUF_POWER_REQUEST : 0); 1042 intel_de_posting_read(dev_priv, reg); 1043 udelay(10); 1044 1045 state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE; 1046 drm_WARN(&dev_priv->drm, enable != state, 1047 "DBuf slice %d power %s timeout!\n", 1048 slice, str_enable_disable(enable)); 1049 } 1050 1051 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 1052 u8 req_slices) 1053 { 1054 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1055 u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask; 1056 enum dbuf_slice slice; 1057 1058 drm_WARN(&dev_priv->drm, req_slices & ~slice_mask, 1059 "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n", 1060 req_slices, slice_mask); 1061 1062 drm_dbg_kms(&dev_priv->drm, "Updating dbuf slices to 0x%x\n", 1063 req_slices); 1064 1065 /* 1066 * Might be running this in parallel to gen9_dc_off_power_well_enable 1067 * being called from intel_dp_detect for instance, 1068 * which causes assertion triggered by race condition, 1069 * as gen9_assert_dbuf_enabled might preempt this when registers 1070 * were already updated, while dev_priv was not. 1071 */ 1072 mutex_lock(&power_domains->lock); 1073 1074 for_each_dbuf_slice(dev_priv, slice) 1075 gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice)); 1076 1077 dev_priv->display.dbuf.enabled_slices = req_slices; 1078 1079 mutex_unlock(&power_domains->lock); 1080 } 1081 1082 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) 1083 { 1084 dev_priv->display.dbuf.enabled_slices = 1085 intel_enabled_dbuf_slices_mask(dev_priv); 1086 1087 /* 1088 * Just power up at least 1 slice, we will 1089 * figure out later which slices we have and what we need. 1090 */ 1091 gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) | 1092 dev_priv->display.dbuf.enabled_slices); 1093 } 1094 1095 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) 1096 { 1097 gen9_dbuf_slices_update(dev_priv, 0); 1098 } 1099 1100 static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv) 1101 { 1102 enum dbuf_slice slice; 1103 1104 if (IS_ALDERLAKE_P(dev_priv)) 1105 return; 1106 1107 for_each_dbuf_slice(dev_priv, slice) 1108 intel_de_rmw(dev_priv, DBUF_CTL_S(slice), 1109 DBUF_TRACKER_STATE_SERVICE_MASK, 1110 DBUF_TRACKER_STATE_SERVICE(8)); 1111 } 1112 1113 static void icl_mbus_init(struct drm_i915_private *dev_priv) 1114 { 1115 unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask; 1116 u32 mask, val, i; 1117 1118 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 1119 return; 1120 1121 mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | 1122 MBUS_ABOX_BT_CREDIT_POOL2_MASK | 1123 MBUS_ABOX_B_CREDIT_MASK | 1124 MBUS_ABOX_BW_CREDIT_MASK; 1125 val = MBUS_ABOX_BT_CREDIT_POOL1(16) | 1126 MBUS_ABOX_BT_CREDIT_POOL2(16) | 1127 MBUS_ABOX_B_CREDIT(1) | 1128 MBUS_ABOX_BW_CREDIT(1); 1129 1130 /* 1131 * gen12 platforms that use abox1 and abox2 for pixel data reads still 1132 * expect us to program the abox_ctl0 register as well, even though 1133 * we don't have to program other instance-0 registers like BW_BUDDY. 1134 */ 1135 if (DISPLAY_VER(dev_priv) == 12) 1136 abox_regs |= BIT(0); 1137 1138 for_each_set_bit(i, &abox_regs, sizeof(abox_regs)) 1139 intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val); 1140 } 1141 1142 static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) 1143 { 1144 u32 val = intel_de_read(dev_priv, LCPLL_CTL); 1145 1146 /* 1147 * The LCPLL register should be turned on by the BIOS. For now 1148 * let's just check its state and print errors in case 1149 * something is wrong. Don't even try to turn it on. 1150 */ 1151 1152 if (val & LCPLL_CD_SOURCE_FCLK) 1153 drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n"); 1154 1155 if (val & LCPLL_PLL_DISABLE) 1156 drm_err(&dev_priv->drm, "LCPLL is disabled\n"); 1157 1158 if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC) 1159 drm_err(&dev_priv->drm, "LCPLL not using non-SSC reference\n"); 1160 } 1161 1162 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) 1163 { 1164 struct intel_crtc *crtc; 1165 1166 for_each_intel_crtc(&dev_priv->drm, crtc) 1167 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", 1168 pipe_name(crtc->pipe)); 1169 1170 I915_STATE_WARN(intel_de_read(dev_priv, HSW_PWR_WELL_CTL2), 1171 "Display power well on\n"); 1172 I915_STATE_WARN(intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE, 1173 "SPLL enabled\n"); 1174 I915_STATE_WARN(intel_de_read(dev_priv, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, 1175 "WRPLL1 enabled\n"); 1176 I915_STATE_WARN(intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, 1177 "WRPLL2 enabled\n"); 1178 I915_STATE_WARN(intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON, 1179 "Panel power on\n"); 1180 I915_STATE_WARN(intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, 1181 "CPU PWM1 enabled\n"); 1182 if (IS_HASWELL(dev_priv)) 1183 I915_STATE_WARN(intel_de_read(dev_priv, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, 1184 "CPU PWM2 enabled\n"); 1185 I915_STATE_WARN(intel_de_read(dev_priv, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, 1186 "PCH PWM1 enabled\n"); 1187 I915_STATE_WARN((intel_de_read(dev_priv, UTIL_PIN_CTL) & 1188 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == 1189 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 1190 "Utility pin enabled in PWM mode\n"); 1191 I915_STATE_WARN(intel_de_read(dev_priv, PCH_GTC_CTL) & PCH_GTC_ENABLE, 1192 "PCH GTC enabled\n"); 1193 1194 /* 1195 * In theory we can still leave IRQs enabled, as long as only the HPD 1196 * interrupts remain enabled. We used to check for that, but since it's 1197 * gen-specific and since we only disable LCPLL after we fully disable 1198 * the interrupts, the check below should be enough. 1199 */ 1200 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); 1201 } 1202 1203 static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv) 1204 { 1205 if (IS_HASWELL(dev_priv)) 1206 return intel_de_read(dev_priv, D_COMP_HSW); 1207 else 1208 return intel_de_read(dev_priv, D_COMP_BDW); 1209 } 1210 1211 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val) 1212 { 1213 if (IS_HASWELL(dev_priv)) { 1214 if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val)) 1215 drm_dbg_kms(&dev_priv->drm, 1216 "Failed to write to D_COMP\n"); 1217 } else { 1218 intel_de_write(dev_priv, D_COMP_BDW, val); 1219 intel_de_posting_read(dev_priv, D_COMP_BDW); 1220 } 1221 } 1222 1223 /* 1224 * This function implements pieces of two sequences from BSpec: 1225 * - Sequence for display software to disable LCPLL 1226 * - Sequence for display software to allow package C8+ 1227 * The steps implemented here are just the steps that actually touch the LCPLL 1228 * register. Callers should take care of disabling all the display engine 1229 * functions, doing the mode unset, fixing interrupts, etc. 1230 */ 1231 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, 1232 bool switch_to_fclk, bool allow_power_down) 1233 { 1234 u32 val; 1235 1236 assert_can_disable_lcpll(dev_priv); 1237 1238 val = intel_de_read(dev_priv, LCPLL_CTL); 1239 1240 if (switch_to_fclk) { 1241 val |= LCPLL_CD_SOURCE_FCLK; 1242 intel_de_write(dev_priv, LCPLL_CTL, val); 1243 1244 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & 1245 LCPLL_CD_SOURCE_FCLK_DONE, 1)) 1246 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); 1247 1248 val = intel_de_read(dev_priv, LCPLL_CTL); 1249 } 1250 1251 val |= LCPLL_PLL_DISABLE; 1252 intel_de_write(dev_priv, LCPLL_CTL, val); 1253 intel_de_posting_read(dev_priv, LCPLL_CTL); 1254 1255 if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) 1256 drm_err(&dev_priv->drm, "LCPLL still locked\n"); 1257 1258 val = hsw_read_dcomp(dev_priv); 1259 val |= D_COMP_COMP_DISABLE; 1260 hsw_write_dcomp(dev_priv, val); 1261 ndelay(100); 1262 1263 if (wait_for((hsw_read_dcomp(dev_priv) & 1264 D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) 1265 drm_err(&dev_priv->drm, "D_COMP RCOMP still in progress\n"); 1266 1267 if (allow_power_down) { 1268 intel_de_rmw(dev_priv, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW); 1269 intel_de_posting_read(dev_priv, LCPLL_CTL); 1270 } 1271 } 1272 1273 /* 1274 * Fully restores LCPLL, disallowing power down and switching back to LCPLL 1275 * source. 1276 */ 1277 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) 1278 { 1279 u32 val; 1280 1281 val = intel_de_read(dev_priv, LCPLL_CTL); 1282 1283 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | 1284 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) 1285 return; 1286 1287 /* 1288 * Make sure we're not on PC8 state before disabling PC8, otherwise 1289 * we'll hang the machine. To prevent PC8 state, just enable force_wake. 1290 */ 1291 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); 1292 1293 if (val & LCPLL_POWER_DOWN_ALLOW) { 1294 val &= ~LCPLL_POWER_DOWN_ALLOW; 1295 intel_de_write(dev_priv, LCPLL_CTL, val); 1296 intel_de_posting_read(dev_priv, LCPLL_CTL); 1297 } 1298 1299 val = hsw_read_dcomp(dev_priv); 1300 val |= D_COMP_COMP_FORCE; 1301 val &= ~D_COMP_COMP_DISABLE; 1302 hsw_write_dcomp(dev_priv, val); 1303 1304 val = intel_de_read(dev_priv, LCPLL_CTL); 1305 val &= ~LCPLL_PLL_DISABLE; 1306 intel_de_write(dev_priv, LCPLL_CTL, val); 1307 1308 if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) 1309 drm_err(&dev_priv->drm, "LCPLL not locked yet\n"); 1310 1311 if (val & LCPLL_CD_SOURCE_FCLK) { 1312 intel_de_rmw(dev_priv, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); 1313 1314 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & 1315 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 1316 drm_err(&dev_priv->drm, 1317 "Switching back to LCPLL failed\n"); 1318 } 1319 1320 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); 1321 1322 intel_update_cdclk(dev_priv); 1323 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 1324 } 1325 1326 /* 1327 * Package states C8 and deeper are really deep PC states that can only be 1328 * reached when all the devices on the system allow it, so even if the graphics 1329 * device allows PC8+, it doesn't mean the system will actually get to these 1330 * states. Our driver only allows PC8+ when going into runtime PM. 1331 * 1332 * The requirements for PC8+ are that all the outputs are disabled, the power 1333 * well is disabled and most interrupts are disabled, and these are also 1334 * requirements for runtime PM. When these conditions are met, we manually do 1335 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk 1336 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard 1337 * hang the machine. 1338 * 1339 * When we really reach PC8 or deeper states (not just when we allow it) we lose 1340 * the state of some registers, so when we come back from PC8+ we need to 1341 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't 1342 * need to take care of the registers kept by RC6. Notice that this happens even 1343 * if we don't put the device in PCI D3 state (which is what currently happens 1344 * because of the runtime PM support). 1345 * 1346 * For more, read "Display Sequences for Package C8" on the hardware 1347 * documentation. 1348 */ 1349 static void hsw_enable_pc8(struct drm_i915_private *dev_priv) 1350 { 1351 drm_dbg_kms(&dev_priv->drm, "Enabling package C8+\n"); 1352 1353 if (HAS_PCH_LPT_LP(dev_priv)) 1354 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 1355 PCH_LP_PARTITION_LEVEL_DISABLE, 0); 1356 1357 lpt_disable_clkout_dp(dev_priv); 1358 hsw_disable_lcpll(dev_priv, true, true); 1359 } 1360 1361 static void hsw_disable_pc8(struct drm_i915_private *dev_priv) 1362 { 1363 drm_dbg_kms(&dev_priv->drm, "Disabling package C8+\n"); 1364 1365 hsw_restore_lcpll(dev_priv); 1366 intel_init_pch_refclk(dev_priv); 1367 1368 if (HAS_PCH_LPT_LP(dev_priv)) 1369 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 1370 0, PCH_LP_PARTITION_LEVEL_DISABLE); 1371 } 1372 1373 static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, 1374 bool enable) 1375 { 1376 i915_reg_t reg; 1377 u32 reset_bits; 1378 1379 if (IS_IVYBRIDGE(dev_priv)) { 1380 reg = GEN7_MSG_CTL; 1381 reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK; 1382 } else { 1383 reg = HSW_NDE_RSTWRN_OPT; 1384 reset_bits = RESET_PCH_HANDSHAKE_ENABLE; 1385 } 1386 1387 if (DISPLAY_VER(dev_priv) >= 14) 1388 reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN; 1389 1390 intel_de_rmw(dev_priv, reg, reset_bits, enable ? reset_bits : 0); 1391 } 1392 1393 static void skl_display_core_init(struct drm_i915_private *dev_priv, 1394 bool resume) 1395 { 1396 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1397 struct i915_power_well *well; 1398 1399 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 1400 1401 /* enable PCH reset handshake */ 1402 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); 1403 1404 if (!HAS_DISPLAY(dev_priv)) 1405 return; 1406 1407 /* enable PG1 and Misc I/O */ 1408 mutex_lock(&power_domains->lock); 1409 1410 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1411 intel_power_well_enable(dev_priv, well); 1412 1413 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 1414 intel_power_well_enable(dev_priv, well); 1415 1416 mutex_unlock(&power_domains->lock); 1417 1418 intel_cdclk_init_hw(dev_priv); 1419 1420 gen9_dbuf_enable(dev_priv); 1421 1422 if (resume) 1423 intel_dmc_load_program(dev_priv); 1424 } 1425 1426 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 1427 { 1428 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1429 struct i915_power_well *well; 1430 1431 if (!HAS_DISPLAY(dev_priv)) 1432 return; 1433 1434 gen9_disable_dc_states(dev_priv); 1435 /* TODO: disable DMC program */ 1436 1437 gen9_dbuf_disable(dev_priv); 1438 1439 intel_cdclk_uninit_hw(dev_priv); 1440 1441 /* The spec doesn't call for removing the reset handshake flag */ 1442 /* disable PG1 and Misc I/O */ 1443 1444 mutex_lock(&power_domains->lock); 1445 1446 /* 1447 * BSpec says to keep the MISC IO power well enabled here, only 1448 * remove our request for power well 1. 1449 * Note that even though the driver's request is removed power well 1 1450 * may stay enabled after this due to DMC's own request on it. 1451 */ 1452 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1453 intel_power_well_disable(dev_priv, well); 1454 1455 mutex_unlock(&power_domains->lock); 1456 1457 usleep_range(10, 30); /* 10 us delay per Bspec */ 1458 } 1459 1460 static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume) 1461 { 1462 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1463 struct i915_power_well *well; 1464 1465 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 1466 1467 /* 1468 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 1469 * or else the reset will hang because there is no PCH to respond. 1470 * Move the handshake programming to initialization sequence. 1471 * Previously was left up to BIOS. 1472 */ 1473 intel_pch_reset_handshake(dev_priv, false); 1474 1475 if (!HAS_DISPLAY(dev_priv)) 1476 return; 1477 1478 /* Enable PG1 */ 1479 mutex_lock(&power_domains->lock); 1480 1481 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1482 intel_power_well_enable(dev_priv, well); 1483 1484 mutex_unlock(&power_domains->lock); 1485 1486 intel_cdclk_init_hw(dev_priv); 1487 1488 gen9_dbuf_enable(dev_priv); 1489 1490 if (resume) 1491 intel_dmc_load_program(dev_priv); 1492 } 1493 1494 static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) 1495 { 1496 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1497 struct i915_power_well *well; 1498 1499 if (!HAS_DISPLAY(dev_priv)) 1500 return; 1501 1502 gen9_disable_dc_states(dev_priv); 1503 /* TODO: disable DMC program */ 1504 1505 gen9_dbuf_disable(dev_priv); 1506 1507 intel_cdclk_uninit_hw(dev_priv); 1508 1509 /* The spec doesn't call for removing the reset handshake flag */ 1510 1511 /* 1512 * Disable PW1 (PG1). 1513 * Note that even though the driver's request is removed power well 1 1514 * may stay enabled after this due to DMC's own request on it. 1515 */ 1516 mutex_lock(&power_domains->lock); 1517 1518 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1519 intel_power_well_disable(dev_priv, well); 1520 1521 mutex_unlock(&power_domains->lock); 1522 1523 usleep_range(10, 30); /* 10 us delay per Bspec */ 1524 } 1525 1526 struct buddy_page_mask { 1527 u32 page_mask; 1528 u8 type; 1529 u8 num_channels; 1530 }; 1531 1532 static const struct buddy_page_mask tgl_buddy_page_masks[] = { 1533 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF }, 1534 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0xF }, 1535 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C }, 1536 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1C }, 1537 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F }, 1538 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x1E }, 1539 { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 }, 1540 { .num_channels = 4, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x38 }, 1541 {} 1542 }; 1543 1544 static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = { 1545 { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 }, 1546 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0x1 }, 1547 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0x1 }, 1548 { .num_channels = 1, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1 }, 1549 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 }, 1550 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x3 }, 1551 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x3 }, 1552 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x3 }, 1553 {} 1554 }; 1555 1556 static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) 1557 { 1558 enum intel_dram_type type = dev_priv->dram_info.type; 1559 u8 num_channels = dev_priv->dram_info.num_channels; 1560 const struct buddy_page_mask *table; 1561 unsigned long abox_mask = INTEL_INFO(dev_priv)->display.abox_mask; 1562 int config, i; 1563 1564 /* BW_BUDDY registers are not used on dgpu's beyond DG1 */ 1565 if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv)) 1566 return; 1567 1568 if (IS_ALDERLAKE_S(dev_priv) || 1569 IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1570 /* Wa_1409767108 */ 1571 table = wa_1409767108_buddy_page_masks; 1572 else 1573 table = tgl_buddy_page_masks; 1574 1575 for (config = 0; table[config].page_mask != 0; config++) 1576 if (table[config].num_channels == num_channels && 1577 table[config].type == type) 1578 break; 1579 1580 if (table[config].page_mask == 0) { 1581 drm_dbg(&dev_priv->drm, 1582 "Unknown memory configuration; disabling address buddy logic.\n"); 1583 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) 1584 intel_de_write(dev_priv, BW_BUDDY_CTL(i), 1585 BW_BUDDY_DISABLE); 1586 } else { 1587 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) { 1588 intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), 1589 table[config].page_mask); 1590 1591 /* Wa_22010178259:tgl,dg1,rkl,adl-s */ 1592 if (DISPLAY_VER(dev_priv) == 12) 1593 intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), 1594 BW_BUDDY_TLB_REQ_TIMER_MASK, 1595 BW_BUDDY_TLB_REQ_TIMER(0x8)); 1596 } 1597 } 1598 } 1599 1600 static void icl_display_core_init(struct drm_i915_private *dev_priv, 1601 bool resume) 1602 { 1603 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1604 struct i915_power_well *well; 1605 1606 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 1607 1608 /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */ 1609 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && 1610 INTEL_PCH_TYPE(dev_priv) < PCH_DG1) 1611 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, 1612 PCH_DPMGUNIT_CLOCK_GATE_DISABLE); 1613 1614 /* 1. Enable PCH reset handshake. */ 1615 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); 1616 1617 if (!HAS_DISPLAY(dev_priv)) 1618 return; 1619 1620 /* 2. Initialize all combo phys */ 1621 intel_combo_phy_init(dev_priv); 1622 1623 /* 1624 * 3. Enable Power Well 1 (PG1). 1625 * The AUX IO power wells will be enabled on demand. 1626 */ 1627 mutex_lock(&power_domains->lock); 1628 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1629 intel_power_well_enable(dev_priv, well); 1630 mutex_unlock(&power_domains->lock); 1631 1632 if (DISPLAY_VER(dev_priv) == 14) 1633 intel_de_rmw(dev_priv, DC_STATE_EN, 1634 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0); 1635 1636 /* 4. Enable CDCLK. */ 1637 intel_cdclk_init_hw(dev_priv); 1638 1639 if (DISPLAY_VER(dev_priv) >= 12) 1640 gen12_dbuf_slices_config(dev_priv); 1641 1642 /* 5. Enable DBUF. */ 1643 gen9_dbuf_enable(dev_priv); 1644 1645 /* 6. Setup MBUS. */ 1646 icl_mbus_init(dev_priv); 1647 1648 /* 7. Program arbiter BW_BUDDY registers */ 1649 if (DISPLAY_VER(dev_priv) >= 12) 1650 tgl_bw_buddy_init(dev_priv); 1651 1652 /* 8. Ensure PHYs have completed calibration and adaptation */ 1653 if (IS_DG2(dev_priv)) 1654 intel_snps_phy_wait_for_calibration(dev_priv); 1655 1656 if (resume) 1657 intel_dmc_load_program(dev_priv); 1658 1659 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p */ 1660 if (DISPLAY_VER(dev_priv) >= 12) 1661 intel_de_rmw(dev_priv, GEN11_CHICKEN_DCPR_2, 0, 1662 DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | 1663 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR); 1664 1665 /* Wa_14011503030:xelpd */ 1666 if (DISPLAY_VER(dev_priv) >= 13) 1667 intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0); 1668 } 1669 1670 static void icl_display_core_uninit(struct drm_i915_private *dev_priv) 1671 { 1672 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1673 struct i915_power_well *well; 1674 1675 if (!HAS_DISPLAY(dev_priv)) 1676 return; 1677 1678 gen9_disable_dc_states(dev_priv); 1679 intel_dmc_disable_program(dev_priv); 1680 1681 /* 1. Disable all display engine functions -> aready done */ 1682 1683 /* 2. Disable DBUF */ 1684 gen9_dbuf_disable(dev_priv); 1685 1686 /* 3. Disable CD clock */ 1687 intel_cdclk_uninit_hw(dev_priv); 1688 1689 if (DISPLAY_VER(dev_priv) == 14) 1690 intel_de_rmw(dev_priv, DC_STATE_EN, 0, 1691 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH); 1692 1693 /* 1694 * 4. Disable Power Well 1 (PG1). 1695 * The AUX IO power wells are toggled on demand, so they are already 1696 * disabled at this point. 1697 */ 1698 mutex_lock(&power_domains->lock); 1699 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1700 intel_power_well_disable(dev_priv, well); 1701 mutex_unlock(&power_domains->lock); 1702 1703 /* 5. */ 1704 intel_combo_phy_uninit(dev_priv); 1705 } 1706 1707 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 1708 { 1709 struct i915_power_well *cmn_bc = 1710 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 1711 struct i915_power_well *cmn_d = 1712 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D); 1713 1714 /* 1715 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 1716 * workaround never ever read DISPLAY_PHY_CONTROL, and 1717 * instead maintain a shadow copy ourselves. Use the actual 1718 * power well state and lane status to reconstruct the 1719 * expected initial value. 1720 */ 1721 dev_priv->display.power.chv_phy_control = 1722 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 1723 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 1724 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 1725 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 1726 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 1727 1728 /* 1729 * If all lanes are disabled we leave the override disabled 1730 * with all power down bits cleared to match the state we 1731 * would use after disabling the port. Otherwise enable the 1732 * override and set the lane powerdown bits accding to the 1733 * current lane status. 1734 */ 1735 if (intel_power_well_is_enabled(dev_priv, cmn_bc)) { 1736 u32 status = intel_de_read(dev_priv, DPLL(PIPE_A)); 1737 unsigned int mask; 1738 1739 mask = status & DPLL_PORTB_READY_MASK; 1740 if (mask == 0xf) 1741 mask = 0x0; 1742 else 1743 dev_priv->display.power.chv_phy_control |= 1744 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 1745 1746 dev_priv->display.power.chv_phy_control |= 1747 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 1748 1749 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 1750 if (mask == 0xf) 1751 mask = 0x0; 1752 else 1753 dev_priv->display.power.chv_phy_control |= 1754 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 1755 1756 dev_priv->display.power.chv_phy_control |= 1757 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 1758 1759 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 1760 1761 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = false; 1762 } else { 1763 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true; 1764 } 1765 1766 if (intel_power_well_is_enabled(dev_priv, cmn_d)) { 1767 u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS); 1768 unsigned int mask; 1769 1770 mask = status & DPLL_PORTD_READY_MASK; 1771 1772 if (mask == 0xf) 1773 mask = 0x0; 1774 else 1775 dev_priv->display.power.chv_phy_control |= 1776 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 1777 1778 dev_priv->display.power.chv_phy_control |= 1779 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 1780 1781 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 1782 1783 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = false; 1784 } else { 1785 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = true; 1786 } 1787 1788 drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n", 1789 dev_priv->display.power.chv_phy_control); 1790 1791 /* Defer application of initial phy_control to enabling the powerwell */ 1792 } 1793 1794 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 1795 { 1796 struct i915_power_well *cmn = 1797 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 1798 struct i915_power_well *disp2d = 1799 lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D); 1800 1801 /* If the display might be already active skip this */ 1802 if (intel_power_well_is_enabled(dev_priv, cmn) && 1803 intel_power_well_is_enabled(dev_priv, disp2d) && 1804 intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST) 1805 return; 1806 1807 drm_dbg_kms(&dev_priv->drm, "toggling display PHY side reset\n"); 1808 1809 /* cmnlane needs DPLL registers */ 1810 intel_power_well_enable(dev_priv, disp2d); 1811 1812 /* 1813 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 1814 * Need to assert and de-assert PHY SB reset by gating the 1815 * common lane power, then un-gating it. 1816 * Simply ungating isn't enough to reset the PHY enough to get 1817 * ports and lanes running. 1818 */ 1819 intel_power_well_disable(dev_priv, cmn); 1820 } 1821 1822 static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0) 1823 { 1824 bool ret; 1825 1826 vlv_punit_get(dev_priv); 1827 ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; 1828 vlv_punit_put(dev_priv); 1829 1830 return ret; 1831 } 1832 1833 static void assert_ved_power_gated(struct drm_i915_private *dev_priv) 1834 { 1835 drm_WARN(&dev_priv->drm, 1836 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0), 1837 "VED not power gated\n"); 1838 } 1839 1840 static void assert_isp_power_gated(struct drm_i915_private *dev_priv) 1841 { 1842 static const struct pci_device_id isp_ids[] = { 1843 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)}, 1844 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)}, 1845 {} 1846 }; 1847 1848 drm_WARN(&dev_priv->drm, !pci_dev_present(isp_ids) && 1849 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0), 1850 "ISP not power gated\n"); 1851 } 1852 1853 static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv); 1854 1855 /** 1856 * intel_power_domains_init_hw - initialize hardware power domain state 1857 * @i915: i915 device instance 1858 * @resume: Called from resume code paths or not 1859 * 1860 * This function initializes the hardware power domain state and enables all 1861 * power wells belonging to the INIT power domain. Power wells in other 1862 * domains (and not in the INIT domain) are referenced or disabled by 1863 * intel_modeset_readout_hw_state(). After that the reference count of each 1864 * power well must match its HW enabled state, see 1865 * intel_power_domains_verify_state(). 1866 * 1867 * It will return with power domains disabled (to be enabled later by 1868 * intel_power_domains_enable()) and must be paired with 1869 * intel_power_domains_driver_remove(). 1870 */ 1871 void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) 1872 { 1873 struct i915_power_domains *power_domains = &i915->display.power.domains; 1874 1875 power_domains->initializing = true; 1876 1877 if (DISPLAY_VER(i915) >= 11) { 1878 icl_display_core_init(i915, resume); 1879 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 1880 bxt_display_core_init(i915, resume); 1881 } else if (DISPLAY_VER(i915) == 9) { 1882 skl_display_core_init(i915, resume); 1883 } else if (IS_CHERRYVIEW(i915)) { 1884 mutex_lock(&power_domains->lock); 1885 chv_phy_control_init(i915); 1886 mutex_unlock(&power_domains->lock); 1887 assert_isp_power_gated(i915); 1888 } else if (IS_VALLEYVIEW(i915)) { 1889 mutex_lock(&power_domains->lock); 1890 vlv_cmnlane_wa(i915); 1891 mutex_unlock(&power_domains->lock); 1892 assert_ved_power_gated(i915); 1893 assert_isp_power_gated(i915); 1894 } else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) { 1895 hsw_assert_cdclk(i915); 1896 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915)); 1897 } else if (IS_IVYBRIDGE(i915)) { 1898 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915)); 1899 } 1900 1901 /* 1902 * Keep all power wells enabled for any dependent HW access during 1903 * initialization and to make sure we keep BIOS enabled display HW 1904 * resources powered until display HW readout is complete. We drop 1905 * this reference in intel_power_domains_enable(). 1906 */ 1907 drm_WARN_ON(&i915->drm, power_domains->init_wakeref); 1908 power_domains->init_wakeref = 1909 intel_display_power_get(i915, POWER_DOMAIN_INIT); 1910 1911 /* Disable power support if the user asked so. */ 1912 if (!i915->params.disable_power_well) { 1913 drm_WARN_ON(&i915->drm, power_domains->disable_wakeref); 1914 i915->display.power.domains.disable_wakeref = intel_display_power_get(i915, 1915 POWER_DOMAIN_INIT); 1916 } 1917 intel_power_domains_sync_hw(i915); 1918 1919 power_domains->initializing = false; 1920 } 1921 1922 /** 1923 * intel_power_domains_driver_remove - deinitialize hw power domain state 1924 * @i915: i915 device instance 1925 * 1926 * De-initializes the display power domain HW state. It also ensures that the 1927 * device stays powered up so that the driver can be reloaded. 1928 * 1929 * It must be called with power domains already disabled (after a call to 1930 * intel_power_domains_disable()) and must be paired with 1931 * intel_power_domains_init_hw(). 1932 */ 1933 void intel_power_domains_driver_remove(struct drm_i915_private *i915) 1934 { 1935 intel_wakeref_t wakeref __maybe_unused = 1936 fetch_and_zero(&i915->display.power.domains.init_wakeref); 1937 1938 /* Remove the refcount we took to keep power well support disabled. */ 1939 if (!i915->params.disable_power_well) 1940 intel_display_power_put(i915, POWER_DOMAIN_INIT, 1941 fetch_and_zero(&i915->display.power.domains.disable_wakeref)); 1942 1943 intel_display_power_flush_work_sync(i915); 1944 1945 intel_power_domains_verify_state(i915); 1946 1947 /* Keep the power well enabled, but cancel its rpm wakeref. */ 1948 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1949 } 1950 1951 /** 1952 * intel_power_domains_sanitize_state - sanitize power domains state 1953 * @i915: i915 device instance 1954 * 1955 * Sanitize the power domains state during driver loading and system resume. 1956 * The function will disable all display power wells that BIOS has enabled 1957 * without a user for it (any user for a power well has taken a reference 1958 * on it by the time this function is called, after the state of all the 1959 * pipe, encoder, etc. HW resources have been sanitized). 1960 */ 1961 void intel_power_domains_sanitize_state(struct drm_i915_private *i915) 1962 { 1963 struct i915_power_domains *power_domains = &i915->display.power.domains; 1964 struct i915_power_well *power_well; 1965 1966 mutex_lock(&power_domains->lock); 1967 1968 for_each_power_well_reverse(i915, power_well) { 1969 if (power_well->desc->always_on || power_well->count || 1970 !intel_power_well_is_enabled(i915, power_well)) 1971 continue; 1972 1973 drm_dbg_kms(&i915->drm, 1974 "BIOS left unused %s power well enabled, disabling it\n", 1975 intel_power_well_name(power_well)); 1976 intel_power_well_disable(i915, power_well); 1977 } 1978 1979 mutex_unlock(&power_domains->lock); 1980 } 1981 1982 /** 1983 * intel_power_domains_enable - enable toggling of display power wells 1984 * @i915: i915 device instance 1985 * 1986 * Enable the ondemand enabling/disabling of the display power wells. Note that 1987 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled 1988 * only at specific points of the display modeset sequence, thus they are not 1989 * affected by the intel_power_domains_enable()/disable() calls. The purpose 1990 * of these function is to keep the rest of power wells enabled until the end 1991 * of display HW readout (which will acquire the power references reflecting 1992 * the current HW state). 1993 */ 1994 void intel_power_domains_enable(struct drm_i915_private *i915) 1995 { 1996 intel_wakeref_t wakeref __maybe_unused = 1997 fetch_and_zero(&i915->display.power.domains.init_wakeref); 1998 1999 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 2000 intel_power_domains_verify_state(i915); 2001 } 2002 2003 /** 2004 * intel_power_domains_disable - disable toggling of display power wells 2005 * @i915: i915 device instance 2006 * 2007 * Disable the ondemand enabling/disabling of the display power wells. See 2008 * intel_power_domains_enable() for which power wells this call controls. 2009 */ 2010 void intel_power_domains_disable(struct drm_i915_private *i915) 2011 { 2012 struct i915_power_domains *power_domains = &i915->display.power.domains; 2013 2014 drm_WARN_ON(&i915->drm, power_domains->init_wakeref); 2015 power_domains->init_wakeref = 2016 intel_display_power_get(i915, POWER_DOMAIN_INIT); 2017 2018 intel_power_domains_verify_state(i915); 2019 } 2020 2021 /** 2022 * intel_power_domains_suspend - suspend power domain state 2023 * @i915: i915 device instance 2024 * @suspend_mode: specifies the target suspend state (idle, mem, hibernation) 2025 * 2026 * This function prepares the hardware power domain state before entering 2027 * system suspend. 2028 * 2029 * It must be called with power domains already disabled (after a call to 2030 * intel_power_domains_disable()) and paired with intel_power_domains_resume(). 2031 */ 2032 void intel_power_domains_suspend(struct drm_i915_private *i915, 2033 enum i915_drm_suspend_mode suspend_mode) 2034 { 2035 struct i915_power_domains *power_domains = &i915->display.power.domains; 2036 intel_wakeref_t wakeref __maybe_unused = 2037 fetch_and_zero(&power_domains->init_wakeref); 2038 2039 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 2040 2041 /* 2042 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9 2043 * support don't manually deinit the power domains. This also means the 2044 * DMC firmware will stay active, it will power down any HW 2045 * resources as required and also enable deeper system power states 2046 * that would be blocked if the firmware was inactive. 2047 */ 2048 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && 2049 suspend_mode == I915_DRM_SUSPEND_IDLE && 2050 intel_dmc_has_payload(i915)) { 2051 intel_display_power_flush_work(i915); 2052 intel_power_domains_verify_state(i915); 2053 return; 2054 } 2055 2056 /* 2057 * Even if power well support was disabled we still want to disable 2058 * power wells if power domains must be deinitialized for suspend. 2059 */ 2060 if (!i915->params.disable_power_well) 2061 intel_display_power_put(i915, POWER_DOMAIN_INIT, 2062 fetch_and_zero(&i915->display.power.domains.disable_wakeref)); 2063 2064 intel_display_power_flush_work(i915); 2065 intel_power_domains_verify_state(i915); 2066 2067 if (DISPLAY_VER(i915) >= 11) 2068 icl_display_core_uninit(i915); 2069 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 2070 bxt_display_core_uninit(i915); 2071 else if (DISPLAY_VER(i915) == 9) 2072 skl_display_core_uninit(i915); 2073 2074 power_domains->display_core_suspended = true; 2075 } 2076 2077 /** 2078 * intel_power_domains_resume - resume power domain state 2079 * @i915: i915 device instance 2080 * 2081 * This function resume the hardware power domain state during system resume. 2082 * 2083 * It will return with power domain support disabled (to be enabled later by 2084 * intel_power_domains_enable()) and must be paired with 2085 * intel_power_domains_suspend(). 2086 */ 2087 void intel_power_domains_resume(struct drm_i915_private *i915) 2088 { 2089 struct i915_power_domains *power_domains = &i915->display.power.domains; 2090 2091 if (power_domains->display_core_suspended) { 2092 intel_power_domains_init_hw(i915, true); 2093 power_domains->display_core_suspended = false; 2094 } else { 2095 drm_WARN_ON(&i915->drm, power_domains->init_wakeref); 2096 power_domains->init_wakeref = 2097 intel_display_power_get(i915, POWER_DOMAIN_INIT); 2098 } 2099 2100 intel_power_domains_verify_state(i915); 2101 } 2102 2103 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 2104 2105 static void intel_power_domains_dump_info(struct drm_i915_private *i915) 2106 { 2107 struct i915_power_domains *power_domains = &i915->display.power.domains; 2108 struct i915_power_well *power_well; 2109 2110 for_each_power_well(i915, power_well) { 2111 enum intel_display_power_domain domain; 2112 2113 drm_dbg(&i915->drm, "%-25s %d\n", 2114 intel_power_well_name(power_well), intel_power_well_refcount(power_well)); 2115 2116 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2117 drm_dbg(&i915->drm, " %-23s %d\n", 2118 intel_display_power_domain_str(domain), 2119 power_domains->domain_use_count[domain]); 2120 } 2121 } 2122 2123 /** 2124 * intel_power_domains_verify_state - verify the HW/SW state for all power wells 2125 * @i915: i915 device instance 2126 * 2127 * Verify if the reference count of each power well matches its HW enabled 2128 * state and the total refcount of the domains it belongs to. This must be 2129 * called after modeset HW state sanitization, which is responsible for 2130 * acquiring reference counts for any power wells in use and disabling the 2131 * ones left on by BIOS but not required by any active output. 2132 */ 2133 static void intel_power_domains_verify_state(struct drm_i915_private *i915) 2134 { 2135 struct i915_power_domains *power_domains = &i915->display.power.domains; 2136 struct i915_power_well *power_well; 2137 bool dump_domain_info; 2138 2139 mutex_lock(&power_domains->lock); 2140 2141 verify_async_put_domains_state(power_domains); 2142 2143 dump_domain_info = false; 2144 for_each_power_well(i915, power_well) { 2145 enum intel_display_power_domain domain; 2146 int domains_count; 2147 bool enabled; 2148 2149 enabled = intel_power_well_is_enabled(i915, power_well); 2150 if ((intel_power_well_refcount(power_well) || 2151 intel_power_well_is_always_on(power_well)) != 2152 enabled) 2153 drm_err(&i915->drm, 2154 "power well %s state mismatch (refcount %d/enabled %d)", 2155 intel_power_well_name(power_well), 2156 intel_power_well_refcount(power_well), enabled); 2157 2158 domains_count = 0; 2159 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2160 domains_count += power_domains->domain_use_count[domain]; 2161 2162 if (intel_power_well_refcount(power_well) != domains_count) { 2163 drm_err(&i915->drm, 2164 "power well %s refcount/domain refcount mismatch " 2165 "(refcount %d/domains refcount %d)\n", 2166 intel_power_well_name(power_well), 2167 intel_power_well_refcount(power_well), 2168 domains_count); 2169 dump_domain_info = true; 2170 } 2171 } 2172 2173 if (dump_domain_info) { 2174 static bool dumped; 2175 2176 if (!dumped) { 2177 intel_power_domains_dump_info(i915); 2178 dumped = true; 2179 } 2180 } 2181 2182 mutex_unlock(&power_domains->lock); 2183 } 2184 2185 #else 2186 2187 static void intel_power_domains_verify_state(struct drm_i915_private *i915) 2188 { 2189 } 2190 2191 #endif 2192 2193 void intel_display_power_suspend_late(struct drm_i915_private *i915) 2194 { 2195 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || 2196 IS_BROXTON(i915)) { 2197 bxt_enable_dc9(i915); 2198 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2199 hsw_enable_pc8(i915); 2200 } 2201 2202 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2203 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) 2204 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); 2205 } 2206 2207 void intel_display_power_resume_early(struct drm_i915_private *i915) 2208 { 2209 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || 2210 IS_BROXTON(i915)) { 2211 gen9_sanitize_dc_state(i915); 2212 bxt_disable_dc9(i915); 2213 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2214 hsw_disable_pc8(i915); 2215 } 2216 2217 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2218 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) 2219 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); 2220 } 2221 2222 void intel_display_power_suspend(struct drm_i915_private *i915) 2223 { 2224 if (DISPLAY_VER(i915) >= 11) { 2225 icl_display_core_uninit(i915); 2226 bxt_enable_dc9(i915); 2227 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 2228 bxt_display_core_uninit(i915); 2229 bxt_enable_dc9(i915); 2230 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2231 hsw_enable_pc8(i915); 2232 } 2233 } 2234 2235 void intel_display_power_resume(struct drm_i915_private *i915) 2236 { 2237 struct i915_power_domains *power_domains = &i915->display.power.domains; 2238 2239 if (DISPLAY_VER(i915) >= 11) { 2240 bxt_disable_dc9(i915); 2241 icl_display_core_init(i915, true); 2242 if (intel_dmc_has_payload(i915)) { 2243 if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 2244 skl_enable_dc6(i915); 2245 else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 2246 gen9_enable_dc5(i915); 2247 } 2248 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 2249 bxt_disable_dc9(i915); 2250 bxt_display_core_init(i915, true); 2251 if (intel_dmc_has_payload(i915) && 2252 (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) 2253 gen9_enable_dc5(i915); 2254 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2255 hsw_disable_pc8(i915); 2256 } 2257 } 2258 2259 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m) 2260 { 2261 struct i915_power_domains *power_domains = &i915->display.power.domains; 2262 int i; 2263 2264 mutex_lock(&power_domains->lock); 2265 2266 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); 2267 for (i = 0; i < power_domains->power_well_count; i++) { 2268 struct i915_power_well *power_well; 2269 enum intel_display_power_domain power_domain; 2270 2271 power_well = &power_domains->power_wells[i]; 2272 seq_printf(m, "%-25s %d\n", intel_power_well_name(power_well), 2273 intel_power_well_refcount(power_well)); 2274 2275 for_each_power_domain(power_domain, intel_power_well_domains(power_well)) 2276 seq_printf(m, " %-23s %d\n", 2277 intel_display_power_domain_str(power_domain), 2278 power_domains->domain_use_count[power_domain]); 2279 } 2280 2281 mutex_unlock(&power_domains->lock); 2282 } 2283 2284 struct intel_ddi_port_domains { 2285 enum port port_start; 2286 enum port port_end; 2287 enum aux_ch aux_ch_start; 2288 enum aux_ch aux_ch_end; 2289 2290 enum intel_display_power_domain ddi_lanes; 2291 enum intel_display_power_domain ddi_io; 2292 enum intel_display_power_domain aux_io; 2293 enum intel_display_power_domain aux_legacy_usbc; 2294 enum intel_display_power_domain aux_tbt; 2295 }; 2296 2297 static const struct intel_ddi_port_domains 2298 i9xx_port_domains[] = { 2299 { 2300 .port_start = PORT_A, 2301 .port_end = PORT_F, 2302 .aux_ch_start = AUX_CH_A, 2303 .aux_ch_end = AUX_CH_F, 2304 2305 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2306 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2307 .aux_io = POWER_DOMAIN_AUX_IO_A, 2308 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2309 .aux_tbt = POWER_DOMAIN_INVALID, 2310 }, 2311 }; 2312 2313 static const struct intel_ddi_port_domains 2314 d11_port_domains[] = { 2315 { 2316 .port_start = PORT_A, 2317 .port_end = PORT_B, 2318 .aux_ch_start = AUX_CH_A, 2319 .aux_ch_end = AUX_CH_B, 2320 2321 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2322 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2323 .aux_io = POWER_DOMAIN_AUX_IO_A, 2324 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2325 .aux_tbt = POWER_DOMAIN_INVALID, 2326 }, { 2327 .port_start = PORT_C, 2328 .port_end = PORT_F, 2329 .aux_ch_start = AUX_CH_C, 2330 .aux_ch_end = AUX_CH_F, 2331 2332 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C, 2333 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_C, 2334 .aux_io = POWER_DOMAIN_AUX_IO_C, 2335 .aux_legacy_usbc = POWER_DOMAIN_AUX_C, 2336 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2337 }, 2338 }; 2339 2340 static const struct intel_ddi_port_domains 2341 d12_port_domains[] = { 2342 { 2343 .port_start = PORT_A, 2344 .port_end = PORT_C, 2345 .aux_ch_start = AUX_CH_A, 2346 .aux_ch_end = AUX_CH_C, 2347 2348 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2349 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2350 .aux_io = POWER_DOMAIN_AUX_IO_A, 2351 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2352 .aux_tbt = POWER_DOMAIN_INVALID, 2353 }, { 2354 .port_start = PORT_TC1, 2355 .port_end = PORT_TC6, 2356 .aux_ch_start = AUX_CH_USBC1, 2357 .aux_ch_end = AUX_CH_USBC6, 2358 2359 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1, 2360 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1, 2361 .aux_io = POWER_DOMAIN_INVALID, 2362 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1, 2363 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2364 }, 2365 }; 2366 2367 static const struct intel_ddi_port_domains 2368 d13_port_domains[] = { 2369 { 2370 .port_start = PORT_A, 2371 .port_end = PORT_C, 2372 .aux_ch_start = AUX_CH_A, 2373 .aux_ch_end = AUX_CH_C, 2374 2375 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2376 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2377 .aux_io = POWER_DOMAIN_AUX_IO_A, 2378 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2379 .aux_tbt = POWER_DOMAIN_INVALID, 2380 }, { 2381 .port_start = PORT_TC1, 2382 .port_end = PORT_TC4, 2383 .aux_ch_start = AUX_CH_USBC1, 2384 .aux_ch_end = AUX_CH_USBC4, 2385 2386 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1, 2387 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1, 2388 .aux_io = POWER_DOMAIN_INVALID, 2389 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1, 2390 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2391 }, { 2392 .port_start = PORT_D_XELPD, 2393 .port_end = PORT_E_XELPD, 2394 .aux_ch_start = AUX_CH_D_XELPD, 2395 .aux_ch_end = AUX_CH_E_XELPD, 2396 2397 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D, 2398 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D, 2399 .aux_io = POWER_DOMAIN_AUX_IO_D, 2400 .aux_legacy_usbc = POWER_DOMAIN_AUX_D, 2401 .aux_tbt = POWER_DOMAIN_INVALID, 2402 }, 2403 }; 2404 2405 static void 2406 intel_port_domains_for_platform(struct drm_i915_private *i915, 2407 const struct intel_ddi_port_domains **domains, 2408 int *domains_size) 2409 { 2410 if (DISPLAY_VER(i915) >= 13) { 2411 *domains = d13_port_domains; 2412 *domains_size = ARRAY_SIZE(d13_port_domains); 2413 } else if (DISPLAY_VER(i915) >= 12) { 2414 *domains = d12_port_domains; 2415 *domains_size = ARRAY_SIZE(d12_port_domains); 2416 } else if (DISPLAY_VER(i915) >= 11) { 2417 *domains = d11_port_domains; 2418 *domains_size = ARRAY_SIZE(d11_port_domains); 2419 } else { 2420 *domains = i9xx_port_domains; 2421 *domains_size = ARRAY_SIZE(i9xx_port_domains); 2422 } 2423 } 2424 2425 static const struct intel_ddi_port_domains * 2426 intel_port_domains_for_port(struct drm_i915_private *i915, enum port port) 2427 { 2428 const struct intel_ddi_port_domains *domains; 2429 int domains_size; 2430 int i; 2431 2432 intel_port_domains_for_platform(i915, &domains, &domains_size); 2433 for (i = 0; i < domains_size; i++) 2434 if (port >= domains[i].port_start && port <= domains[i].port_end) 2435 return &domains[i]; 2436 2437 return NULL; 2438 } 2439 2440 enum intel_display_power_domain 2441 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port) 2442 { 2443 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port); 2444 2445 if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID)) 2446 return POWER_DOMAIN_PORT_DDI_IO_A; 2447 2448 return domains->ddi_io + (int)(port - domains->port_start); 2449 } 2450 2451 enum intel_display_power_domain 2452 intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port) 2453 { 2454 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port); 2455 2456 if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)) 2457 return POWER_DOMAIN_PORT_DDI_LANES_A; 2458 2459 return domains->ddi_lanes + (int)(port - domains->port_start); 2460 } 2461 2462 static const struct intel_ddi_port_domains * 2463 intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch) 2464 { 2465 const struct intel_ddi_port_domains *domains; 2466 int domains_size; 2467 int i; 2468 2469 intel_port_domains_for_platform(i915, &domains, &domains_size); 2470 for (i = 0; i < domains_size; i++) 2471 if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end) 2472 return &domains[i]; 2473 2474 return NULL; 2475 } 2476 2477 enum intel_display_power_domain 2478 intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2479 { 2480 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch); 2481 2482 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID)) 2483 return POWER_DOMAIN_AUX_IO_A; 2484 2485 return domains->aux_io + (int)(aux_ch - domains->aux_ch_start); 2486 } 2487 2488 enum intel_display_power_domain 2489 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2490 { 2491 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch); 2492 2493 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)) 2494 return POWER_DOMAIN_AUX_A; 2495 2496 return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start); 2497 } 2498 2499 enum intel_display_power_domain 2500 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2501 { 2502 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch); 2503 2504 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID)) 2505 return POWER_DOMAIN_AUX_TBT1; 2506 2507 return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start); 2508 } 2509