1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include "gt/intel_rps.h" 7 #include "i915_drv.h" 8 #include "i915_irq.h" 9 #include "i915_reg.h" 10 #include "icl_dsi_regs.h" 11 #include "intel_crtc.h" 12 #include "intel_de.h" 13 #include "intel_display_irq.h" 14 #include "intel_display_trace.h" 15 #include "intel_display_types.h" 16 #include "intel_dp_aux.h" 17 #include "intel_fdi_regs.h" 18 #include "intel_fifo_underrun.h" 19 #include "intel_gmbus.h" 20 #include "intel_hotplug_irq.h" 21 #include "intel_pmdemand.h" 22 #include "intel_psr.h" 23 #include "intel_psr_regs.h" 24 25 static void 26 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) 27 { 28 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 29 30 drm_crtc_handle_vblank(&crtc->base); 31 } 32 33 /** 34 * ilk_update_display_irq - update DEIMR 35 * @dev_priv: driver private 36 * @interrupt_mask: mask of interrupt bits to update 37 * @enabled_irq_mask: mask of interrupt bits to enable 38 */ 39 void ilk_update_display_irq(struct drm_i915_private *dev_priv, 40 u32 interrupt_mask, u32 enabled_irq_mask) 41 { 42 u32 new_val; 43 44 lockdep_assert_held(&dev_priv->irq_lock); 45 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 46 47 new_val = dev_priv->irq_mask; 48 new_val &= ~interrupt_mask; 49 new_val |= (~enabled_irq_mask & interrupt_mask); 50 51 if (new_val != dev_priv->irq_mask && 52 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) { 53 dev_priv->irq_mask = new_val; 54 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask); 55 intel_uncore_posting_read(&dev_priv->uncore, DEIMR); 56 } 57 } 58 59 void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits) 60 { 61 ilk_update_display_irq(i915, bits, bits); 62 } 63 64 void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits) 65 { 66 ilk_update_display_irq(i915, bits, 0); 67 } 68 69 /** 70 * bdw_update_port_irq - update DE port interrupt 71 * @dev_priv: driver private 72 * @interrupt_mask: mask of interrupt bits to update 73 * @enabled_irq_mask: mask of interrupt bits to enable 74 */ 75 void bdw_update_port_irq(struct drm_i915_private *dev_priv, 76 u32 interrupt_mask, u32 enabled_irq_mask) 77 { 78 u32 new_val; 79 u32 old_val; 80 81 lockdep_assert_held(&dev_priv->irq_lock); 82 83 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 84 85 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 86 return; 87 88 old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); 89 90 new_val = old_val; 91 new_val &= ~interrupt_mask; 92 new_val |= (~enabled_irq_mask & interrupt_mask); 93 94 if (new_val != old_val) { 95 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val); 96 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); 97 } 98 } 99 100 /** 101 * bdw_update_pipe_irq - update DE pipe interrupt 102 * @dev_priv: driver private 103 * @pipe: pipe whose interrupt to update 104 * @interrupt_mask: mask of interrupt bits to update 105 * @enabled_irq_mask: mask of interrupt bits to enable 106 */ 107 static void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, 108 enum pipe pipe, u32 interrupt_mask, 109 u32 enabled_irq_mask) 110 { 111 u32 new_val; 112 113 lockdep_assert_held(&dev_priv->irq_lock); 114 115 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 116 117 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 118 return; 119 120 new_val = dev_priv->de_irq_mask[pipe]; 121 new_val &= ~interrupt_mask; 122 new_val |= (~enabled_irq_mask & interrupt_mask); 123 124 if (new_val != dev_priv->de_irq_mask[pipe]) { 125 dev_priv->de_irq_mask[pipe] = new_val; 126 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 127 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); 128 } 129 } 130 131 void bdw_enable_pipe_irq(struct drm_i915_private *i915, 132 enum pipe pipe, u32 bits) 133 { 134 bdw_update_pipe_irq(i915, pipe, bits, bits); 135 } 136 137 void bdw_disable_pipe_irq(struct drm_i915_private *i915, 138 enum pipe pipe, u32 bits) 139 { 140 bdw_update_pipe_irq(i915, pipe, bits, 0); 141 } 142 143 /** 144 * ibx_display_interrupt_update - update SDEIMR 145 * @dev_priv: driver private 146 * @interrupt_mask: mask of interrupt bits to update 147 * @enabled_irq_mask: mask of interrupt bits to enable 148 */ 149 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 150 u32 interrupt_mask, 151 u32 enabled_irq_mask) 152 { 153 u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR); 154 155 sdeimr &= ~interrupt_mask; 156 sdeimr |= (~enabled_irq_mask & interrupt_mask); 157 158 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 159 160 lockdep_assert_held(&dev_priv->irq_lock); 161 162 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 163 return; 164 165 intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr); 166 intel_uncore_posting_read(&dev_priv->uncore, SDEIMR); 167 } 168 169 void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits) 170 { 171 ibx_display_interrupt_update(i915, bits, bits); 172 } 173 174 void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits) 175 { 176 ibx_display_interrupt_update(i915, bits, 0); 177 } 178 179 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, 180 enum pipe pipe) 181 { 182 u32 status_mask = dev_priv->pipestat_irq_mask[pipe]; 183 u32 enable_mask = status_mask << 16; 184 185 lockdep_assert_held(&dev_priv->irq_lock); 186 187 if (DISPLAY_VER(dev_priv) < 5) 188 goto out; 189 190 /* 191 * On pipe A we don't support the PSR interrupt yet, 192 * on pipe B and C the same bit MBZ. 193 */ 194 if (drm_WARN_ON_ONCE(&dev_priv->drm, 195 status_mask & PIPE_A_PSR_STATUS_VLV)) 196 return 0; 197 /* 198 * On pipe B and C we don't support the PSR interrupt yet, on pipe 199 * A the same bit is for perf counters which we don't use either. 200 */ 201 if (drm_WARN_ON_ONCE(&dev_priv->drm, 202 status_mask & PIPE_B_PSR_STATUS_VLV)) 203 return 0; 204 205 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | 206 SPRITE0_FLIP_DONE_INT_EN_VLV | 207 SPRITE1_FLIP_DONE_INT_EN_VLV); 208 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) 209 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; 210 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) 211 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; 212 213 out: 214 drm_WARN_ONCE(&dev_priv->drm, 215 enable_mask & ~PIPESTAT_INT_ENABLE_MASK || 216 status_mask & ~PIPESTAT_INT_STATUS_MASK, 217 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", 218 pipe_name(pipe), enable_mask, status_mask); 219 220 return enable_mask; 221 } 222 223 void i915_enable_pipestat(struct drm_i915_private *dev_priv, 224 enum pipe pipe, u32 status_mask) 225 { 226 i915_reg_t reg = PIPESTAT(pipe); 227 u32 enable_mask; 228 229 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, 230 "pipe %c: status_mask=0x%x\n", 231 pipe_name(pipe), status_mask); 232 233 lockdep_assert_held(&dev_priv->irq_lock); 234 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); 235 236 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask) 237 return; 238 239 dev_priv->pipestat_irq_mask[pipe] |= status_mask; 240 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 241 242 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); 243 intel_uncore_posting_read(&dev_priv->uncore, reg); 244 } 245 246 void i915_disable_pipestat(struct drm_i915_private *dev_priv, 247 enum pipe pipe, u32 status_mask) 248 { 249 i915_reg_t reg = PIPESTAT(pipe); 250 u32 enable_mask; 251 252 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, 253 "pipe %c: status_mask=0x%x\n", 254 pipe_name(pipe), status_mask); 255 256 lockdep_assert_held(&dev_priv->irq_lock); 257 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); 258 259 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0) 260 return; 261 262 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; 263 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 264 265 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); 266 intel_uncore_posting_read(&dev_priv->uncore, reg); 267 } 268 269 static bool i915_has_asle(struct drm_i915_private *dev_priv) 270 { 271 if (!dev_priv->display.opregion.asle) 272 return false; 273 274 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 275 } 276 277 /** 278 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion 279 * @dev_priv: i915 device private 280 */ 281 void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) 282 { 283 if (!i915_has_asle(dev_priv)) 284 return; 285 286 spin_lock_irq(&dev_priv->irq_lock); 287 288 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); 289 if (DISPLAY_VER(dev_priv) >= 4) 290 i915_enable_pipestat(dev_priv, PIPE_A, 291 PIPE_LEGACY_BLC_EVENT_STATUS); 292 293 spin_unlock_irq(&dev_priv->irq_lock); 294 } 295 296 #if defined(CONFIG_DEBUG_FS) 297 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 298 enum pipe pipe, 299 u32 crc0, u32 crc1, 300 u32 crc2, u32 crc3, 301 u32 crc4) 302 { 303 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 304 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 305 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 }; 306 307 trace_intel_pipe_crc(crtc, crcs); 308 309 spin_lock(&pipe_crc->lock); 310 /* 311 * For some not yet identified reason, the first CRC is 312 * bonkers. So let's just wait for the next vblank and read 313 * out the buggy result. 314 * 315 * On GEN8+ sometimes the second CRC is bonkers as well, so 316 * don't trust that one either. 317 */ 318 if (pipe_crc->skipped <= 0 || 319 (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) { 320 pipe_crc->skipped++; 321 spin_unlock(&pipe_crc->lock); 322 return; 323 } 324 spin_unlock(&pipe_crc->lock); 325 326 drm_crtc_add_crc_entry(&crtc->base, true, 327 drm_crtc_accurate_vblank_count(&crtc->base), 328 crcs); 329 } 330 #else 331 static inline void 332 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 333 enum pipe pipe, 334 u32 crc0, u32 crc1, 335 u32 crc2, u32 crc3, 336 u32 crc4) {} 337 #endif 338 339 static void flip_done_handler(struct drm_i915_private *i915, 340 enum pipe pipe) 341 { 342 struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe); 343 struct drm_crtc_state *crtc_state = crtc->base.state; 344 struct drm_pending_vblank_event *e = crtc_state->event; 345 struct drm_device *dev = &i915->drm; 346 unsigned long irqflags; 347 348 spin_lock_irqsave(&dev->event_lock, irqflags); 349 350 crtc_state->event = NULL; 351 352 drm_crtc_send_vblank_event(&crtc->base, e); 353 354 spin_unlock_irqrestore(&dev->event_lock, irqflags); 355 } 356 357 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 358 enum pipe pipe) 359 { 360 display_pipe_crc_irq_handler(dev_priv, pipe, 361 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), 362 0, 0, 0, 0); 363 } 364 365 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 366 enum pipe pipe) 367 { 368 display_pipe_crc_irq_handler(dev_priv, pipe, 369 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), 370 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), 371 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), 372 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), 373 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); 374 } 375 376 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 377 enum pipe pipe) 378 { 379 u32 res1, res2; 380 381 if (DISPLAY_VER(dev_priv) >= 3) 382 res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe)); 383 else 384 res1 = 0; 385 386 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 387 res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe)); 388 else 389 res2 = 0; 390 391 display_pipe_crc_irq_handler(dev_priv, pipe, 392 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)), 393 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)), 394 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)), 395 res1, res2); 396 } 397 398 void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) 399 { 400 enum pipe pipe; 401 402 for_each_pipe(dev_priv, pipe) { 403 intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe), 404 PIPESTAT_INT_STATUS_MASK | 405 PIPE_FIFO_UNDERRUN_STATUS); 406 407 dev_priv->pipestat_irq_mask[pipe] = 0; 408 } 409 } 410 411 void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, 412 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 413 { 414 enum pipe pipe; 415 416 spin_lock(&dev_priv->irq_lock); 417 418 if (!dev_priv->display_irqs_enabled) { 419 spin_unlock(&dev_priv->irq_lock); 420 return; 421 } 422 423 for_each_pipe(dev_priv, pipe) { 424 i915_reg_t reg; 425 u32 status_mask, enable_mask, iir_bit = 0; 426 427 /* 428 * PIPESTAT bits get signalled even when the interrupt is 429 * disabled with the mask bits, and some of the status bits do 430 * not generate interrupts at all (like the underrun bit). Hence 431 * we need to be careful that we only handle what we want to 432 * handle. 433 */ 434 435 /* fifo underruns are filterered in the underrun handler. */ 436 status_mask = PIPE_FIFO_UNDERRUN_STATUS; 437 438 switch (pipe) { 439 default: 440 case PIPE_A: 441 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; 442 break; 443 case PIPE_B: 444 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; 445 break; 446 case PIPE_C: 447 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; 448 break; 449 } 450 if (iir & iir_bit) 451 status_mask |= dev_priv->pipestat_irq_mask[pipe]; 452 453 if (!status_mask) 454 continue; 455 456 reg = PIPESTAT(pipe); 457 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask; 458 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 459 460 /* 461 * Clear the PIPE*STAT regs before the IIR 462 * 463 * Toggle the enable bits to make sure we get an 464 * edge in the ISR pipe event bit if we don't clear 465 * all the enabled status bits. Otherwise the edge 466 * triggered IIR on i965/g4x wouldn't notice that 467 * an interrupt is still pending. 468 */ 469 if (pipe_stats[pipe]) { 470 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]); 471 intel_uncore_write(&dev_priv->uncore, reg, enable_mask); 472 } 473 } 474 spin_unlock(&dev_priv->irq_lock); 475 } 476 477 void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv, 478 u16 iir, u32 pipe_stats[I915_MAX_PIPES]) 479 { 480 enum pipe pipe; 481 482 for_each_pipe(dev_priv, pipe) { 483 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 484 intel_handle_vblank(dev_priv, pipe); 485 486 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 487 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 488 489 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 490 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 491 } 492 } 493 494 void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv, 495 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 496 { 497 bool blc_event = false; 498 enum pipe pipe; 499 500 for_each_pipe(dev_priv, pipe) { 501 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 502 intel_handle_vblank(dev_priv, pipe); 503 504 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 505 blc_event = true; 506 507 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 508 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 509 510 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 511 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 512 } 513 514 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 515 intel_opregion_asle_intr(dev_priv); 516 } 517 518 void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv, 519 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 520 { 521 bool blc_event = false; 522 enum pipe pipe; 523 524 for_each_pipe(dev_priv, pipe) { 525 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 526 intel_handle_vblank(dev_priv, pipe); 527 528 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 529 blc_event = true; 530 531 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 532 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 533 534 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 535 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 536 } 537 538 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 539 intel_opregion_asle_intr(dev_priv); 540 541 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 542 intel_gmbus_irq_handler(dev_priv); 543 } 544 545 void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, 546 u32 pipe_stats[I915_MAX_PIPES]) 547 { 548 enum pipe pipe; 549 550 for_each_pipe(dev_priv, pipe) { 551 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 552 intel_handle_vblank(dev_priv, pipe); 553 554 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) 555 flip_done_handler(dev_priv, pipe); 556 557 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 558 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 559 560 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 561 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 562 } 563 564 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 565 intel_gmbus_irq_handler(dev_priv); 566 } 567 568 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 569 { 570 enum pipe pipe; 571 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; 572 573 ibx_hpd_irq_handler(dev_priv, hotplug_trigger); 574 575 if (pch_iir & SDE_AUDIO_POWER_MASK) { 576 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> 577 SDE_AUDIO_POWER_SHIFT); 578 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n", 579 port_name(port)); 580 } 581 582 if (pch_iir & SDE_AUX_MASK) 583 intel_dp_aux_irq_handler(dev_priv); 584 585 if (pch_iir & SDE_GMBUS) 586 intel_gmbus_irq_handler(dev_priv); 587 588 if (pch_iir & SDE_AUDIO_HDCP_MASK) 589 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n"); 590 591 if (pch_iir & SDE_AUDIO_TRANS_MASK) 592 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n"); 593 594 if (pch_iir & SDE_POISON) 595 drm_err(&dev_priv->drm, "PCH poison interrupt\n"); 596 597 if (pch_iir & SDE_FDI_MASK) { 598 for_each_pipe(dev_priv, pipe) 599 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", 600 pipe_name(pipe), 601 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); 602 } 603 604 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 605 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n"); 606 607 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 608 drm_dbg(&dev_priv->drm, 609 "PCH transcoder CRC error interrupt\n"); 610 611 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 612 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); 613 614 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 615 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); 616 } 617 618 static void ivb_err_int_handler(struct drm_i915_private *dev_priv) 619 { 620 u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT); 621 enum pipe pipe; 622 623 if (err_int & ERR_INT_POISON) 624 drm_err(&dev_priv->drm, "Poison interrupt\n"); 625 626 for_each_pipe(dev_priv, pipe) { 627 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) 628 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 629 630 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { 631 if (IS_IVYBRIDGE(dev_priv)) 632 ivb_pipe_crc_irq_handler(dev_priv, pipe); 633 else 634 hsw_pipe_crc_irq_handler(dev_priv, pipe); 635 } 636 } 637 638 intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int); 639 } 640 641 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) 642 { 643 u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT); 644 enum pipe pipe; 645 646 if (serr_int & SERR_INT_POISON) 647 drm_err(&dev_priv->drm, "PCH poison interrupt\n"); 648 649 for_each_pipe(dev_priv, pipe) 650 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe)) 651 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe); 652 653 intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int); 654 } 655 656 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 657 { 658 enum pipe pipe; 659 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; 660 661 ibx_hpd_irq_handler(dev_priv, hotplug_trigger); 662 663 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { 664 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 665 SDE_AUDIO_POWER_SHIFT_CPT); 666 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n", 667 port_name(port)); 668 } 669 670 if (pch_iir & SDE_AUX_MASK_CPT) 671 intel_dp_aux_irq_handler(dev_priv); 672 673 if (pch_iir & SDE_GMBUS_CPT) 674 intel_gmbus_irq_handler(dev_priv); 675 676 if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 677 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n"); 678 679 if (pch_iir & SDE_AUDIO_CP_CHG_CPT) 680 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n"); 681 682 if (pch_iir & SDE_FDI_MASK_CPT) { 683 for_each_pipe(dev_priv, pipe) 684 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", 685 pipe_name(pipe), 686 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); 687 } 688 689 if (pch_iir & SDE_ERROR_CPT) 690 cpt_serr_int_handler(dev_priv); 691 } 692 693 void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) 694 { 695 enum pipe pipe; 696 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; 697 698 if (hotplug_trigger) 699 ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 700 701 if (de_iir & DE_AUX_CHANNEL_A) 702 intel_dp_aux_irq_handler(dev_priv); 703 704 if (de_iir & DE_GSE) 705 intel_opregion_asle_intr(dev_priv); 706 707 if (de_iir & DE_POISON) 708 drm_err(&dev_priv->drm, "Poison interrupt\n"); 709 710 for_each_pipe(dev_priv, pipe) { 711 if (de_iir & DE_PIPE_VBLANK(pipe)) 712 intel_handle_vblank(dev_priv, pipe); 713 714 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) 715 flip_done_handler(dev_priv, pipe); 716 717 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) 718 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 719 720 if (de_iir & DE_PIPE_CRC_DONE(pipe)) 721 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 722 } 723 724 /* check event from PCH */ 725 if (de_iir & DE_PCH_EVENT) { 726 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); 727 728 if (HAS_PCH_CPT(dev_priv)) 729 cpt_irq_handler(dev_priv, pch_iir); 730 else 731 ibx_irq_handler(dev_priv, pch_iir); 732 733 /* should clear PCH hotplug event before clear CPU irq */ 734 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); 735 } 736 737 if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT) 738 gen5_rps_irq_handler(&to_gt(dev_priv)->rps); 739 } 740 741 void ivb_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) 742 { 743 enum pipe pipe; 744 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; 745 746 if (hotplug_trigger) 747 ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 748 749 if (de_iir & DE_ERR_INT_IVB) 750 ivb_err_int_handler(dev_priv); 751 752 if (de_iir & DE_AUX_CHANNEL_A_IVB) 753 intel_dp_aux_irq_handler(dev_priv); 754 755 if (de_iir & DE_GSE_IVB) 756 intel_opregion_asle_intr(dev_priv); 757 758 for_each_pipe(dev_priv, pipe) { 759 if (de_iir & DE_PIPE_VBLANK_IVB(pipe)) 760 intel_handle_vblank(dev_priv, pipe); 761 762 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) 763 flip_done_handler(dev_priv, pipe); 764 } 765 766 /* check event from PCH */ 767 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { 768 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); 769 770 cpt_irq_handler(dev_priv, pch_iir); 771 772 /* clear PCH hotplug event before clear CPU irq */ 773 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); 774 } 775 } 776 777 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) 778 { 779 u32 mask; 780 781 if (DISPLAY_VER(dev_priv) >= 14) 782 return TGL_DE_PORT_AUX_DDIA | 783 TGL_DE_PORT_AUX_DDIB; 784 else if (DISPLAY_VER(dev_priv) >= 13) 785 return TGL_DE_PORT_AUX_DDIA | 786 TGL_DE_PORT_AUX_DDIB | 787 TGL_DE_PORT_AUX_DDIC | 788 XELPD_DE_PORT_AUX_DDID | 789 XELPD_DE_PORT_AUX_DDIE | 790 TGL_DE_PORT_AUX_USBC1 | 791 TGL_DE_PORT_AUX_USBC2 | 792 TGL_DE_PORT_AUX_USBC3 | 793 TGL_DE_PORT_AUX_USBC4; 794 else if (DISPLAY_VER(dev_priv) >= 12) 795 return TGL_DE_PORT_AUX_DDIA | 796 TGL_DE_PORT_AUX_DDIB | 797 TGL_DE_PORT_AUX_DDIC | 798 TGL_DE_PORT_AUX_USBC1 | 799 TGL_DE_PORT_AUX_USBC2 | 800 TGL_DE_PORT_AUX_USBC3 | 801 TGL_DE_PORT_AUX_USBC4 | 802 TGL_DE_PORT_AUX_USBC5 | 803 TGL_DE_PORT_AUX_USBC6; 804 805 mask = GEN8_AUX_CHANNEL_A; 806 if (DISPLAY_VER(dev_priv) >= 9) 807 mask |= GEN9_AUX_CHANNEL_B | 808 GEN9_AUX_CHANNEL_C | 809 GEN9_AUX_CHANNEL_D; 810 811 if (DISPLAY_VER(dev_priv) == 11) { 812 mask |= ICL_AUX_CHANNEL_F; 813 mask |= ICL_AUX_CHANNEL_E; 814 } 815 816 return mask; 817 } 818 819 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) 820 { 821 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) 822 return RKL_DE_PIPE_IRQ_FAULT_ERRORS; 823 else if (DISPLAY_VER(dev_priv) >= 11) 824 return GEN11_DE_PIPE_IRQ_FAULT_ERRORS; 825 else if (DISPLAY_VER(dev_priv) >= 9) 826 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS; 827 else 828 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS; 829 } 830 831 static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv) 832 { 833 wake_up_all(&dev_priv->display.pmdemand.waitqueue); 834 } 835 836 static void 837 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) 838 { 839 bool found = false; 840 841 if (DISPLAY_VER(dev_priv) >= 14) { 842 if (iir & (XELPDP_PMDEMAND_RSP | 843 XELPDP_PMDEMAND_RSPTOUT_ERR)) { 844 if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR) 845 drm_dbg(&dev_priv->drm, 846 "Error waiting for Punit PM Demand Response\n"); 847 848 intel_pmdemand_irq_handler(dev_priv); 849 found = true; 850 } 851 } else if (iir & GEN8_DE_MISC_GSE) { 852 intel_opregion_asle_intr(dev_priv); 853 found = true; 854 } 855 856 if (iir & GEN8_DE_EDP_PSR) { 857 struct intel_encoder *encoder; 858 u32 psr_iir; 859 i915_reg_t iir_reg; 860 861 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 862 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 863 864 if (DISPLAY_VER(dev_priv) >= 12) 865 iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder); 866 else 867 iir_reg = EDP_PSR_IIR; 868 869 psr_iir = intel_uncore_rmw(&dev_priv->uncore, iir_reg, 0, 0); 870 871 if (psr_iir) 872 found = true; 873 874 intel_psr_irq_handler(intel_dp, psr_iir); 875 876 /* prior GEN12 only have one EDP PSR */ 877 if (DISPLAY_VER(dev_priv) < 12) 878 break; 879 } 880 } 881 882 if (!found) 883 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n"); 884 } 885 886 static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, 887 u32 te_trigger) 888 { 889 enum pipe pipe = INVALID_PIPE; 890 enum transcoder dsi_trans; 891 enum port port; 892 u32 val; 893 894 /* 895 * Incase of dual link, TE comes from DSI_1 896 * this is to check if dual link is enabled 897 */ 898 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0)); 899 val &= PORT_SYNC_MODE_ENABLE; 900 901 /* 902 * if dual link is enabled, then read DSI_0 903 * transcoder registers 904 */ 905 port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ? 906 PORT_A : PORT_B; 907 dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; 908 909 /* Check if DSI configured in command mode */ 910 val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans)); 911 val = val & OP_MODE_MASK; 912 913 if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) { 914 drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n"); 915 return; 916 } 917 918 /* Get PIPE for handling VBLANK event */ 919 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans)); 920 switch (val & TRANS_DDI_EDP_INPUT_MASK) { 921 case TRANS_DDI_EDP_INPUT_A_ON: 922 pipe = PIPE_A; 923 break; 924 case TRANS_DDI_EDP_INPUT_B_ONOFF: 925 pipe = PIPE_B; 926 break; 927 case TRANS_DDI_EDP_INPUT_C_ONOFF: 928 pipe = PIPE_C; 929 break; 930 default: 931 drm_err(&dev_priv->drm, "Invalid PIPE\n"); 932 return; 933 } 934 935 intel_handle_vblank(dev_priv, pipe); 936 937 /* clear TE in dsi IIR */ 938 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; 939 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), 0, 0); 940 } 941 942 static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915) 943 { 944 if (DISPLAY_VER(i915) >= 9) 945 return GEN9_PIPE_PLANE1_FLIP_DONE; 946 else 947 return GEN8_PIPE_PRIMARY_FLIP_DONE; 948 } 949 950 u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv) 951 { 952 u32 mask = GEN8_PIPE_FIFO_UNDERRUN; 953 954 if (DISPLAY_VER(dev_priv) >= 13) 955 mask |= XELPD_PIPE_SOFT_UNDERRUN | 956 XELPD_PIPE_HARD_UNDERRUN; 957 958 return mask; 959 } 960 961 static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32 *pch_iir, u32 *pica_iir) 962 { 963 u32 pica_ier = 0; 964 965 *pica_iir = 0; 966 *pch_iir = intel_de_read(i915, SDEIIR); 967 if (!*pch_iir) 968 return; 969 970 /** 971 * PICA IER must be disabled/re-enabled around clearing PICA IIR and 972 * SDEIIR, to avoid losing PICA IRQs and to ensure that such IRQs set 973 * their flags both in the PICA and SDE IIR. 974 */ 975 if (*pch_iir & SDE_PICAINTERRUPT) { 976 drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTP); 977 978 pica_ier = intel_de_rmw(i915, PICAINTERRUPT_IER, ~0, 0); 979 *pica_iir = intel_de_read(i915, PICAINTERRUPT_IIR); 980 intel_de_write(i915, PICAINTERRUPT_IIR, *pica_iir); 981 } 982 983 intel_de_write(i915, SDEIIR, *pch_iir); 984 985 if (pica_ier) 986 intel_de_write(i915, PICAINTERRUPT_IER, pica_ier); 987 } 988 989 void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) 990 { 991 u32 iir; 992 enum pipe pipe; 993 994 drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); 995 996 if (master_ctl & GEN8_DE_MISC_IRQ) { 997 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR); 998 if (iir) { 999 intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir); 1000 gen8_de_misc_irq_handler(dev_priv, iir); 1001 } else { 1002 drm_err_ratelimited(&dev_priv->drm, 1003 "The master control interrupt lied (DE MISC)!\n"); 1004 } 1005 } 1006 1007 if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) { 1008 iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR); 1009 if (iir) { 1010 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir); 1011 gen11_hpd_irq_handler(dev_priv, iir); 1012 } else { 1013 drm_err_ratelimited(&dev_priv->drm, 1014 "The master control interrupt lied, (DE HPD)!\n"); 1015 } 1016 } 1017 1018 if (master_ctl & GEN8_DE_PORT_IRQ) { 1019 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR); 1020 if (iir) { 1021 bool found = false; 1022 1023 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir); 1024 1025 if (iir & gen8_de_port_aux_mask(dev_priv)) { 1026 intel_dp_aux_irq_handler(dev_priv); 1027 found = true; 1028 } 1029 1030 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1031 u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK; 1032 1033 if (hotplug_trigger) { 1034 bxt_hpd_irq_handler(dev_priv, hotplug_trigger); 1035 found = true; 1036 } 1037 } else if (IS_BROADWELL(dev_priv)) { 1038 u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK; 1039 1040 if (hotplug_trigger) { 1041 ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 1042 found = true; 1043 } 1044 } 1045 1046 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1047 (iir & BXT_DE_PORT_GMBUS)) { 1048 intel_gmbus_irq_handler(dev_priv); 1049 found = true; 1050 } 1051 1052 if (DISPLAY_VER(dev_priv) >= 11) { 1053 u32 te_trigger = iir & (DSI0_TE | DSI1_TE); 1054 1055 if (te_trigger) { 1056 gen11_dsi_te_interrupt_handler(dev_priv, te_trigger); 1057 found = true; 1058 } 1059 } 1060 1061 if (!found) 1062 drm_err_ratelimited(&dev_priv->drm, 1063 "Unexpected DE Port interrupt\n"); 1064 } else { 1065 drm_err_ratelimited(&dev_priv->drm, 1066 "The master control interrupt lied (DE PORT)!\n"); 1067 } 1068 } 1069 1070 for_each_pipe(dev_priv, pipe) { 1071 u32 fault_errors; 1072 1073 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) 1074 continue; 1075 1076 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)); 1077 if (!iir) { 1078 drm_err_ratelimited(&dev_priv->drm, 1079 "The master control interrupt lied (DE PIPE)!\n"); 1080 continue; 1081 } 1082 1083 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); 1084 1085 if (iir & GEN8_PIPE_VBLANK) 1086 intel_handle_vblank(dev_priv, pipe); 1087 1088 if (iir & gen8_de_pipe_flip_done_mask(dev_priv)) 1089 flip_done_handler(dev_priv, pipe); 1090 1091 if (iir & GEN8_PIPE_CDCLK_CRC_DONE) 1092 hsw_pipe_crc_irq_handler(dev_priv, pipe); 1093 1094 if (iir & gen8_de_pipe_underrun_mask(dev_priv)) 1095 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 1096 1097 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv); 1098 if (fault_errors) 1099 drm_err_ratelimited(&dev_priv->drm, 1100 "Fault errors on pipe %c: 0x%08x\n", 1101 pipe_name(pipe), 1102 fault_errors); 1103 } 1104 1105 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && 1106 master_ctl & GEN8_DE_PCH_IRQ) { 1107 u32 pica_iir; 1108 1109 /* 1110 * FIXME(BDW): Assume for now that the new interrupt handling 1111 * scheme also closed the SDE interrupt handling race we've seen 1112 * on older pch-split platforms. But this needs testing. 1113 */ 1114 gen8_read_and_ack_pch_irqs(dev_priv, &iir, &pica_iir); 1115 if (iir) { 1116 if (pica_iir) 1117 xelpdp_pica_irq_handler(dev_priv, pica_iir); 1118 1119 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 1120 icp_irq_handler(dev_priv, iir); 1121 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) 1122 spt_irq_handler(dev_priv, iir); 1123 else 1124 cpt_irq_handler(dev_priv, iir); 1125 } else { 1126 /* 1127 * Like on previous PCH there seems to be something 1128 * fishy going on with forwarding PCH interrupts. 1129 */ 1130 drm_dbg(&dev_priv->drm, 1131 "The master control interrupt lied (SDE)!\n"); 1132 } 1133 } 1134 } 1135 1136 u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl) 1137 { 1138 void __iomem * const regs = i915->uncore.regs; 1139 u32 iir; 1140 1141 if (!(master_ctl & GEN11_GU_MISC_IRQ)) 1142 return 0; 1143 1144 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR); 1145 if (likely(iir)) 1146 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir); 1147 1148 return iir; 1149 } 1150 1151 void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir) 1152 { 1153 if (iir & GEN11_GU_MISC_GSE) 1154 intel_opregion_asle_intr(i915); 1155 } 1156 1157 void gen11_display_irq_handler(struct drm_i915_private *i915) 1158 { 1159 void __iomem * const regs = i915->uncore.regs; 1160 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL); 1161 1162 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1163 /* 1164 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ 1165 * for the display related bits. 1166 */ 1167 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0); 1168 gen8_de_irq_handler(i915, disp_ctl); 1169 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 1170 GEN11_DISPLAY_IRQ_ENABLE); 1171 1172 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1173 } 1174 1175 /* Called from drm generic code, passed 'crtc' which 1176 * we use as a pipe index 1177 */ 1178 int i8xx_enable_vblank(struct drm_crtc *crtc) 1179 { 1180 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1181 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1182 unsigned long irqflags; 1183 1184 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1185 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); 1186 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1187 1188 return 0; 1189 } 1190 1191 int i915gm_enable_vblank(struct drm_crtc *crtc) 1192 { 1193 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1194 1195 /* 1196 * Vblank interrupts fail to wake the device up from C2+. 1197 * Disabling render clock gating during C-states avoids 1198 * the problem. There is a small power cost so we do this 1199 * only when vblank interrupts are actually enabled. 1200 */ 1201 if (dev_priv->vblank_enabled++ == 0) 1202 intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); 1203 1204 return i8xx_enable_vblank(crtc); 1205 } 1206 1207 int i965_enable_vblank(struct drm_crtc *crtc) 1208 { 1209 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1210 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1211 unsigned long irqflags; 1212 1213 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1214 i915_enable_pipestat(dev_priv, pipe, 1215 PIPE_START_VBLANK_INTERRUPT_STATUS); 1216 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1217 1218 return 0; 1219 } 1220 1221 int ilk_enable_vblank(struct drm_crtc *crtc) 1222 { 1223 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1224 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1225 unsigned long irqflags; 1226 u32 bit = DISPLAY_VER(dev_priv) >= 7 ? 1227 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); 1228 1229 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1230 ilk_enable_display_irq(dev_priv, bit); 1231 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1232 1233 /* Even though there is no DMC, frame counter can get stuck when 1234 * PSR is active as no frames are generated. 1235 */ 1236 if (HAS_PSR(dev_priv)) 1237 drm_crtc_vblank_restore(crtc); 1238 1239 return 0; 1240 } 1241 1242 static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc, 1243 bool enable) 1244 { 1245 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 1246 enum port port; 1247 1248 if (!(intel_crtc->mode_flags & 1249 (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) 1250 return false; 1251 1252 /* for dual link cases we consider TE from slave */ 1253 if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 1254 port = PORT_B; 1255 else 1256 port = PORT_A; 1257 1258 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_MASK_REG(port), DSI_TE_EVENT, 1259 enable ? 0 : DSI_TE_EVENT); 1260 1261 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), 0, 0); 1262 1263 return true; 1264 } 1265 1266 int bdw_enable_vblank(struct drm_crtc *_crtc) 1267 { 1268 struct intel_crtc *crtc = to_intel_crtc(_crtc); 1269 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1270 enum pipe pipe = crtc->pipe; 1271 unsigned long irqflags; 1272 1273 if (gen11_dsi_configure_te(crtc, true)) 1274 return 0; 1275 1276 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1277 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); 1278 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1279 1280 /* Even if there is no DMC, frame counter can get stuck when 1281 * PSR is active as no frames are generated, so check only for PSR. 1282 */ 1283 if (HAS_PSR(dev_priv)) 1284 drm_crtc_vblank_restore(&crtc->base); 1285 1286 return 0; 1287 } 1288 1289 /* Called from drm generic code, passed 'crtc' which 1290 * we use as a pipe index 1291 */ 1292 void i8xx_disable_vblank(struct drm_crtc *crtc) 1293 { 1294 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1295 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1296 unsigned long irqflags; 1297 1298 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1299 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); 1300 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1301 } 1302 1303 void i915gm_disable_vblank(struct drm_crtc *crtc) 1304 { 1305 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1306 1307 i8xx_disable_vblank(crtc); 1308 1309 if (--dev_priv->vblank_enabled == 0) 1310 intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); 1311 } 1312 1313 void i965_disable_vblank(struct drm_crtc *crtc) 1314 { 1315 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1316 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1317 unsigned long irqflags; 1318 1319 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1320 i915_disable_pipestat(dev_priv, pipe, 1321 PIPE_START_VBLANK_INTERRUPT_STATUS); 1322 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1323 } 1324 1325 void ilk_disable_vblank(struct drm_crtc *crtc) 1326 { 1327 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 1328 enum pipe pipe = to_intel_crtc(crtc)->pipe; 1329 unsigned long irqflags; 1330 u32 bit = DISPLAY_VER(dev_priv) >= 7 ? 1331 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); 1332 1333 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1334 ilk_disable_display_irq(dev_priv, bit); 1335 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1336 } 1337 1338 void bdw_disable_vblank(struct drm_crtc *_crtc) 1339 { 1340 struct intel_crtc *crtc = to_intel_crtc(_crtc); 1341 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1342 enum pipe pipe = crtc->pipe; 1343 unsigned long irqflags; 1344 1345 if (gen11_dsi_configure_te(crtc, false)) 1346 return; 1347 1348 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1349 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); 1350 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1351 } 1352 1353 void vlv_display_irq_reset(struct drm_i915_private *dev_priv) 1354 { 1355 struct intel_uncore *uncore = &dev_priv->uncore; 1356 1357 if (IS_CHERRYVIEW(dev_priv)) 1358 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV); 1359 else 1360 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_VLV); 1361 1362 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); 1363 intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT, 0, 0); 1364 1365 i9xx_pipestat_irq_reset(dev_priv); 1366 1367 GEN3_IRQ_RESET(uncore, VLV_); 1368 dev_priv->irq_mask = ~0u; 1369 } 1370 1371 void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) 1372 { 1373 struct intel_uncore *uncore = &dev_priv->uncore; 1374 1375 u32 pipestat_mask; 1376 u32 enable_mask; 1377 enum pipe pipe; 1378 1379 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; 1380 1381 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 1382 for_each_pipe(dev_priv, pipe) 1383 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); 1384 1385 enable_mask = I915_DISPLAY_PORT_INTERRUPT | 1386 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1387 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1388 I915_LPE_PIPE_A_INTERRUPT | 1389 I915_LPE_PIPE_B_INTERRUPT; 1390 1391 if (IS_CHERRYVIEW(dev_priv)) 1392 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | 1393 I915_LPE_PIPE_C_INTERRUPT; 1394 1395 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u); 1396 1397 dev_priv->irq_mask = ~enable_mask; 1398 1399 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask); 1400 } 1401 1402 void gen8_display_irq_reset(struct drm_i915_private *dev_priv) 1403 { 1404 struct intel_uncore *uncore = &dev_priv->uncore; 1405 enum pipe pipe; 1406 1407 if (!HAS_DISPLAY(dev_priv)) 1408 return; 1409 1410 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 1411 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 1412 1413 for_each_pipe(dev_priv, pipe) 1414 if (intel_display_power_is_enabled(dev_priv, 1415 POWER_DOMAIN_PIPE(pipe))) 1416 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 1417 1418 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); 1419 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); 1420 } 1421 1422 void gen11_display_irq_reset(struct drm_i915_private *dev_priv) 1423 { 1424 struct intel_uncore *uncore = &dev_priv->uncore; 1425 enum pipe pipe; 1426 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1427 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 1428 1429 if (!HAS_DISPLAY(dev_priv)) 1430 return; 1431 1432 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0); 1433 1434 if (DISPLAY_VER(dev_priv) >= 12) { 1435 enum transcoder trans; 1436 1437 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { 1438 enum intel_display_power_domain domain; 1439 1440 domain = POWER_DOMAIN_TRANSCODER(trans); 1441 if (!intel_display_power_is_enabled(dev_priv, domain)) 1442 continue; 1443 1444 intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff); 1445 intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff); 1446 } 1447 } else { 1448 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 1449 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 1450 } 1451 1452 for_each_pipe(dev_priv, pipe) 1453 if (intel_display_power_is_enabled(dev_priv, 1454 POWER_DOMAIN_PIPE(pipe))) 1455 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 1456 1457 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); 1458 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); 1459 1460 if (DISPLAY_VER(dev_priv) >= 14) 1461 GEN3_IRQ_RESET(uncore, PICAINTERRUPT_); 1462 else 1463 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_); 1464 1465 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 1466 GEN3_IRQ_RESET(uncore, SDE); 1467 } 1468 1469 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, 1470 u8 pipe_mask) 1471 { 1472 struct intel_uncore *uncore = &dev_priv->uncore; 1473 u32 extra_ier = GEN8_PIPE_VBLANK | 1474 gen8_de_pipe_underrun_mask(dev_priv) | 1475 gen8_de_pipe_flip_done_mask(dev_priv); 1476 enum pipe pipe; 1477 1478 spin_lock_irq(&dev_priv->irq_lock); 1479 1480 if (!intel_irqs_enabled(dev_priv)) { 1481 spin_unlock_irq(&dev_priv->irq_lock); 1482 return; 1483 } 1484 1485 for_each_pipe_masked(dev_priv, pipe, pipe_mask) 1486 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, 1487 dev_priv->de_irq_mask[pipe], 1488 ~dev_priv->de_irq_mask[pipe] | extra_ier); 1489 1490 spin_unlock_irq(&dev_priv->irq_lock); 1491 } 1492 1493 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, 1494 u8 pipe_mask) 1495 { 1496 struct intel_uncore *uncore = &dev_priv->uncore; 1497 enum pipe pipe; 1498 1499 spin_lock_irq(&dev_priv->irq_lock); 1500 1501 if (!intel_irqs_enabled(dev_priv)) { 1502 spin_unlock_irq(&dev_priv->irq_lock); 1503 return; 1504 } 1505 1506 for_each_pipe_masked(dev_priv, pipe, pipe_mask) 1507 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 1508 1509 spin_unlock_irq(&dev_priv->irq_lock); 1510 1511 /* make sure we're done processing display irqs */ 1512 intel_synchronize_irq(dev_priv); 1513 } 1514 1515 /* 1516 * SDEIER is also touched by the interrupt handler to work around missed PCH 1517 * interrupts. Hence we can't update it after the interrupt handler is enabled - 1518 * instead we unconditionally enable all PCH interrupt sources here, but then 1519 * only unmask them as needed with SDEIMR. 1520 * 1521 * Note that we currently do this after installing the interrupt handler, 1522 * but before we enable the master interrupt. That should be sufficient 1523 * to avoid races with the irq handler, assuming we have MSI. Shared legacy 1524 * interrupts could still race. 1525 */ 1526 void ibx_irq_postinstall(struct drm_i915_private *dev_priv) 1527 { 1528 struct intel_uncore *uncore = &dev_priv->uncore; 1529 u32 mask; 1530 1531 if (HAS_PCH_NOP(dev_priv)) 1532 return; 1533 1534 if (HAS_PCH_IBX(dev_priv)) 1535 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; 1536 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) 1537 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; 1538 else 1539 mask = SDE_GMBUS_CPT; 1540 1541 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); 1542 } 1543 1544 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) 1545 { 1546 lockdep_assert_held(&dev_priv->irq_lock); 1547 1548 if (dev_priv->display_irqs_enabled) 1549 return; 1550 1551 dev_priv->display_irqs_enabled = true; 1552 1553 if (intel_irqs_enabled(dev_priv)) { 1554 vlv_display_irq_reset(dev_priv); 1555 vlv_display_irq_postinstall(dev_priv); 1556 } 1557 } 1558 1559 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) 1560 { 1561 lockdep_assert_held(&dev_priv->irq_lock); 1562 1563 if (!dev_priv->display_irqs_enabled) 1564 return; 1565 1566 dev_priv->display_irqs_enabled = false; 1567 1568 if (intel_irqs_enabled(dev_priv)) 1569 vlv_display_irq_reset(dev_priv); 1570 } 1571 1572 void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 1573 { 1574 struct intel_uncore *uncore = &dev_priv->uncore; 1575 1576 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) | 1577 GEN8_PIPE_CDCLK_CRC_DONE; 1578 u32 de_pipe_enables; 1579 u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); 1580 u32 de_port_enables; 1581 u32 de_misc_masked = GEN8_DE_EDP_PSR; 1582 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1583 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 1584 enum pipe pipe; 1585 1586 if (!HAS_DISPLAY(dev_priv)) 1587 return; 1588 1589 if (DISPLAY_VER(dev_priv) <= 10) 1590 de_misc_masked |= GEN8_DE_MISC_GSE; 1591 1592 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1593 de_port_masked |= BXT_DE_PORT_GMBUS; 1594 1595 if (DISPLAY_VER(dev_priv) >= 14) { 1596 de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR | 1597 XELPDP_PMDEMAND_RSP; 1598 } else if (DISPLAY_VER(dev_priv) >= 11) { 1599 enum port port; 1600 1601 if (intel_bios_is_dsi_present(dev_priv, &port)) 1602 de_port_masked |= DSI0_TE | DSI1_TE; 1603 } 1604 1605 de_pipe_enables = de_pipe_masked | 1606 GEN8_PIPE_VBLANK | 1607 gen8_de_pipe_underrun_mask(dev_priv) | 1608 gen8_de_pipe_flip_done_mask(dev_priv); 1609 1610 de_port_enables = de_port_masked; 1611 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1612 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; 1613 else if (IS_BROADWELL(dev_priv)) 1614 de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK; 1615 1616 if (DISPLAY_VER(dev_priv) >= 12) { 1617 enum transcoder trans; 1618 1619 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { 1620 enum intel_display_power_domain domain; 1621 1622 domain = POWER_DOMAIN_TRANSCODER(trans); 1623 if (!intel_display_power_is_enabled(dev_priv, domain)) 1624 continue; 1625 1626 gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans)); 1627 } 1628 } else { 1629 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); 1630 } 1631 1632 for_each_pipe(dev_priv, pipe) { 1633 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked; 1634 1635 if (intel_display_power_is_enabled(dev_priv, 1636 POWER_DOMAIN_PIPE(pipe))) 1637 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, 1638 dev_priv->de_irq_mask[pipe], 1639 de_pipe_enables); 1640 } 1641 1642 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables); 1643 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); 1644 1645 if (IS_DISPLAY_VER(dev_priv, 11, 13)) { 1646 u32 de_hpd_masked = 0; 1647 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | 1648 GEN11_DE_TBT_HOTPLUG_MASK; 1649 1650 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked, 1651 de_hpd_enables); 1652 } 1653 } 1654 1655 void mtp_irq_postinstall(struct drm_i915_private *i915) 1656 { 1657 struct intel_uncore *uncore = &i915->uncore; 1658 u32 sde_mask = SDE_GMBUS_ICP | SDE_PICAINTERRUPT; 1659 u32 de_hpd_mask = XELPDP_AUX_TC_MASK; 1660 u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK | 1661 XELPDP_TBT_HOTPLUG_MASK; 1662 1663 GEN3_IRQ_INIT(uncore, PICAINTERRUPT_, ~de_hpd_mask, 1664 de_hpd_enables); 1665 1666 GEN3_IRQ_INIT(uncore, SDE, ~sde_mask, 0xffffffff); 1667 } 1668 1669 void icp_irq_postinstall(struct drm_i915_private *dev_priv) 1670 { 1671 struct intel_uncore *uncore = &dev_priv->uncore; 1672 u32 mask = SDE_GMBUS_ICP; 1673 1674 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); 1675 } 1676 1677 void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv) 1678 { 1679 if (!HAS_DISPLAY(dev_priv)) 1680 return; 1681 1682 gen8_de_irq_postinstall(dev_priv); 1683 1684 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, 1685 GEN11_DISPLAY_IRQ_ENABLE); 1686 } 1687 1688