1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022-2023 Intel Corporation 4 * 5 * High level display driver entry points. This is a layer between top level 6 * driver code and low level display functionality; no low level display code or 7 * details here. 8 */ 9 10 #include <linux/vga_switcheroo.h> 11 #include <acpi/video.h> 12 #include <drm/display/drm_dp_mst_helper.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_mode_config.h> 15 #include <drm/drm_privacy_screen_consumer.h> 16 #include <drm/drm_probe_helper.h> 17 #include <drm/drm_vblank.h> 18 19 #include "i915_drv.h" 20 #include "i9xx_wm.h" 21 #include "intel_acpi.h" 22 #include "intel_atomic.h" 23 #include "intel_audio.h" 24 #include "intel_bios.h" 25 #include "intel_bw.h" 26 #include "intel_cdclk.h" 27 #include "intel_color.h" 28 #include "intel_crtc.h" 29 #include "intel_display_debugfs.h" 30 #include "intel_display_driver.h" 31 #include "intel_display_power.h" 32 #include "intel_display_types.h" 33 #include "intel_dkl_phy.h" 34 #include "intel_dmc.h" 35 #include "intel_dp.h" 36 #include "intel_dpll.h" 37 #include "intel_dpll_mgr.h" 38 #include "intel_fb.h" 39 #include "intel_fbc.h" 40 #include "intel_fbdev.h" 41 #include "intel_fdi.h" 42 #include "intel_gmbus.h" 43 #include "intel_hdcp.h" 44 #include "intel_hotplug.h" 45 #include "intel_hti.h" 46 #include "intel_modeset_setup.h" 47 #include "intel_opregion.h" 48 #include "intel_overlay.h" 49 #include "intel_plane_initial.h" 50 #include "intel_pmdemand.h" 51 #include "intel_pps.h" 52 #include "intel_quirks.h" 53 #include "intel_vga.h" 54 #include "intel_wm.h" 55 #include "skl_watermark.h" 56 57 bool intel_display_driver_probe_defer(struct pci_dev *pdev) 58 { 59 struct drm_privacy_screen *privacy_screen; 60 61 /* 62 * apple-gmux is needed on dual GPU MacBook Pro 63 * to probe the panel if we're the inactive GPU. 64 */ 65 if (vga_switcheroo_client_probe_defer(pdev)) 66 return true; 67 68 /* If the LCD panel has a privacy-screen, wait for it */ 69 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 70 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 71 return true; 72 73 drm_privacy_screen_put(privacy_screen); 74 75 return false; 76 } 77 78 void intel_display_driver_init_hw(struct drm_i915_private *i915) 79 { 80 struct intel_cdclk_state *cdclk_state; 81 82 if (!HAS_DISPLAY(i915)) 83 return; 84 85 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); 86 87 intel_update_cdclk(i915); 88 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); 89 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; 90 } 91 92 static const struct drm_mode_config_funcs intel_mode_funcs = { 93 .fb_create = intel_user_framebuffer_create, 94 .get_format_info = intel_fb_get_format_info, 95 .output_poll_changed = intel_fbdev_output_poll_changed, 96 .mode_valid = intel_mode_valid, 97 .atomic_check = intel_atomic_check, 98 .atomic_commit = intel_atomic_commit, 99 .atomic_state_alloc = intel_atomic_state_alloc, 100 .atomic_state_clear = intel_atomic_state_clear, 101 .atomic_state_free = intel_atomic_state_free, 102 }; 103 104 static const struct drm_mode_config_helper_funcs intel_mode_config_funcs = { 105 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 106 }; 107 108 static void intel_mode_config_init(struct drm_i915_private *i915) 109 { 110 struct drm_mode_config *mode_config = &i915->drm.mode_config; 111 112 drm_mode_config_init(&i915->drm); 113 INIT_LIST_HEAD(&i915->display.global.obj_list); 114 115 mode_config->min_width = 0; 116 mode_config->min_height = 0; 117 118 mode_config->preferred_depth = 24; 119 mode_config->prefer_shadow = 1; 120 121 mode_config->funcs = &intel_mode_funcs; 122 mode_config->helper_private = &intel_mode_config_funcs; 123 124 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 125 126 /* 127 * Maximum framebuffer dimensions, chosen to match 128 * the maximum render engine surface size on gen4+. 129 */ 130 if (DISPLAY_VER(i915) >= 7) { 131 mode_config->max_width = 16384; 132 mode_config->max_height = 16384; 133 } else if (DISPLAY_VER(i915) >= 4) { 134 mode_config->max_width = 8192; 135 mode_config->max_height = 8192; 136 } else if (DISPLAY_VER(i915) == 3) { 137 mode_config->max_width = 4096; 138 mode_config->max_height = 4096; 139 } else { 140 mode_config->max_width = 2048; 141 mode_config->max_height = 2048; 142 } 143 144 if (IS_I845G(i915) || IS_I865G(i915)) { 145 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 146 mode_config->cursor_height = 1023; 147 } else if (IS_I830(i915) || IS_I85X(i915) || 148 IS_I915G(i915) || IS_I915GM(i915)) { 149 mode_config->cursor_width = 64; 150 mode_config->cursor_height = 64; 151 } else { 152 mode_config->cursor_width = 256; 153 mode_config->cursor_height = 256; 154 } 155 } 156 157 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 158 { 159 intel_atomic_global_obj_cleanup(i915); 160 drm_mode_config_cleanup(&i915->drm); 161 } 162 163 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 164 { 165 struct intel_plane *plane; 166 167 for_each_intel_plane(&dev_priv->drm, plane) { 168 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 169 plane->pipe); 170 171 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 172 } 173 } 174 175 void intel_display_driver_early_probe(struct drm_i915_private *i915) 176 { 177 if (!HAS_DISPLAY(i915)) 178 return; 179 180 intel_dkl_phy_init(i915); 181 intel_color_init_hooks(i915); 182 intel_init_cdclk_hooks(i915); 183 intel_audio_hooks_init(i915); 184 intel_dpll_init_clock_hook(i915); 185 intel_init_display_hooks(i915); 186 intel_fdi_init_hook(i915); 187 } 188 189 /* part #1: call before irq install */ 190 int intel_display_driver_probe_noirq(struct drm_i915_private *i915) 191 { 192 int ret; 193 194 if (i915_inject_probe_failure(i915)) 195 return -ENODEV; 196 197 if (HAS_DISPLAY(i915)) { 198 ret = drm_vblank_init(&i915->drm, 199 INTEL_NUM_PIPES(i915)); 200 if (ret) 201 return ret; 202 } 203 204 intel_bios_init(i915); 205 206 ret = intel_vga_register(i915); 207 if (ret) 208 goto cleanup_bios; 209 210 /* FIXME: completely on the wrong abstraction layer */ 211 ret = intel_power_domains_init(i915); 212 if (ret < 0) 213 goto cleanup_vga; 214 215 intel_pmdemand_init_early(i915); 216 217 intel_power_domains_init_hw(i915, false); 218 219 if (!HAS_DISPLAY(i915)) 220 return 0; 221 222 intel_dmc_init(i915); 223 224 i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0); 225 i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI | 226 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 227 228 intel_mode_config_init(i915); 229 230 ret = intel_cdclk_init(i915); 231 if (ret) 232 goto cleanup_vga_client_pw_domain_dmc; 233 234 ret = intel_color_init(i915); 235 if (ret) 236 goto cleanup_vga_client_pw_domain_dmc; 237 238 ret = intel_dbuf_init(i915); 239 if (ret) 240 goto cleanup_vga_client_pw_domain_dmc; 241 242 ret = intel_bw_init(i915); 243 if (ret) 244 goto cleanup_vga_client_pw_domain_dmc; 245 246 ret = intel_pmdemand_init(i915); 247 if (ret) 248 goto cleanup_vga_client_pw_domain_dmc; 249 250 init_llist_head(&i915->display.atomic_helper.free_list); 251 INIT_WORK(&i915->display.atomic_helper.free_work, 252 intel_atomic_helper_free_state_worker); 253 254 intel_init_quirks(i915); 255 256 intel_fbc_init(i915); 257 258 return 0; 259 260 cleanup_vga_client_pw_domain_dmc: 261 intel_dmc_fini(i915); 262 intel_power_domains_driver_remove(i915); 263 cleanup_vga: 264 intel_vga_unregister(i915); 265 cleanup_bios: 266 intel_bios_driver_remove(i915); 267 268 return ret; 269 } 270 271 /* part #2: call after irq install, but before gem init */ 272 int intel_display_driver_probe_nogem(struct drm_i915_private *i915) 273 { 274 struct drm_device *dev = &i915->drm; 275 enum pipe pipe; 276 struct intel_crtc *crtc; 277 int ret; 278 279 if (!HAS_DISPLAY(i915)) 280 return 0; 281 282 intel_wm_init(i915); 283 284 intel_panel_sanitize_ssc(i915); 285 286 intel_pps_setup(i915); 287 288 intel_gmbus_setup(i915); 289 290 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 291 INTEL_NUM_PIPES(i915), 292 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 293 294 for_each_pipe(i915, pipe) { 295 ret = intel_crtc_init(i915, pipe); 296 if (ret) { 297 intel_mode_config_cleanup(i915); 298 return ret; 299 } 300 } 301 302 intel_plane_possible_crtcs_init(i915); 303 intel_shared_dpll_init(i915); 304 intel_fdi_pll_freq_update(i915); 305 306 intel_update_czclk(i915); 307 intel_display_driver_init_hw(i915); 308 intel_dpll_update_ref_clks(i915); 309 310 intel_hdcp_component_init(i915); 311 312 if (i915->display.cdclk.max_cdclk_freq == 0) 313 intel_update_max_cdclk(i915); 314 315 intel_hti_init(i915); 316 317 /* Just disable it once at startup */ 318 intel_vga_disable(i915); 319 intel_setup_outputs(i915); 320 321 drm_modeset_lock_all(dev); 322 intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx); 323 intel_acpi_assign_connector_fwnodes(i915); 324 drm_modeset_unlock_all(dev); 325 326 for_each_intel_crtc(dev, crtc) { 327 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 328 continue; 329 intel_crtc_initial_plane_config(crtc); 330 } 331 332 /* 333 * Make sure hardware watermarks really match the state we read out. 334 * Note that we need to do this after reconstructing the BIOS fb's 335 * since the watermark calculation done here will use pstate->fb. 336 */ 337 if (!HAS_GMCH(i915)) 338 ilk_wm_sanitize(i915); 339 340 return 0; 341 } 342 343 /* part #3: call after gem init */ 344 int intel_display_driver_probe(struct drm_i915_private *i915) 345 { 346 int ret; 347 348 if (!HAS_DISPLAY(i915)) 349 return 0; 350 351 /* 352 * Force all active planes to recompute their states. So that on 353 * mode_setcrtc after probe, all the intel_plane_state variables 354 * are already calculated and there is no assert_plane warnings 355 * during bootup. 356 */ 357 ret = intel_initial_commit(&i915->drm); 358 if (ret) 359 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 360 361 intel_overlay_setup(i915); 362 363 ret = intel_fbdev_init(&i915->drm); 364 if (ret) 365 return ret; 366 367 /* Only enable hotplug handling once the fbdev is fully set up. */ 368 intel_hpd_init(i915); 369 intel_hpd_poll_disable(i915); 370 371 skl_watermark_ipc_init(i915); 372 373 return 0; 374 } 375 376 void intel_display_driver_register(struct drm_i915_private *i915) 377 { 378 if (!HAS_DISPLAY(i915)) 379 return; 380 381 /* Must be done after probing outputs */ 382 intel_opregion_register(i915); 383 intel_acpi_video_register(i915); 384 385 intel_audio_init(i915); 386 387 intel_display_debugfs_register(i915); 388 389 /* 390 * Some ports require correctly set-up hpd registers for 391 * detection to work properly (leading to ghost connected 392 * connector status), e.g. VGA on gm45. Hence we can only set 393 * up the initial fbdev config after hpd irqs are fully 394 * enabled. We do it last so that the async config cannot run 395 * before the connectors are registered. 396 */ 397 intel_fbdev_initial_config_async(i915); 398 399 /* 400 * We need to coordinate the hotplugs with the asynchronous 401 * fbdev configuration, for which we use the 402 * fbdev->async_cookie. 403 */ 404 drm_kms_helper_poll_init(&i915->drm); 405 } 406 407 /* part #1: call before irq uninstall */ 408 void intel_display_driver_remove(struct drm_i915_private *i915) 409 { 410 if (!HAS_DISPLAY(i915)) 411 return; 412 413 flush_workqueue(i915->display.wq.flip); 414 flush_workqueue(i915->display.wq.modeset); 415 416 flush_work(&i915->display.atomic_helper.free_work); 417 drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list)); 418 419 /* 420 * MST topology needs to be suspended so we don't have any calls to 421 * fbdev after it's finalized. MST will be destroyed later as part of 422 * drm_mode_config_cleanup() 423 */ 424 intel_dp_mst_suspend(i915); 425 } 426 427 /* part #2: call after irq uninstall */ 428 void intel_display_driver_remove_noirq(struct drm_i915_private *i915) 429 { 430 if (!HAS_DISPLAY(i915)) 431 return; 432 433 /* 434 * Due to the hpd irq storm handling the hotplug work can re-arm the 435 * poll handlers. Hence disable polling after hpd handling is shut down. 436 */ 437 intel_hpd_poll_fini(i915); 438 439 /* poll work can call into fbdev, hence clean that up afterwards */ 440 intel_fbdev_fini(i915); 441 442 intel_unregister_dsm_handler(); 443 444 /* flush any delayed tasks or pending work */ 445 flush_workqueue(i915->unordered_wq); 446 447 intel_hdcp_component_fini(i915); 448 449 intel_mode_config_cleanup(i915); 450 451 intel_overlay_cleanup(i915); 452 453 intel_gmbus_teardown(i915); 454 455 destroy_workqueue(i915->display.wq.flip); 456 destroy_workqueue(i915->display.wq.modeset); 457 458 intel_fbc_cleanup(i915); 459 } 460 461 /* part #3: call after gem init */ 462 void intel_display_driver_remove_nogem(struct drm_i915_private *i915) 463 { 464 intel_dmc_fini(i915); 465 466 intel_power_domains_driver_remove(i915); 467 468 intel_vga_unregister(i915); 469 470 intel_bios_driver_remove(i915); 471 } 472 473 void intel_display_driver_unregister(struct drm_i915_private *i915) 474 { 475 if (!HAS_DISPLAY(i915)) 476 return; 477 478 intel_fbdev_unregister(i915); 479 intel_audio_deinit(i915); 480 481 /* 482 * After flushing the fbdev (incl. a late async config which 483 * will have delayed queuing of a hotplug event), then flush 484 * the hotplug events. 485 */ 486 drm_kms_helper_poll_fini(&i915->drm); 487 drm_atomic_helper_shutdown(&i915->drm); 488 489 acpi_video_unregister(); 490 intel_opregion_unregister(i915); 491 } 492 493 /* 494 * turn all crtc's off, but do not adjust state 495 * This has to be paired with a call to intel_modeset_setup_hw_state. 496 */ 497 int intel_display_driver_suspend(struct drm_i915_private *i915) 498 { 499 struct drm_atomic_state *state; 500 int ret; 501 502 if (!HAS_DISPLAY(i915)) 503 return 0; 504 505 state = drm_atomic_helper_suspend(&i915->drm); 506 ret = PTR_ERR_OR_ZERO(state); 507 if (ret) 508 drm_err(&i915->drm, "Suspending crtc's failed with %i\n", 509 ret); 510 else 511 i915->display.restore.modeset_state = state; 512 return ret; 513 } 514 515 int 516 __intel_display_driver_resume(struct drm_i915_private *i915, 517 struct drm_atomic_state *state, 518 struct drm_modeset_acquire_ctx *ctx) 519 { 520 struct drm_crtc_state *crtc_state; 521 struct drm_crtc *crtc; 522 int ret, i; 523 524 intel_modeset_setup_hw_state(i915, ctx); 525 intel_vga_redisable(i915); 526 527 if (!state) 528 return 0; 529 530 /* 531 * We've duplicated the state, pointers to the old state are invalid. 532 * 533 * Don't attempt to use the old state until we commit the duplicated state. 534 */ 535 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 536 /* 537 * Force recalculation even if we restore 538 * current state. With fast modeset this may not result 539 * in a modeset when the state is compatible. 540 */ 541 crtc_state->mode_changed = true; 542 } 543 544 /* ignore any reset values/BIOS leftovers in the WM registers */ 545 if (!HAS_GMCH(i915)) 546 to_intel_atomic_state(state)->skip_intermediate_wm = true; 547 548 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 549 550 drm_WARN_ON(&i915->drm, ret == -EDEADLK); 551 552 return ret; 553 } 554 555 void intel_display_driver_resume(struct drm_i915_private *i915) 556 { 557 struct drm_atomic_state *state = i915->display.restore.modeset_state; 558 struct drm_modeset_acquire_ctx ctx; 559 int ret; 560 561 if (!HAS_DISPLAY(i915)) 562 return; 563 564 i915->display.restore.modeset_state = NULL; 565 if (state) 566 state->acquire_ctx = &ctx; 567 568 drm_modeset_acquire_init(&ctx, 0); 569 570 while (1) { 571 ret = drm_modeset_lock_all_ctx(&i915->drm, &ctx); 572 if (ret != -EDEADLK) 573 break; 574 575 drm_modeset_backoff(&ctx); 576 } 577 578 if (!ret) 579 ret = __intel_display_driver_resume(i915, state, &ctx); 580 581 skl_watermark_ipc_update(i915); 582 drm_modeset_drop_locks(&ctx); 583 drm_modeset_acquire_fini(&ctx); 584 585 if (ret) 586 drm_err(&i915->drm, 587 "Restoring old state failed with %i\n", ret); 588 if (state) 589 drm_atomic_state_put(state); 590 } 591