1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022-2023 Intel Corporation 4 * 5 * High level display driver entry points. This is a layer between top level 6 * driver code and low level display functionality; no low level display code or 7 * details here. 8 */ 9 10 #include <linux/vga_switcheroo.h> 11 #include <acpi/video.h> 12 #include <drm/display/drm_dp_mst_helper.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_mode_config.h> 15 #include <drm/drm_privacy_screen_consumer.h> 16 #include <drm/drm_probe_helper.h> 17 #include <drm/drm_vblank.h> 18 19 #include "i915_drv.h" 20 #include "i9xx_wm.h" 21 #include "intel_acpi.h" 22 #include "intel_atomic.h" 23 #include "intel_audio.h" 24 #include "intel_bios.h" 25 #include "intel_bw.h" 26 #include "intel_cdclk.h" 27 #include "intel_color.h" 28 #include "intel_crtc.h" 29 #include "intel_display_debugfs.h" 30 #include "intel_display_driver.h" 31 #include "intel_display_irq.h" 32 #include "intel_display_power.h" 33 #include "intel_display_types.h" 34 #include "intel_dkl_phy.h" 35 #include "intel_dmc.h" 36 #include "intel_dp.h" 37 #include "intel_dpll.h" 38 #include "intel_dpll_mgr.h" 39 #include "intel_fb.h" 40 #include "intel_fbc.h" 41 #include "intel_fbdev.h" 42 #include "intel_fdi.h" 43 #include "intel_gmbus.h" 44 #include "intel_hdcp.h" 45 #include "intel_hotplug.h" 46 #include "intel_hti.h" 47 #include "intel_modeset_setup.h" 48 #include "intel_opregion.h" 49 #include "intel_overlay.h" 50 #include "intel_plane_initial.h" 51 #include "intel_pmdemand.h" 52 #include "intel_pps.h" 53 #include "intel_quirks.h" 54 #include "intel_vga.h" 55 #include "intel_wm.h" 56 #include "skl_watermark.h" 57 58 bool intel_display_driver_probe_defer(struct pci_dev *pdev) 59 { 60 struct drm_privacy_screen *privacy_screen; 61 62 /* 63 * apple-gmux is needed on dual GPU MacBook Pro 64 * to probe the panel if we're the inactive GPU. 65 */ 66 if (vga_switcheroo_client_probe_defer(pdev)) 67 return true; 68 69 /* If the LCD panel has a privacy-screen, wait for it */ 70 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 71 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 72 return true; 73 74 drm_privacy_screen_put(privacy_screen); 75 76 return false; 77 } 78 79 void intel_display_driver_init_hw(struct drm_i915_private *i915) 80 { 81 struct intel_cdclk_state *cdclk_state; 82 83 if (!HAS_DISPLAY(i915)) 84 return; 85 86 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); 87 88 intel_update_cdclk(i915); 89 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); 90 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; 91 } 92 93 static const struct drm_mode_config_funcs intel_mode_funcs = { 94 .fb_create = intel_user_framebuffer_create, 95 .get_format_info = intel_fb_get_format_info, 96 .output_poll_changed = intel_fbdev_output_poll_changed, 97 .mode_valid = intel_mode_valid, 98 .atomic_check = intel_atomic_check, 99 .atomic_commit = intel_atomic_commit, 100 .atomic_state_alloc = intel_atomic_state_alloc, 101 .atomic_state_clear = intel_atomic_state_clear, 102 .atomic_state_free = intel_atomic_state_free, 103 }; 104 105 static const struct drm_mode_config_helper_funcs intel_mode_config_funcs = { 106 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 107 }; 108 109 static void intel_mode_config_init(struct drm_i915_private *i915) 110 { 111 struct drm_mode_config *mode_config = &i915->drm.mode_config; 112 113 drm_mode_config_init(&i915->drm); 114 INIT_LIST_HEAD(&i915->display.global.obj_list); 115 116 mode_config->min_width = 0; 117 mode_config->min_height = 0; 118 119 mode_config->preferred_depth = 24; 120 mode_config->prefer_shadow = 1; 121 122 mode_config->funcs = &intel_mode_funcs; 123 mode_config->helper_private = &intel_mode_config_funcs; 124 125 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 126 127 /* 128 * Maximum framebuffer dimensions, chosen to match 129 * the maximum render engine surface size on gen4+. 130 */ 131 if (DISPLAY_VER(i915) >= 7) { 132 mode_config->max_width = 16384; 133 mode_config->max_height = 16384; 134 } else if (DISPLAY_VER(i915) >= 4) { 135 mode_config->max_width = 8192; 136 mode_config->max_height = 8192; 137 } else if (DISPLAY_VER(i915) == 3) { 138 mode_config->max_width = 4096; 139 mode_config->max_height = 4096; 140 } else { 141 mode_config->max_width = 2048; 142 mode_config->max_height = 2048; 143 } 144 145 if (IS_I845G(i915) || IS_I865G(i915)) { 146 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 147 mode_config->cursor_height = 1023; 148 } else if (IS_I830(i915) || IS_I85X(i915) || 149 IS_I915G(i915) || IS_I915GM(i915)) { 150 mode_config->cursor_width = 64; 151 mode_config->cursor_height = 64; 152 } else { 153 mode_config->cursor_width = 256; 154 mode_config->cursor_height = 256; 155 } 156 } 157 158 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 159 { 160 intel_atomic_global_obj_cleanup(i915); 161 drm_mode_config_cleanup(&i915->drm); 162 } 163 164 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 165 { 166 struct intel_plane *plane; 167 168 for_each_intel_plane(&dev_priv->drm, plane) { 169 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 170 plane->pipe); 171 172 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 173 } 174 } 175 176 void intel_display_driver_early_probe(struct drm_i915_private *i915) 177 { 178 if (!HAS_DISPLAY(i915)) 179 return; 180 181 intel_display_irq_init(i915); 182 intel_dkl_phy_init(i915); 183 intel_color_init_hooks(i915); 184 intel_init_cdclk_hooks(i915); 185 intel_audio_hooks_init(i915); 186 intel_dpll_init_clock_hook(i915); 187 intel_init_display_hooks(i915); 188 intel_fdi_init_hook(i915); 189 } 190 191 /* part #1: call before irq install */ 192 int intel_display_driver_probe_noirq(struct drm_i915_private *i915) 193 { 194 int ret; 195 196 if (i915_inject_probe_failure(i915)) 197 return -ENODEV; 198 199 if (HAS_DISPLAY(i915)) { 200 ret = drm_vblank_init(&i915->drm, 201 INTEL_NUM_PIPES(i915)); 202 if (ret) 203 return ret; 204 } 205 206 intel_bios_init(i915); 207 208 ret = intel_vga_register(i915); 209 if (ret) 210 goto cleanup_bios; 211 212 /* FIXME: completely on the wrong abstraction layer */ 213 ret = intel_power_domains_init(i915); 214 if (ret < 0) 215 goto cleanup_vga; 216 217 intel_pmdemand_init_early(i915); 218 219 intel_power_domains_init_hw(i915, false); 220 221 if (!HAS_DISPLAY(i915)) 222 return 0; 223 224 intel_dmc_init(i915); 225 226 i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0); 227 i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI | 228 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 229 230 intel_mode_config_init(i915); 231 232 ret = intel_cdclk_init(i915); 233 if (ret) 234 goto cleanup_vga_client_pw_domain_dmc; 235 236 ret = intel_color_init(i915); 237 if (ret) 238 goto cleanup_vga_client_pw_domain_dmc; 239 240 ret = intel_dbuf_init(i915); 241 if (ret) 242 goto cleanup_vga_client_pw_domain_dmc; 243 244 ret = intel_bw_init(i915); 245 if (ret) 246 goto cleanup_vga_client_pw_domain_dmc; 247 248 ret = intel_pmdemand_init(i915); 249 if (ret) 250 goto cleanup_vga_client_pw_domain_dmc; 251 252 init_llist_head(&i915->display.atomic_helper.free_list); 253 INIT_WORK(&i915->display.atomic_helper.free_work, 254 intel_atomic_helper_free_state_worker); 255 256 intel_init_quirks(i915); 257 258 intel_fbc_init(i915); 259 260 return 0; 261 262 cleanup_vga_client_pw_domain_dmc: 263 intel_dmc_fini(i915); 264 intel_power_domains_driver_remove(i915); 265 cleanup_vga: 266 intel_vga_unregister(i915); 267 cleanup_bios: 268 intel_bios_driver_remove(i915); 269 270 return ret; 271 } 272 273 /* part #2: call after irq install, but before gem init */ 274 int intel_display_driver_probe_nogem(struct drm_i915_private *i915) 275 { 276 struct drm_device *dev = &i915->drm; 277 enum pipe pipe; 278 struct intel_crtc *crtc; 279 int ret; 280 281 if (!HAS_DISPLAY(i915)) 282 return 0; 283 284 intel_wm_init(i915); 285 286 intel_panel_sanitize_ssc(i915); 287 288 intel_pps_setup(i915); 289 290 intel_gmbus_setup(i915); 291 292 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 293 INTEL_NUM_PIPES(i915), 294 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 295 296 for_each_pipe(i915, pipe) { 297 ret = intel_crtc_init(i915, pipe); 298 if (ret) { 299 intel_mode_config_cleanup(i915); 300 return ret; 301 } 302 } 303 304 intel_plane_possible_crtcs_init(i915); 305 intel_shared_dpll_init(i915); 306 intel_fdi_pll_freq_update(i915); 307 308 intel_update_czclk(i915); 309 intel_display_driver_init_hw(i915); 310 intel_dpll_update_ref_clks(i915); 311 312 intel_hdcp_component_init(i915); 313 314 if (i915->display.cdclk.max_cdclk_freq == 0) 315 intel_update_max_cdclk(i915); 316 317 intel_hti_init(i915); 318 319 /* Just disable it once at startup */ 320 intel_vga_disable(i915); 321 intel_setup_outputs(i915); 322 323 drm_modeset_lock_all(dev); 324 intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx); 325 intel_acpi_assign_connector_fwnodes(i915); 326 drm_modeset_unlock_all(dev); 327 328 for_each_intel_crtc(dev, crtc) { 329 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 330 continue; 331 intel_crtc_initial_plane_config(crtc); 332 } 333 334 /* 335 * Make sure hardware watermarks really match the state we read out. 336 * Note that we need to do this after reconstructing the BIOS fb's 337 * since the watermark calculation done here will use pstate->fb. 338 */ 339 if (!HAS_GMCH(i915)) 340 ilk_wm_sanitize(i915); 341 342 return 0; 343 } 344 345 /* part #3: call after gem init */ 346 int intel_display_driver_probe(struct drm_i915_private *i915) 347 { 348 int ret; 349 350 if (!HAS_DISPLAY(i915)) 351 return 0; 352 353 /* 354 * Force all active planes to recompute their states. So that on 355 * mode_setcrtc after probe, all the intel_plane_state variables 356 * are already calculated and there is no assert_plane warnings 357 * during bootup. 358 */ 359 ret = intel_initial_commit(&i915->drm); 360 if (ret) 361 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 362 363 intel_overlay_setup(i915); 364 365 ret = intel_fbdev_init(&i915->drm); 366 if (ret) 367 return ret; 368 369 /* Only enable hotplug handling once the fbdev is fully set up. */ 370 intel_hpd_init(i915); 371 intel_hpd_poll_disable(i915); 372 373 skl_watermark_ipc_init(i915); 374 375 return 0; 376 } 377 378 void intel_display_driver_register(struct drm_i915_private *i915) 379 { 380 if (!HAS_DISPLAY(i915)) 381 return; 382 383 /* Must be done after probing outputs */ 384 intel_opregion_register(i915); 385 intel_acpi_video_register(i915); 386 387 intel_audio_init(i915); 388 389 intel_audio_register(i915); 390 391 intel_display_debugfs_register(i915); 392 393 /* 394 * Some ports require correctly set-up hpd registers for 395 * detection to work properly (leading to ghost connected 396 * connector status), e.g. VGA on gm45. Hence we can only set 397 * up the initial fbdev config after hpd irqs are fully 398 * enabled. We do it last so that the async config cannot run 399 * before the connectors are registered. 400 */ 401 intel_fbdev_initial_config_async(i915); 402 403 /* 404 * We need to coordinate the hotplugs with the asynchronous 405 * fbdev configuration, for which we use the 406 * fbdev->async_cookie. 407 */ 408 drm_kms_helper_poll_init(&i915->drm); 409 } 410 411 /* part #1: call before irq uninstall */ 412 void intel_display_driver_remove(struct drm_i915_private *i915) 413 { 414 if (!HAS_DISPLAY(i915)) 415 return; 416 417 flush_workqueue(i915->display.wq.flip); 418 flush_workqueue(i915->display.wq.modeset); 419 420 flush_work(&i915->display.atomic_helper.free_work); 421 drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list)); 422 423 /* 424 * MST topology needs to be suspended so we don't have any calls to 425 * fbdev after it's finalized. MST will be destroyed later as part of 426 * drm_mode_config_cleanup() 427 */ 428 intel_dp_mst_suspend(i915); 429 } 430 431 /* part #2: call after irq uninstall */ 432 void intel_display_driver_remove_noirq(struct drm_i915_private *i915) 433 { 434 if (!HAS_DISPLAY(i915)) 435 return; 436 437 /* 438 * Due to the hpd irq storm handling the hotplug work can re-arm the 439 * poll handlers. Hence disable polling after hpd handling is shut down. 440 */ 441 intel_hpd_poll_fini(i915); 442 443 /* poll work can call into fbdev, hence clean that up afterwards */ 444 intel_fbdev_fini(i915); 445 446 intel_unregister_dsm_handler(); 447 448 /* flush any delayed tasks or pending work */ 449 flush_workqueue(i915->unordered_wq); 450 451 intel_hdcp_component_fini(i915); 452 453 intel_mode_config_cleanup(i915); 454 455 intel_overlay_cleanup(i915); 456 457 intel_gmbus_teardown(i915); 458 459 destroy_workqueue(i915->display.wq.flip); 460 destroy_workqueue(i915->display.wq.modeset); 461 462 intel_fbc_cleanup(i915); 463 } 464 465 /* part #3: call after gem init */ 466 void intel_display_driver_remove_nogem(struct drm_i915_private *i915) 467 { 468 intel_dmc_fini(i915); 469 470 intel_power_domains_driver_remove(i915); 471 472 intel_vga_unregister(i915); 473 474 intel_bios_driver_remove(i915); 475 } 476 477 void intel_display_driver_unregister(struct drm_i915_private *i915) 478 { 479 if (!HAS_DISPLAY(i915)) 480 return; 481 482 intel_fbdev_unregister(i915); 483 intel_audio_deinit(i915); 484 485 /* 486 * After flushing the fbdev (incl. a late async config which 487 * will have delayed queuing of a hotplug event), then flush 488 * the hotplug events. 489 */ 490 drm_kms_helper_poll_fini(&i915->drm); 491 drm_atomic_helper_shutdown(&i915->drm); 492 493 acpi_video_unregister(); 494 intel_opregion_unregister(i915); 495 } 496 497 /* 498 * turn all crtc's off, but do not adjust state 499 * This has to be paired with a call to intel_modeset_setup_hw_state. 500 */ 501 int intel_display_driver_suspend(struct drm_i915_private *i915) 502 { 503 struct drm_atomic_state *state; 504 int ret; 505 506 if (!HAS_DISPLAY(i915)) 507 return 0; 508 509 state = drm_atomic_helper_suspend(&i915->drm); 510 ret = PTR_ERR_OR_ZERO(state); 511 if (ret) 512 drm_err(&i915->drm, "Suspending crtc's failed with %i\n", 513 ret); 514 else 515 i915->display.restore.modeset_state = state; 516 return ret; 517 } 518 519 int 520 __intel_display_driver_resume(struct drm_i915_private *i915, 521 struct drm_atomic_state *state, 522 struct drm_modeset_acquire_ctx *ctx) 523 { 524 struct drm_crtc_state *crtc_state; 525 struct drm_crtc *crtc; 526 int ret, i; 527 528 intel_modeset_setup_hw_state(i915, ctx); 529 intel_vga_redisable(i915); 530 531 if (!state) 532 return 0; 533 534 /* 535 * We've duplicated the state, pointers to the old state are invalid. 536 * 537 * Don't attempt to use the old state until we commit the duplicated state. 538 */ 539 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 540 /* 541 * Force recalculation even if we restore 542 * current state. With fast modeset this may not result 543 * in a modeset when the state is compatible. 544 */ 545 crtc_state->mode_changed = true; 546 } 547 548 /* ignore any reset values/BIOS leftovers in the WM registers */ 549 if (!HAS_GMCH(i915)) 550 to_intel_atomic_state(state)->skip_intermediate_wm = true; 551 552 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 553 554 drm_WARN_ON(&i915->drm, ret == -EDEADLK); 555 556 return ret; 557 } 558 559 void intel_display_driver_resume(struct drm_i915_private *i915) 560 { 561 struct drm_atomic_state *state = i915->display.restore.modeset_state; 562 struct drm_modeset_acquire_ctx ctx; 563 int ret; 564 565 if (!HAS_DISPLAY(i915)) 566 return; 567 568 i915->display.restore.modeset_state = NULL; 569 if (state) 570 state->acquire_ctx = &ctx; 571 572 drm_modeset_acquire_init(&ctx, 0); 573 574 while (1) { 575 ret = drm_modeset_lock_all_ctx(&i915->drm, &ctx); 576 if (ret != -EDEADLK) 577 break; 578 579 drm_modeset_backoff(&ctx); 580 } 581 582 if (!ret) 583 ret = __intel_display_driver_resume(i915, state, &ctx); 584 585 skl_watermark_ipc_update(i915); 586 drm_modeset_drop_locks(&ctx); 587 drm_modeset_acquire_fini(&ctx); 588 589 if (ret) 590 drm_err(&i915->drm, 591 "Restoring old state failed with %i\n", ret); 592 if (state) 593 drm_atomic_state_put(state); 594 } 595