1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <drm/i915_pciids.h> 7 #include <drm/drm_color_mgmt.h> 8 #include <linux/pci.h> 9 10 #include "i915_drv.h" 11 #include "i915_reg.h" 12 #include "intel_de.h" 13 #include "intel_display.h" 14 #include "intel_display_device.h" 15 #include "intel_display_power.h" 16 #include "intel_display_reg_defs.h" 17 #include "intel_fbc.h" 18 19 __diag_push(); 20 __diag_ignore_all("-Woverride-init", "Allow overriding inherited members"); 21 22 static const struct intel_display_device_info no_display = {}; 23 24 #define PIPE_A_OFFSET 0x70000 25 #define PIPE_B_OFFSET 0x71000 26 #define PIPE_C_OFFSET 0x72000 27 #define PIPE_D_OFFSET 0x73000 28 #define CHV_PIPE_C_OFFSET 0x74000 29 /* 30 * There's actually no pipe EDP. Some pipe registers have 31 * simply shifted from the pipe to the transcoder, while 32 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 33 * to access such registers in transcoder EDP. 34 */ 35 #define PIPE_EDP_OFFSET 0x7f000 36 37 /* ICL DSI 0 and 1 */ 38 #define PIPE_DSI0_OFFSET 0x7b000 39 #define PIPE_DSI1_OFFSET 0x7b800 40 41 #define TRANSCODER_A_OFFSET 0x60000 42 #define TRANSCODER_B_OFFSET 0x61000 43 #define TRANSCODER_C_OFFSET 0x62000 44 #define CHV_TRANSCODER_C_OFFSET 0x63000 45 #define TRANSCODER_D_OFFSET 0x63000 46 #define TRANSCODER_EDP_OFFSET 0x6f000 47 #define TRANSCODER_DSI0_OFFSET 0x6b000 48 #define TRANSCODER_DSI1_OFFSET 0x6b800 49 50 #define CURSOR_A_OFFSET 0x70080 51 #define CURSOR_B_OFFSET 0x700c0 52 #define CHV_CURSOR_C_OFFSET 0x700e0 53 #define IVB_CURSOR_B_OFFSET 0x71080 54 #define IVB_CURSOR_C_OFFSET 0x72080 55 #define TGL_CURSOR_D_OFFSET 0x73080 56 57 #define I845_PIPE_OFFSETS \ 58 .pipe_offsets = { \ 59 [TRANSCODER_A] = PIPE_A_OFFSET, \ 60 }, \ 61 .trans_offsets = { \ 62 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 63 } 64 65 #define I9XX_PIPE_OFFSETS \ 66 .pipe_offsets = { \ 67 [TRANSCODER_A] = PIPE_A_OFFSET, \ 68 [TRANSCODER_B] = PIPE_B_OFFSET, \ 69 }, \ 70 .trans_offsets = { \ 71 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 72 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 73 } 74 75 #define IVB_PIPE_OFFSETS \ 76 .pipe_offsets = { \ 77 [TRANSCODER_A] = PIPE_A_OFFSET, \ 78 [TRANSCODER_B] = PIPE_B_OFFSET, \ 79 [TRANSCODER_C] = PIPE_C_OFFSET, \ 80 }, \ 81 .trans_offsets = { \ 82 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 83 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 84 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 85 } 86 87 #define HSW_PIPE_OFFSETS \ 88 .pipe_offsets = { \ 89 [TRANSCODER_A] = PIPE_A_OFFSET, \ 90 [TRANSCODER_B] = PIPE_B_OFFSET, \ 91 [TRANSCODER_C] = PIPE_C_OFFSET, \ 92 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 93 }, \ 94 .trans_offsets = { \ 95 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 96 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 97 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 98 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 99 } 100 101 #define CHV_PIPE_OFFSETS \ 102 .pipe_offsets = { \ 103 [TRANSCODER_A] = PIPE_A_OFFSET, \ 104 [TRANSCODER_B] = PIPE_B_OFFSET, \ 105 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 106 }, \ 107 .trans_offsets = { \ 108 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 109 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 110 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 111 } 112 113 #define I845_CURSOR_OFFSETS \ 114 .cursor_offsets = { \ 115 [PIPE_A] = CURSOR_A_OFFSET, \ 116 } 117 118 #define I9XX_CURSOR_OFFSETS \ 119 .cursor_offsets = { \ 120 [PIPE_A] = CURSOR_A_OFFSET, \ 121 [PIPE_B] = CURSOR_B_OFFSET, \ 122 } 123 124 #define CHV_CURSOR_OFFSETS \ 125 .cursor_offsets = { \ 126 [PIPE_A] = CURSOR_A_OFFSET, \ 127 [PIPE_B] = CURSOR_B_OFFSET, \ 128 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 129 } 130 131 #define IVB_CURSOR_OFFSETS \ 132 .cursor_offsets = { \ 133 [PIPE_A] = CURSOR_A_OFFSET, \ 134 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 135 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 136 } 137 138 #define TGL_CURSOR_OFFSETS \ 139 .cursor_offsets = { \ 140 [PIPE_A] = CURSOR_A_OFFSET, \ 141 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 142 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 143 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 144 } 145 146 #define I845_COLORS \ 147 .color = { .gamma_lut_size = 256 } 148 #define I9XX_COLORS \ 149 .color = { .gamma_lut_size = 129, \ 150 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 151 } 152 #define ILK_COLORS \ 153 .color = { .gamma_lut_size = 1024 } 154 #define IVB_COLORS \ 155 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 156 #define CHV_COLORS \ 157 .color = { \ 158 .degamma_lut_size = 65, .gamma_lut_size = 257, \ 159 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 160 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 161 } 162 #define GLK_COLORS \ 163 .color = { \ 164 .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 165 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 166 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 167 } 168 #define ICL_COLORS \ 169 .color = { \ 170 .degamma_lut_size = 33, .gamma_lut_size = 262145, \ 171 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 172 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 173 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 174 } 175 176 #define I830_DISPLAY \ 177 .has_overlay = 1, \ 178 .cursor_needs_physical = 1, \ 179 .overlay_needs_physical = 1, \ 180 .has_gmch = 1, \ 181 I9XX_PIPE_OFFSETS, \ 182 I9XX_CURSOR_OFFSETS, \ 183 I9XX_COLORS, \ 184 \ 185 .__runtime_defaults.ip.ver = 2, \ 186 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 187 .__runtime_defaults.cpu_transcoder_mask = \ 188 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 189 190 static const struct intel_display_device_info i830_display = { 191 I830_DISPLAY, 192 }; 193 194 #define I845_DISPLAY \ 195 .has_overlay = 1, \ 196 .overlay_needs_physical = 1, \ 197 .has_gmch = 1, \ 198 I845_PIPE_OFFSETS, \ 199 I845_CURSOR_OFFSETS, \ 200 I845_COLORS, \ 201 \ 202 .__runtime_defaults.ip.ver = 2, \ 203 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \ 204 .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) 205 206 static const struct intel_display_device_info i845_display = { 207 I845_DISPLAY, 208 }; 209 210 static const struct intel_display_device_info i85x_display = { 211 I830_DISPLAY, 212 213 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 214 }; 215 216 static const struct intel_display_device_info i865g_display = { 217 I845_DISPLAY, 218 219 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 220 }; 221 222 #define GEN3_DISPLAY \ 223 .has_gmch = 1, \ 224 .has_overlay = 1, \ 225 I9XX_PIPE_OFFSETS, \ 226 I9XX_CURSOR_OFFSETS, \ 227 \ 228 .__runtime_defaults.ip.ver = 3, \ 229 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 230 .__runtime_defaults.cpu_transcoder_mask = \ 231 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 232 233 static const struct intel_display_device_info i915g_display = { 234 GEN3_DISPLAY, 235 I845_COLORS, 236 .cursor_needs_physical = 1, 237 .overlay_needs_physical = 1, 238 }; 239 240 static const struct intel_display_device_info i915gm_display = { 241 GEN3_DISPLAY, 242 I9XX_COLORS, 243 .cursor_needs_physical = 1, 244 .overlay_needs_physical = 1, 245 .supports_tv = 1, 246 247 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 248 }; 249 250 static const struct intel_display_device_info i945g_display = { 251 GEN3_DISPLAY, 252 I845_COLORS, 253 .has_hotplug = 1, 254 .cursor_needs_physical = 1, 255 .overlay_needs_physical = 1, 256 }; 257 258 static const struct intel_display_device_info i945gm_display = { 259 GEN3_DISPLAY, 260 I9XX_COLORS, 261 .has_hotplug = 1, 262 .cursor_needs_physical = 1, 263 .overlay_needs_physical = 1, 264 .supports_tv = 1, 265 266 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 267 }; 268 269 static const struct intel_display_device_info g33_display = { 270 GEN3_DISPLAY, 271 I845_COLORS, 272 .has_hotplug = 1, 273 }; 274 275 static const struct intel_display_device_info pnv_display = { 276 GEN3_DISPLAY, 277 I9XX_COLORS, 278 .has_hotplug = 1, 279 }; 280 281 #define GEN4_DISPLAY \ 282 .has_hotplug = 1, \ 283 .has_gmch = 1, \ 284 I9XX_PIPE_OFFSETS, \ 285 I9XX_CURSOR_OFFSETS, \ 286 I9XX_COLORS, \ 287 \ 288 .__runtime_defaults.ip.ver = 4, \ 289 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 290 .__runtime_defaults.cpu_transcoder_mask = \ 291 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 292 293 static const struct intel_display_device_info i965g_display = { 294 GEN4_DISPLAY, 295 .has_overlay = 1, 296 }; 297 298 static const struct intel_display_device_info i965gm_display = { 299 GEN4_DISPLAY, 300 .has_overlay = 1, 301 .supports_tv = 1, 302 303 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 304 }; 305 306 static const struct intel_display_device_info g45_display = { 307 GEN4_DISPLAY, 308 }; 309 310 static const struct intel_display_device_info gm45_display = { 311 GEN4_DISPLAY, 312 .supports_tv = 1, 313 314 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 315 }; 316 317 #define ILK_DISPLAY \ 318 .has_hotplug = 1, \ 319 I9XX_PIPE_OFFSETS, \ 320 I9XX_CURSOR_OFFSETS, \ 321 ILK_COLORS, \ 322 \ 323 .__runtime_defaults.ip.ver = 5, \ 324 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 325 .__runtime_defaults.cpu_transcoder_mask = \ 326 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 327 328 static const struct intel_display_device_info ilk_d_display = { 329 ILK_DISPLAY, 330 }; 331 332 static const struct intel_display_device_info ilk_m_display = { 333 ILK_DISPLAY, 334 335 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 336 }; 337 338 static const struct intel_display_device_info snb_display = { 339 .has_hotplug = 1, 340 I9XX_PIPE_OFFSETS, 341 I9XX_CURSOR_OFFSETS, 342 ILK_COLORS, 343 344 .__runtime_defaults.ip.ver = 6, 345 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 346 .__runtime_defaults.cpu_transcoder_mask = 347 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 348 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 349 }; 350 351 static const struct intel_display_device_info ivb_display = { 352 .has_hotplug = 1, 353 IVB_PIPE_OFFSETS, 354 IVB_CURSOR_OFFSETS, 355 IVB_COLORS, 356 357 .__runtime_defaults.ip.ver = 7, 358 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 359 .__runtime_defaults.cpu_transcoder_mask = 360 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 361 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 362 }; 363 364 static const struct intel_display_device_info vlv_display = { 365 .has_gmch = 1, 366 .has_hotplug = 1, 367 .mmio_offset = VLV_DISPLAY_BASE, 368 I9XX_PIPE_OFFSETS, 369 I9XX_CURSOR_OFFSETS, 370 I9XX_COLORS, 371 372 .__runtime_defaults.ip.ver = 7, 373 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 374 .__runtime_defaults.cpu_transcoder_mask = 375 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 376 }; 377 378 static const struct intel_display_device_info hsw_display = { 379 .has_ddi = 1, 380 .has_dp_mst = 1, 381 .has_fpga_dbg = 1, 382 .has_hotplug = 1, 383 HSW_PIPE_OFFSETS, 384 IVB_CURSOR_OFFSETS, 385 IVB_COLORS, 386 387 .__runtime_defaults.ip.ver = 7, 388 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 389 .__runtime_defaults.cpu_transcoder_mask = 390 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 391 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 392 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 393 }; 394 395 static const struct intel_display_device_info bdw_display = { 396 .has_ddi = 1, 397 .has_dp_mst = 1, 398 .has_fpga_dbg = 1, 399 .has_hotplug = 1, 400 HSW_PIPE_OFFSETS, 401 IVB_CURSOR_OFFSETS, 402 IVB_COLORS, 403 404 .__runtime_defaults.ip.ver = 8, 405 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 406 .__runtime_defaults.cpu_transcoder_mask = 407 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 408 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 409 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 410 }; 411 412 static const struct intel_display_device_info chv_display = { 413 .has_hotplug = 1, 414 .has_gmch = 1, 415 .mmio_offset = VLV_DISPLAY_BASE, 416 CHV_PIPE_OFFSETS, 417 CHV_CURSOR_OFFSETS, 418 CHV_COLORS, 419 420 .__runtime_defaults.ip.ver = 8, 421 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 422 .__runtime_defaults.cpu_transcoder_mask = 423 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 424 }; 425 426 static const struct intel_display_device_info skl_display = { 427 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ 428 .dbuf.slice_mask = BIT(DBUF_S1), 429 .has_ddi = 1, 430 .has_dp_mst = 1, 431 .has_fpga_dbg = 1, 432 .has_hotplug = 1, 433 .has_ipc = 1, 434 .has_psr = 1, 435 .has_psr_hw_tracking = 1, 436 HSW_PIPE_OFFSETS, 437 IVB_CURSOR_OFFSETS, 438 IVB_COLORS, 439 440 .__runtime_defaults.ip.ver = 9, 441 .__runtime_defaults.has_dmc = 1, 442 .__runtime_defaults.has_hdcp = 1, 443 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 444 .__runtime_defaults.cpu_transcoder_mask = 445 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 446 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 447 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 448 }; 449 450 #define GEN9_LP_DISPLAY \ 451 .dbuf.slice_mask = BIT(DBUF_S1), \ 452 .has_dp_mst = 1, \ 453 .has_ddi = 1, \ 454 .has_fpga_dbg = 1, \ 455 .has_hotplug = 1, \ 456 .has_ipc = 1, \ 457 .has_psr = 1, \ 458 .has_psr_hw_tracking = 1, \ 459 HSW_PIPE_OFFSETS, \ 460 IVB_CURSOR_OFFSETS, \ 461 IVB_COLORS, \ 462 \ 463 .__runtime_defaults.has_dmc = 1, \ 464 .__runtime_defaults.has_hdcp = 1, \ 465 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \ 466 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 467 .__runtime_defaults.cpu_transcoder_mask = \ 468 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 469 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 470 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C) 471 472 static const struct intel_display_device_info bxt_display = { 473 GEN9_LP_DISPLAY, 474 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ 475 476 .__runtime_defaults.ip.ver = 9, 477 }; 478 479 static const struct intel_display_device_info glk_display = { 480 GEN9_LP_DISPLAY, 481 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ 482 GLK_COLORS, 483 484 .__runtime_defaults.ip.ver = 10, 485 }; 486 487 static const struct intel_display_device_info gen11_display = { 488 .abox_mask = BIT(0), 489 .dbuf.size = 2048, 490 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), 491 .has_ddi = 1, 492 .has_dp_mst = 1, 493 .has_fpga_dbg = 1, 494 .has_hotplug = 1, 495 .has_ipc = 1, 496 .has_psr = 1, 497 .has_psr_hw_tracking = 1, 498 .pipe_offsets = { 499 [TRANSCODER_A] = PIPE_A_OFFSET, 500 [TRANSCODER_B] = PIPE_B_OFFSET, 501 [TRANSCODER_C] = PIPE_C_OFFSET, 502 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, 503 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, 504 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, 505 }, 506 .trans_offsets = { 507 [TRANSCODER_A] = TRANSCODER_A_OFFSET, 508 [TRANSCODER_B] = TRANSCODER_B_OFFSET, 509 [TRANSCODER_C] = TRANSCODER_C_OFFSET, 510 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, 511 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, 512 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, 513 }, 514 IVB_CURSOR_OFFSETS, 515 ICL_COLORS, 516 517 .__runtime_defaults.ip.ver = 11, 518 .__runtime_defaults.has_dmc = 1, 519 .__runtime_defaults.has_dsc = 1, 520 .__runtime_defaults.has_hdcp = 1, 521 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 522 .__runtime_defaults.cpu_transcoder_mask = 523 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 524 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | 525 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 526 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 527 }; 528 529 #define XE_D_DISPLAY \ 530 .abox_mask = GENMASK(2, 1), \ 531 .dbuf.size = 2048, \ 532 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 533 .has_ddi = 1, \ 534 .has_dp_mst = 1, \ 535 .has_dsb = 1, \ 536 .has_fpga_dbg = 1, \ 537 .has_hotplug = 1, \ 538 .has_ipc = 1, \ 539 .has_psr = 1, \ 540 .has_psr_hw_tracking = 1, \ 541 .pipe_offsets = { \ 542 [TRANSCODER_A] = PIPE_A_OFFSET, \ 543 [TRANSCODER_B] = PIPE_B_OFFSET, \ 544 [TRANSCODER_C] = PIPE_C_OFFSET, \ 545 [TRANSCODER_D] = PIPE_D_OFFSET, \ 546 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 547 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 548 }, \ 549 .trans_offsets = { \ 550 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 551 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 552 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 553 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 554 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 555 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 556 }, \ 557 TGL_CURSOR_OFFSETS, \ 558 ICL_COLORS, \ 559 \ 560 .__runtime_defaults.ip.ver = 12, \ 561 .__runtime_defaults.has_dmc = 1, \ 562 .__runtime_defaults.has_dsc = 1, \ 563 .__runtime_defaults.has_hdcp = 1, \ 564 .__runtime_defaults.pipe_mask = \ 565 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 566 .__runtime_defaults.cpu_transcoder_mask = \ 567 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 568 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 569 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 570 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) 571 572 static const struct intel_display_device_info tgl_display = { 573 XE_D_DISPLAY, 574 }; 575 576 static const struct intel_display_device_info rkl_display = { 577 XE_D_DISPLAY, 578 .abox_mask = BIT(0), 579 .has_hti = 1, 580 .has_psr_hw_tracking = 0, 581 582 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 583 .__runtime_defaults.cpu_transcoder_mask = 584 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 585 }; 586 587 static const struct intel_display_device_info adl_s_display = { 588 XE_D_DISPLAY, 589 .has_hti = 1, 590 .has_psr_hw_tracking = 0, 591 }; 592 593 #define XE_LPD_FEATURES \ 594 .abox_mask = GENMASK(1, 0), \ 595 .color = { \ 596 .degamma_lut_size = 129, .gamma_lut_size = 1024, \ 597 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 598 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 599 }, \ 600 .dbuf.size = 4096, \ 601 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 602 BIT(DBUF_S4), \ 603 .has_ddi = 1, \ 604 .has_dp_mst = 1, \ 605 .has_dsb = 1, \ 606 .has_fpga_dbg = 1, \ 607 .has_hotplug = 1, \ 608 .has_ipc = 1, \ 609 .has_psr = 1, \ 610 .pipe_offsets = { \ 611 [TRANSCODER_A] = PIPE_A_OFFSET, \ 612 [TRANSCODER_B] = PIPE_B_OFFSET, \ 613 [TRANSCODER_C] = PIPE_C_OFFSET, \ 614 [TRANSCODER_D] = PIPE_D_OFFSET, \ 615 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 616 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 617 }, \ 618 .trans_offsets = { \ 619 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 620 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 621 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 622 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 623 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 624 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 625 }, \ 626 TGL_CURSOR_OFFSETS, \ 627 \ 628 .__runtime_defaults.ip.ver = 13, \ 629 .__runtime_defaults.has_dmc = 1, \ 630 .__runtime_defaults.has_dsc = 1, \ 631 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \ 632 .__runtime_defaults.has_hdcp = 1, \ 633 .__runtime_defaults.pipe_mask = \ 634 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D) 635 636 static const struct intel_display_device_info xe_lpd_display = { 637 XE_LPD_FEATURES, 638 .has_cdclk_crawl = 1, 639 .has_psr_hw_tracking = 0, 640 641 .__runtime_defaults.cpu_transcoder_mask = 642 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 643 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 644 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 645 }; 646 647 static const struct intel_display_device_info xe_hpd_display = { 648 XE_LPD_FEATURES, 649 .has_cdclk_squash = 1, 650 651 .__runtime_defaults.cpu_transcoder_mask = 652 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 653 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 654 }; 655 656 static const struct intel_display_device_info xe_lpdp_display = { 657 XE_LPD_FEATURES, 658 .has_cdclk_crawl = 1, 659 .has_cdclk_squash = 1, 660 661 .__runtime_defaults.ip.ver = 14, 662 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), 663 .__runtime_defaults.cpu_transcoder_mask = 664 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 665 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 666 }; 667 668 __diag_pop(); 669 670 #undef INTEL_VGA_DEVICE 671 #undef INTEL_QUANTA_VGA_DEVICE 672 #define INTEL_VGA_DEVICE(id, info) { id, info } 673 #define INTEL_QUANTA_VGA_DEVICE(info) { 0x16a, info } 674 675 static const struct { 676 u32 devid; 677 const struct intel_display_device_info *info; 678 } intel_display_ids[] = { 679 INTEL_I830_IDS(&i830_display), 680 INTEL_I845G_IDS(&i845_display), 681 INTEL_I85X_IDS(&i85x_display), 682 INTEL_I865G_IDS(&i865g_display), 683 INTEL_I915G_IDS(&i915g_display), 684 INTEL_I915GM_IDS(&i915gm_display), 685 INTEL_I945G_IDS(&i945g_display), 686 INTEL_I945GM_IDS(&i945gm_display), 687 INTEL_I965G_IDS(&i965g_display), 688 INTEL_G33_IDS(&g33_display), 689 INTEL_I965GM_IDS(&i965gm_display), 690 INTEL_GM45_IDS(&gm45_display), 691 INTEL_G45_IDS(&g45_display), 692 INTEL_PINEVIEW_G_IDS(&pnv_display), 693 INTEL_PINEVIEW_M_IDS(&pnv_display), 694 INTEL_IRONLAKE_D_IDS(&ilk_d_display), 695 INTEL_IRONLAKE_M_IDS(&ilk_m_display), 696 INTEL_SNB_D_IDS(&snb_display), 697 INTEL_SNB_M_IDS(&snb_display), 698 INTEL_IVB_Q_IDS(NULL), /* must be first IVB in list */ 699 INTEL_IVB_M_IDS(&ivb_display), 700 INTEL_IVB_D_IDS(&ivb_display), 701 INTEL_HSW_IDS(&hsw_display), 702 INTEL_VLV_IDS(&vlv_display), 703 INTEL_BDW_IDS(&bdw_display), 704 INTEL_CHV_IDS(&chv_display), 705 INTEL_SKL_IDS(&skl_display), 706 INTEL_BXT_IDS(&bxt_display), 707 INTEL_GLK_IDS(&glk_display), 708 INTEL_KBL_IDS(&skl_display), 709 INTEL_CFL_IDS(&skl_display), 710 INTEL_ICL_11_IDS(&gen11_display), 711 INTEL_EHL_IDS(&gen11_display), 712 INTEL_JSL_IDS(&gen11_display), 713 INTEL_TGL_12_IDS(&tgl_display), 714 INTEL_DG1_IDS(&tgl_display), 715 INTEL_RKL_IDS(&rkl_display), 716 INTEL_ADLS_IDS(&adl_s_display), 717 INTEL_RPLS_IDS(&adl_s_display), 718 INTEL_ADLP_IDS(&xe_lpd_display), 719 INTEL_ADLN_IDS(&xe_lpd_display), 720 INTEL_RPLP_IDS(&xe_lpd_display), 721 INTEL_DG2_IDS(&xe_hpd_display), 722 723 /* 724 * Do not add any GMD_ID-based platforms to this list. They will 725 * be probed automatically based on the IP version reported by 726 * the hardware. 727 */ 728 }; 729 730 static const struct { 731 u16 ver; 732 u16 rel; 733 const struct intel_display_device_info *display; 734 } gmdid_display_map[] = { 735 { 14, 0, &xe_lpdp_display }, 736 }; 737 738 static const struct intel_display_device_info * 739 probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step) 740 { 741 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 742 void __iomem *addr; 743 u32 val; 744 int i; 745 746 addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); 747 if (!addr) { 748 drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n"); 749 return &no_display; 750 } 751 752 val = ioread32(addr); 753 pci_iounmap(pdev, addr); 754 755 if (val == 0) 756 /* Platform doesn't have display */ 757 return &no_display; 758 759 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); 760 *rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 761 *step = REG_FIELD_GET(GMD_ID_STEP, val); 762 763 for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) 764 if (*ver == gmdid_display_map[i].ver && 765 *rel == gmdid_display_map[i].rel) 766 return gmdid_display_map[i].display; 767 768 drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n", 769 *ver, *rel); 770 return &no_display; 771 } 772 773 const struct intel_display_device_info * 774 intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid, 775 u16 *gmdid_ver, u16 *gmdid_rel, u16 *gmdid_step) 776 { 777 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 778 int i; 779 780 if (has_gmdid) 781 return probe_gmdid_display(i915, gmdid_ver, gmdid_rel, gmdid_step); 782 783 for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { 784 if (intel_display_ids[i].devid == pdev->device) 785 return intel_display_ids[i].info; 786 } 787 788 drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling display.\n", 789 pdev->device); 790 791 return &no_display; 792 } 793 794 void intel_display_device_info_runtime_init(struct drm_i915_private *i915) 795 { 796 struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915); 797 enum pipe pipe; 798 799 /* Wa_14011765242: adl-s A0,A1 */ 800 if (IS_ADLS_DISPLAY_STEP(i915, STEP_A0, STEP_A2)) 801 for_each_pipe(i915, pipe) 802 display_runtime->num_scalers[pipe] = 0; 803 else if (DISPLAY_VER(i915) >= 11) { 804 for_each_pipe(i915, pipe) 805 display_runtime->num_scalers[pipe] = 2; 806 } else if (DISPLAY_VER(i915) >= 9) { 807 display_runtime->num_scalers[PIPE_A] = 2; 808 display_runtime->num_scalers[PIPE_B] = 2; 809 display_runtime->num_scalers[PIPE_C] = 1; 810 } 811 812 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) 813 for_each_pipe(i915, pipe) 814 display_runtime->num_sprites[pipe] = 4; 815 else if (DISPLAY_VER(i915) >= 11) 816 for_each_pipe(i915, pipe) 817 display_runtime->num_sprites[pipe] = 6; 818 else if (DISPLAY_VER(i915) == 10) 819 for_each_pipe(i915, pipe) 820 display_runtime->num_sprites[pipe] = 3; 821 else if (IS_BROXTON(i915)) { 822 /* 823 * Skylake and Broxton currently don't expose the topmost plane as its 824 * use is exclusive with the legacy cursor and we only want to expose 825 * one of those, not both. Until we can safely expose the topmost plane 826 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 827 * we don't expose the topmost plane at all to prevent ABI breakage 828 * down the line. 829 */ 830 831 display_runtime->num_sprites[PIPE_A] = 2; 832 display_runtime->num_sprites[PIPE_B] = 2; 833 display_runtime->num_sprites[PIPE_C] = 1; 834 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 835 for_each_pipe(i915, pipe) 836 display_runtime->num_sprites[pipe] = 2; 837 } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) { 838 for_each_pipe(i915, pipe) 839 display_runtime->num_sprites[pipe] = 1; 840 } 841 842 if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) && 843 !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) { 844 drm_info(&i915->drm, "Display not present, disabling\n"); 845 goto display_fused_off; 846 } 847 848 if (IS_GRAPHICS_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) { 849 u32 fuse_strap = intel_de_read(i915, FUSE_STRAP); 850 u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP); 851 852 /* 853 * SFUSE_STRAP is supposed to have a bit signalling the display 854 * is fused off. Unfortunately it seems that, at least in 855 * certain cases, fused off display means that PCH display 856 * reads don't land anywhere. In that case, we read 0s. 857 * 858 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 859 * should be set when taking over after the firmware. 860 */ 861 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 862 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 863 (HAS_PCH_CPT(i915) && 864 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 865 drm_info(&i915->drm, 866 "Display fused off, disabling\n"); 867 goto display_fused_off; 868 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 869 drm_info(&i915->drm, "PipeC fused off\n"); 870 display_runtime->pipe_mask &= ~BIT(PIPE_C); 871 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 872 } 873 } else if (DISPLAY_VER(i915) >= 9) { 874 u32 dfsm = intel_de_read(i915, SKL_DFSM); 875 876 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { 877 display_runtime->pipe_mask &= ~BIT(PIPE_A); 878 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); 879 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A); 880 } 881 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { 882 display_runtime->pipe_mask &= ~BIT(PIPE_B); 883 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); 884 } 885 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { 886 display_runtime->pipe_mask &= ~BIT(PIPE_C); 887 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 888 } 889 890 if (DISPLAY_VER(i915) >= 12 && 891 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 892 display_runtime->pipe_mask &= ~BIT(PIPE_D); 893 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); 894 } 895 896 if (!display_runtime->pipe_mask) 897 goto display_fused_off; 898 899 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 900 display_runtime->has_hdcp = 0; 901 902 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 903 display_runtime->fbc_mask = 0; 904 905 if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 906 display_runtime->has_dmc = 0; 907 908 if (IS_DISPLAY_VER(i915, 10, 12) && 909 (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) 910 display_runtime->has_dsc = 0; 911 } 912 913 return; 914 915 display_fused_off: 916 memset(display_runtime, 0, sizeof(*display_runtime)); 917 } 918