1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <drm/i915_pciids.h> 7 #include <drm/drm_color_mgmt.h> 8 #include <linux/pci.h> 9 10 #include "i915_drv.h" 11 #include "i915_reg.h" 12 #include "intel_de.h" 13 #include "intel_display.h" 14 #include "intel_display_device.h" 15 #include "intel_display_power.h" 16 #include "intel_display_reg_defs.h" 17 #include "intel_fbc.h" 18 19 static const struct intel_display_device_info no_display = {}; 20 21 #define PIPE_A_OFFSET 0x70000 22 #define PIPE_B_OFFSET 0x71000 23 #define PIPE_C_OFFSET 0x72000 24 #define PIPE_D_OFFSET 0x73000 25 #define CHV_PIPE_C_OFFSET 0x74000 26 /* 27 * There's actually no pipe EDP. Some pipe registers have 28 * simply shifted from the pipe to the transcoder, while 29 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 30 * to access such registers in transcoder EDP. 31 */ 32 #define PIPE_EDP_OFFSET 0x7f000 33 34 /* ICL DSI 0 and 1 */ 35 #define PIPE_DSI0_OFFSET 0x7b000 36 #define PIPE_DSI1_OFFSET 0x7b800 37 38 #define TRANSCODER_A_OFFSET 0x60000 39 #define TRANSCODER_B_OFFSET 0x61000 40 #define TRANSCODER_C_OFFSET 0x62000 41 #define CHV_TRANSCODER_C_OFFSET 0x63000 42 #define TRANSCODER_D_OFFSET 0x63000 43 #define TRANSCODER_EDP_OFFSET 0x6f000 44 #define TRANSCODER_DSI0_OFFSET 0x6b000 45 #define TRANSCODER_DSI1_OFFSET 0x6b800 46 47 #define CURSOR_A_OFFSET 0x70080 48 #define CURSOR_B_OFFSET 0x700c0 49 #define CHV_CURSOR_C_OFFSET 0x700e0 50 #define IVB_CURSOR_B_OFFSET 0x71080 51 #define IVB_CURSOR_C_OFFSET 0x72080 52 #define TGL_CURSOR_D_OFFSET 0x73080 53 54 #define I845_PIPE_OFFSETS \ 55 .pipe_offsets = { \ 56 [TRANSCODER_A] = PIPE_A_OFFSET, \ 57 }, \ 58 .trans_offsets = { \ 59 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 60 } 61 62 #define I9XX_PIPE_OFFSETS \ 63 .pipe_offsets = { \ 64 [TRANSCODER_A] = PIPE_A_OFFSET, \ 65 [TRANSCODER_B] = PIPE_B_OFFSET, \ 66 }, \ 67 .trans_offsets = { \ 68 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 69 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 70 } 71 72 #define IVB_PIPE_OFFSETS \ 73 .pipe_offsets = { \ 74 [TRANSCODER_A] = PIPE_A_OFFSET, \ 75 [TRANSCODER_B] = PIPE_B_OFFSET, \ 76 [TRANSCODER_C] = PIPE_C_OFFSET, \ 77 }, \ 78 .trans_offsets = { \ 79 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 80 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 81 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 82 } 83 84 #define HSW_PIPE_OFFSETS \ 85 .pipe_offsets = { \ 86 [TRANSCODER_A] = PIPE_A_OFFSET, \ 87 [TRANSCODER_B] = PIPE_B_OFFSET, \ 88 [TRANSCODER_C] = PIPE_C_OFFSET, \ 89 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 90 }, \ 91 .trans_offsets = { \ 92 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 93 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 94 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 95 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 96 } 97 98 #define CHV_PIPE_OFFSETS \ 99 .pipe_offsets = { \ 100 [TRANSCODER_A] = PIPE_A_OFFSET, \ 101 [TRANSCODER_B] = PIPE_B_OFFSET, \ 102 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 103 }, \ 104 .trans_offsets = { \ 105 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 106 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 107 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 108 } 109 110 #define I845_CURSOR_OFFSETS \ 111 .cursor_offsets = { \ 112 [PIPE_A] = CURSOR_A_OFFSET, \ 113 } 114 115 #define I9XX_CURSOR_OFFSETS \ 116 .cursor_offsets = { \ 117 [PIPE_A] = CURSOR_A_OFFSET, \ 118 [PIPE_B] = CURSOR_B_OFFSET, \ 119 } 120 121 #define CHV_CURSOR_OFFSETS \ 122 .cursor_offsets = { \ 123 [PIPE_A] = CURSOR_A_OFFSET, \ 124 [PIPE_B] = CURSOR_B_OFFSET, \ 125 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 126 } 127 128 #define IVB_CURSOR_OFFSETS \ 129 .cursor_offsets = { \ 130 [PIPE_A] = CURSOR_A_OFFSET, \ 131 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 132 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 133 } 134 135 #define TGL_CURSOR_OFFSETS \ 136 .cursor_offsets = { \ 137 [PIPE_A] = CURSOR_A_OFFSET, \ 138 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 139 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 140 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 141 } 142 143 #define I845_COLORS \ 144 .color = { .gamma_lut_size = 256 } 145 #define I9XX_COLORS \ 146 .color = { .gamma_lut_size = 129, \ 147 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 148 } 149 #define ILK_COLORS \ 150 .color = { .gamma_lut_size = 1024 } 151 #define IVB_COLORS \ 152 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 153 #define CHV_COLORS \ 154 .color = { \ 155 .degamma_lut_size = 65, .gamma_lut_size = 257, \ 156 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 157 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 158 } 159 #define GLK_COLORS \ 160 .color = { \ 161 .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 162 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 163 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 164 } 165 #define ICL_COLORS \ 166 .color = { \ 167 .degamma_lut_size = 33, .gamma_lut_size = 262145, \ 168 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 169 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 170 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 171 } 172 173 #define I830_DISPLAY \ 174 .has_overlay = 1, \ 175 .cursor_needs_physical = 1, \ 176 .overlay_needs_physical = 1, \ 177 .has_gmch = 1, \ 178 I9XX_PIPE_OFFSETS, \ 179 I9XX_CURSOR_OFFSETS, \ 180 I9XX_COLORS, \ 181 \ 182 .__runtime_defaults.ip.ver = 2, \ 183 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 184 .__runtime_defaults.cpu_transcoder_mask = \ 185 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 186 187 static const struct intel_display_device_info i830_display = { 188 I830_DISPLAY, 189 }; 190 191 #define I845_DISPLAY \ 192 .has_overlay = 1, \ 193 .overlay_needs_physical = 1, \ 194 .has_gmch = 1, \ 195 I845_PIPE_OFFSETS, \ 196 I845_CURSOR_OFFSETS, \ 197 I845_COLORS, \ 198 \ 199 .__runtime_defaults.ip.ver = 2, \ 200 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \ 201 .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) 202 203 static const struct intel_display_device_info i845_display = { 204 I845_DISPLAY, 205 }; 206 207 static const struct intel_display_device_info i85x_display = { 208 I830_DISPLAY, 209 210 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 211 }; 212 213 static const struct intel_display_device_info i865g_display = { 214 I845_DISPLAY, 215 216 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 217 }; 218 219 #define GEN3_DISPLAY \ 220 .has_gmch = 1, \ 221 .has_overlay = 1, \ 222 I9XX_PIPE_OFFSETS, \ 223 I9XX_CURSOR_OFFSETS, \ 224 \ 225 .__runtime_defaults.ip.ver = 3, \ 226 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 227 .__runtime_defaults.cpu_transcoder_mask = \ 228 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 229 230 static const struct intel_display_device_info i915g_display = { 231 GEN3_DISPLAY, 232 I845_COLORS, 233 .cursor_needs_physical = 1, 234 .overlay_needs_physical = 1, 235 }; 236 237 static const struct intel_display_device_info i915gm_display = { 238 GEN3_DISPLAY, 239 I9XX_COLORS, 240 .cursor_needs_physical = 1, 241 .overlay_needs_physical = 1, 242 .supports_tv = 1, 243 244 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 245 }; 246 247 static const struct intel_display_device_info i945g_display = { 248 GEN3_DISPLAY, 249 I845_COLORS, 250 .has_hotplug = 1, 251 .cursor_needs_physical = 1, 252 .overlay_needs_physical = 1, 253 }; 254 255 static const struct intel_display_device_info i945gm_display = { 256 GEN3_DISPLAY, 257 I9XX_COLORS, 258 .has_hotplug = 1, 259 .cursor_needs_physical = 1, 260 .overlay_needs_physical = 1, 261 .supports_tv = 1, 262 263 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 264 }; 265 266 static const struct intel_display_device_info g33_display = { 267 GEN3_DISPLAY, 268 I845_COLORS, 269 .has_hotplug = 1, 270 }; 271 272 static const struct intel_display_device_info pnv_display = { 273 GEN3_DISPLAY, 274 I9XX_COLORS, 275 .has_hotplug = 1, 276 }; 277 278 #define GEN4_DISPLAY \ 279 .has_hotplug = 1, \ 280 .has_gmch = 1, \ 281 I9XX_PIPE_OFFSETS, \ 282 I9XX_CURSOR_OFFSETS, \ 283 I9XX_COLORS, \ 284 \ 285 .__runtime_defaults.ip.ver = 4, \ 286 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 287 .__runtime_defaults.cpu_transcoder_mask = \ 288 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 289 290 static const struct intel_display_device_info i965g_display = { 291 GEN4_DISPLAY, 292 .has_overlay = 1, 293 }; 294 295 static const struct intel_display_device_info i965gm_display = { 296 GEN4_DISPLAY, 297 .has_overlay = 1, 298 .supports_tv = 1, 299 300 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 301 }; 302 303 static const struct intel_display_device_info g45_display = { 304 GEN4_DISPLAY, 305 }; 306 307 static const struct intel_display_device_info gm45_display = { 308 GEN4_DISPLAY, 309 .supports_tv = 1, 310 311 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 312 }; 313 314 #define ILK_DISPLAY \ 315 .has_hotplug = 1, \ 316 I9XX_PIPE_OFFSETS, \ 317 I9XX_CURSOR_OFFSETS, \ 318 ILK_COLORS, \ 319 \ 320 .__runtime_defaults.ip.ver = 5, \ 321 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 322 .__runtime_defaults.cpu_transcoder_mask = \ 323 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) 324 325 static const struct intel_display_device_info ilk_d_display = { 326 ILK_DISPLAY, 327 }; 328 329 static const struct intel_display_device_info ilk_m_display = { 330 ILK_DISPLAY, 331 332 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 333 }; 334 335 static const struct intel_display_device_info snb_display = { 336 .has_hotplug = 1, 337 I9XX_PIPE_OFFSETS, 338 I9XX_CURSOR_OFFSETS, 339 ILK_COLORS, 340 341 .__runtime_defaults.ip.ver = 6, 342 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 343 .__runtime_defaults.cpu_transcoder_mask = 344 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 345 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 346 }; 347 348 static const struct intel_display_device_info ivb_display = { 349 .has_hotplug = 1, 350 IVB_PIPE_OFFSETS, 351 IVB_CURSOR_OFFSETS, 352 IVB_COLORS, 353 354 .__runtime_defaults.ip.ver = 7, 355 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 356 .__runtime_defaults.cpu_transcoder_mask = 357 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 358 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 359 }; 360 361 static const struct intel_display_device_info vlv_display = { 362 .has_gmch = 1, 363 .has_hotplug = 1, 364 .mmio_offset = VLV_DISPLAY_BASE, 365 I9XX_PIPE_OFFSETS, 366 I9XX_CURSOR_OFFSETS, 367 I9XX_COLORS, 368 369 .__runtime_defaults.ip.ver = 7, 370 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 371 .__runtime_defaults.cpu_transcoder_mask = 372 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 373 }; 374 375 static const struct intel_display_device_info hsw_display = { 376 .has_ddi = 1, 377 .has_dp_mst = 1, 378 .has_fpga_dbg = 1, 379 .has_hotplug = 1, 380 HSW_PIPE_OFFSETS, 381 IVB_CURSOR_OFFSETS, 382 IVB_COLORS, 383 384 .__runtime_defaults.ip.ver = 7, 385 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 386 .__runtime_defaults.cpu_transcoder_mask = 387 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 388 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 389 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 390 }; 391 392 static const struct intel_display_device_info bdw_display = { 393 .has_ddi = 1, 394 .has_dp_mst = 1, 395 .has_fpga_dbg = 1, 396 .has_hotplug = 1, 397 HSW_PIPE_OFFSETS, 398 IVB_CURSOR_OFFSETS, 399 IVB_COLORS, 400 401 .__runtime_defaults.ip.ver = 8, 402 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 403 .__runtime_defaults.cpu_transcoder_mask = 404 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 405 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 406 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 407 }; 408 409 static const struct intel_display_device_info chv_display = { 410 .has_hotplug = 1, 411 .has_gmch = 1, 412 .mmio_offset = VLV_DISPLAY_BASE, 413 CHV_PIPE_OFFSETS, 414 CHV_CURSOR_OFFSETS, 415 CHV_COLORS, 416 417 .__runtime_defaults.ip.ver = 8, 418 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 419 .__runtime_defaults.cpu_transcoder_mask = 420 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 421 }; 422 423 static const struct intel_display_device_info skl_display = { 424 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ 425 .dbuf.slice_mask = BIT(DBUF_S1), 426 .has_ddi = 1, 427 .has_dp_mst = 1, 428 .has_fpga_dbg = 1, 429 .has_hotplug = 1, 430 .has_ipc = 1, 431 .has_psr = 1, 432 .has_psr_hw_tracking = 1, 433 HSW_PIPE_OFFSETS, 434 IVB_CURSOR_OFFSETS, 435 IVB_COLORS, 436 437 .__runtime_defaults.ip.ver = 9, 438 .__runtime_defaults.has_dmc = 1, 439 .__runtime_defaults.has_hdcp = 1, 440 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 441 .__runtime_defaults.cpu_transcoder_mask = 442 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 443 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), 444 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 445 }; 446 447 #define GEN9_LP_DISPLAY \ 448 .dbuf.slice_mask = BIT(DBUF_S1), \ 449 .has_dp_mst = 1, \ 450 .has_ddi = 1, \ 451 .has_fpga_dbg = 1, \ 452 .has_hotplug = 1, \ 453 .has_ipc = 1, \ 454 .has_psr = 1, \ 455 .has_psr_hw_tracking = 1, \ 456 HSW_PIPE_OFFSETS, \ 457 IVB_CURSOR_OFFSETS, \ 458 IVB_COLORS, \ 459 \ 460 .__runtime_defaults.has_dmc = 1, \ 461 .__runtime_defaults.has_hdcp = 1, \ 462 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \ 463 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 464 .__runtime_defaults.cpu_transcoder_mask = \ 465 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 466 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 467 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C) 468 469 static const struct intel_display_device_info bxt_display = { 470 GEN9_LP_DISPLAY, 471 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ 472 473 .__runtime_defaults.ip.ver = 9, 474 }; 475 476 static const struct intel_display_device_info glk_display = { 477 GEN9_LP_DISPLAY, 478 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ 479 GLK_COLORS, 480 481 .__runtime_defaults.ip.ver = 10, 482 }; 483 484 static const struct intel_display_device_info gen11_display = { 485 .abox_mask = BIT(0), 486 .dbuf.size = 2048, 487 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), 488 .has_ddi = 1, 489 .has_dp_mst = 1, 490 .has_fpga_dbg = 1, 491 .has_hotplug = 1, 492 .has_ipc = 1, 493 .has_psr = 1, 494 .has_psr_hw_tracking = 1, 495 .pipe_offsets = { 496 [TRANSCODER_A] = PIPE_A_OFFSET, 497 [TRANSCODER_B] = PIPE_B_OFFSET, 498 [TRANSCODER_C] = PIPE_C_OFFSET, 499 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, 500 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, 501 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, 502 }, 503 .trans_offsets = { 504 [TRANSCODER_A] = TRANSCODER_A_OFFSET, 505 [TRANSCODER_B] = TRANSCODER_B_OFFSET, 506 [TRANSCODER_C] = TRANSCODER_C_OFFSET, 507 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, 508 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, 509 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, 510 }, 511 IVB_CURSOR_OFFSETS, 512 ICL_COLORS, 513 514 .__runtime_defaults.ip.ver = 11, 515 .__runtime_defaults.has_dmc = 1, 516 .__runtime_defaults.has_dsc = 1, 517 .__runtime_defaults.has_hdcp = 1, 518 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 519 .__runtime_defaults.cpu_transcoder_mask = 520 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 521 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | 522 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 523 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 524 }; 525 526 #define XE_D_DISPLAY \ 527 .abox_mask = GENMASK(2, 1), \ 528 .dbuf.size = 2048, \ 529 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 530 .has_ddi = 1, \ 531 .has_dp_mst = 1, \ 532 .has_dsb = 1, \ 533 .has_fpga_dbg = 1, \ 534 .has_hotplug = 1, \ 535 .has_ipc = 1, \ 536 .has_psr = 1, \ 537 .has_psr_hw_tracking = 1, \ 538 .pipe_offsets = { \ 539 [TRANSCODER_A] = PIPE_A_OFFSET, \ 540 [TRANSCODER_B] = PIPE_B_OFFSET, \ 541 [TRANSCODER_C] = PIPE_C_OFFSET, \ 542 [TRANSCODER_D] = PIPE_D_OFFSET, \ 543 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 544 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 545 }, \ 546 .trans_offsets = { \ 547 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 548 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 549 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 550 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 551 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 552 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 553 }, \ 554 TGL_CURSOR_OFFSETS, \ 555 ICL_COLORS, \ 556 \ 557 .__runtime_defaults.ip.ver = 12, \ 558 .__runtime_defaults.has_dmc = 1, \ 559 .__runtime_defaults.has_dsc = 1, \ 560 .__runtime_defaults.has_hdcp = 1, \ 561 .__runtime_defaults.pipe_mask = \ 562 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 563 .__runtime_defaults.cpu_transcoder_mask = \ 564 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 565 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 566 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 567 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) 568 569 static const struct intel_display_device_info tgl_display = { 570 XE_D_DISPLAY, 571 }; 572 573 static const struct intel_display_device_info rkl_display = { 574 XE_D_DISPLAY, 575 .abox_mask = BIT(0), 576 .has_hti = 1, 577 .has_psr_hw_tracking = 0, 578 579 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 580 .__runtime_defaults.cpu_transcoder_mask = 581 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 582 }; 583 584 static const struct intel_display_device_info adl_s_display = { 585 XE_D_DISPLAY, 586 .has_hti = 1, 587 .has_psr_hw_tracking = 0, 588 }; 589 590 #define XE_LPD_FEATURES \ 591 .abox_mask = GENMASK(1, 0), \ 592 .color = { \ 593 .degamma_lut_size = 129, .gamma_lut_size = 1024, \ 594 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 595 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 596 }, \ 597 .dbuf.size = 4096, \ 598 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 599 BIT(DBUF_S4), \ 600 .has_ddi = 1, \ 601 .has_dp_mst = 1, \ 602 .has_dsb = 1, \ 603 .has_fpga_dbg = 1, \ 604 .has_hotplug = 1, \ 605 .has_ipc = 1, \ 606 .has_psr = 1, \ 607 .pipe_offsets = { \ 608 [TRANSCODER_A] = PIPE_A_OFFSET, \ 609 [TRANSCODER_B] = PIPE_B_OFFSET, \ 610 [TRANSCODER_C] = PIPE_C_OFFSET, \ 611 [TRANSCODER_D] = PIPE_D_OFFSET, \ 612 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 613 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 614 }, \ 615 .trans_offsets = { \ 616 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 617 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 618 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 619 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 620 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 621 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 622 }, \ 623 TGL_CURSOR_OFFSETS, \ 624 \ 625 .__runtime_defaults.ip.ver = 13, \ 626 .__runtime_defaults.has_dmc = 1, \ 627 .__runtime_defaults.has_dsc = 1, \ 628 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \ 629 .__runtime_defaults.has_hdcp = 1, \ 630 .__runtime_defaults.pipe_mask = \ 631 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D) 632 633 static const struct intel_display_device_info xe_lpd_display = { 634 XE_LPD_FEATURES, 635 .has_cdclk_crawl = 1, 636 .has_psr_hw_tracking = 0, 637 638 .__runtime_defaults.cpu_transcoder_mask = 639 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 640 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 641 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 642 }; 643 644 static const struct intel_display_device_info xe_hpd_display = { 645 XE_LPD_FEATURES, 646 .has_cdclk_squash = 1, 647 648 .__runtime_defaults.cpu_transcoder_mask = 649 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 650 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 651 }; 652 653 static const struct intel_display_device_info xe_lpdp_display = { 654 XE_LPD_FEATURES, 655 .has_cdclk_crawl = 1, 656 .has_cdclk_squash = 1, 657 658 .__runtime_defaults.ip.ver = 14, 659 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), 660 .__runtime_defaults.cpu_transcoder_mask = 661 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 662 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 663 }; 664 665 #undef INTEL_VGA_DEVICE 666 #undef INTEL_QUANTA_VGA_DEVICE 667 #define INTEL_VGA_DEVICE(id, info) { id, info } 668 #define INTEL_QUANTA_VGA_DEVICE(info) { 0x16a, info } 669 670 static const struct { 671 u32 devid; 672 const struct intel_display_device_info *info; 673 } intel_display_ids[] = { 674 INTEL_I830_IDS(&i830_display), 675 INTEL_I845G_IDS(&i845_display), 676 INTEL_I85X_IDS(&i85x_display), 677 INTEL_I865G_IDS(&i865g_display), 678 INTEL_I915G_IDS(&i915g_display), 679 INTEL_I915GM_IDS(&i915gm_display), 680 INTEL_I945G_IDS(&i945g_display), 681 INTEL_I945GM_IDS(&i945gm_display), 682 INTEL_I965G_IDS(&i965g_display), 683 INTEL_G33_IDS(&g33_display), 684 INTEL_I965GM_IDS(&i965gm_display), 685 INTEL_GM45_IDS(&gm45_display), 686 INTEL_G45_IDS(&g45_display), 687 INTEL_PINEVIEW_G_IDS(&pnv_display), 688 INTEL_PINEVIEW_M_IDS(&pnv_display), 689 INTEL_IRONLAKE_D_IDS(&ilk_d_display), 690 INTEL_IRONLAKE_M_IDS(&ilk_m_display), 691 INTEL_SNB_D_IDS(&snb_display), 692 INTEL_SNB_M_IDS(&snb_display), 693 INTEL_IVB_Q_IDS(NULL), /* must be first IVB in list */ 694 INTEL_IVB_M_IDS(&ivb_display), 695 INTEL_IVB_D_IDS(&ivb_display), 696 INTEL_HSW_IDS(&hsw_display), 697 INTEL_VLV_IDS(&vlv_display), 698 INTEL_BDW_IDS(&bdw_display), 699 INTEL_CHV_IDS(&chv_display), 700 INTEL_SKL_IDS(&skl_display), 701 INTEL_BXT_IDS(&bxt_display), 702 INTEL_GLK_IDS(&glk_display), 703 INTEL_KBL_IDS(&skl_display), 704 INTEL_CFL_IDS(&skl_display), 705 INTEL_ICL_11_IDS(&gen11_display), 706 INTEL_EHL_IDS(&gen11_display), 707 INTEL_JSL_IDS(&gen11_display), 708 INTEL_TGL_12_IDS(&tgl_display), 709 INTEL_DG1_IDS(&tgl_display), 710 INTEL_RKL_IDS(&rkl_display), 711 INTEL_ADLS_IDS(&adl_s_display), 712 INTEL_RPLS_IDS(&adl_s_display), 713 INTEL_ADLP_IDS(&xe_lpd_display), 714 INTEL_ADLN_IDS(&xe_lpd_display), 715 INTEL_RPLP_IDS(&xe_lpd_display), 716 INTEL_DG2_IDS(&xe_hpd_display), 717 718 /* 719 * Do not add any GMD_ID-based platforms to this list. They will 720 * be probed automatically based on the IP version reported by 721 * the hardware. 722 */ 723 }; 724 725 static const struct { 726 u16 ver; 727 u16 rel; 728 const struct intel_display_device_info *display; 729 } gmdid_display_map[] = { 730 { 14, 0, &xe_lpdp_display }, 731 }; 732 733 static const struct intel_display_device_info * 734 probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step) 735 { 736 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 737 void __iomem *addr; 738 u32 val; 739 int i; 740 741 addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); 742 if (!addr) { 743 drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n"); 744 return &no_display; 745 } 746 747 val = ioread32(addr); 748 pci_iounmap(pdev, addr); 749 750 if (val == 0) 751 /* Platform doesn't have display */ 752 return &no_display; 753 754 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); 755 *rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 756 *step = REG_FIELD_GET(GMD_ID_STEP, val); 757 758 for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) 759 if (*ver == gmdid_display_map[i].ver && 760 *rel == gmdid_display_map[i].rel) 761 return gmdid_display_map[i].display; 762 763 drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n", 764 *ver, *rel); 765 return &no_display; 766 } 767 768 const struct intel_display_device_info * 769 intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid, 770 u16 *gmdid_ver, u16 *gmdid_rel, u16 *gmdid_step) 771 { 772 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 773 int i; 774 775 if (has_gmdid) 776 return probe_gmdid_display(i915, gmdid_ver, gmdid_rel, gmdid_step); 777 778 for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { 779 if (intel_display_ids[i].devid == pdev->device) 780 return intel_display_ids[i].info; 781 } 782 783 drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling display.\n", 784 pdev->device); 785 786 return &no_display; 787 } 788 789 void intel_display_device_info_runtime_init(struct drm_i915_private *i915) 790 { 791 struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915); 792 enum pipe pipe; 793 794 /* Wa_14011765242: adl-s A0,A1 */ 795 if (IS_ADLS_DISPLAY_STEP(i915, STEP_A0, STEP_A2)) 796 for_each_pipe(i915, pipe) 797 display_runtime->num_scalers[pipe] = 0; 798 else if (DISPLAY_VER(i915) >= 11) { 799 for_each_pipe(i915, pipe) 800 display_runtime->num_scalers[pipe] = 2; 801 } else if (DISPLAY_VER(i915) >= 9) { 802 display_runtime->num_scalers[PIPE_A] = 2; 803 display_runtime->num_scalers[PIPE_B] = 2; 804 display_runtime->num_scalers[PIPE_C] = 1; 805 } 806 807 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) 808 for_each_pipe(i915, pipe) 809 display_runtime->num_sprites[pipe] = 4; 810 else if (DISPLAY_VER(i915) >= 11) 811 for_each_pipe(i915, pipe) 812 display_runtime->num_sprites[pipe] = 6; 813 else if (DISPLAY_VER(i915) == 10) 814 for_each_pipe(i915, pipe) 815 display_runtime->num_sprites[pipe] = 3; 816 else if (IS_BROXTON(i915)) { 817 /* 818 * Skylake and Broxton currently don't expose the topmost plane as its 819 * use is exclusive with the legacy cursor and we only want to expose 820 * one of those, not both. Until we can safely expose the topmost plane 821 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 822 * we don't expose the topmost plane at all to prevent ABI breakage 823 * down the line. 824 */ 825 826 display_runtime->num_sprites[PIPE_A] = 2; 827 display_runtime->num_sprites[PIPE_B] = 2; 828 display_runtime->num_sprites[PIPE_C] = 1; 829 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 830 for_each_pipe(i915, pipe) 831 display_runtime->num_sprites[pipe] = 2; 832 } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) { 833 for_each_pipe(i915, pipe) 834 display_runtime->num_sprites[pipe] = 1; 835 } 836 837 if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) && 838 !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) { 839 drm_info(&i915->drm, "Display not present, disabling\n"); 840 goto display_fused_off; 841 } 842 843 if (IS_GRAPHICS_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) { 844 u32 fuse_strap = intel_de_read(i915, FUSE_STRAP); 845 u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP); 846 847 /* 848 * SFUSE_STRAP is supposed to have a bit signalling the display 849 * is fused off. Unfortunately it seems that, at least in 850 * certain cases, fused off display means that PCH display 851 * reads don't land anywhere. In that case, we read 0s. 852 * 853 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 854 * should be set when taking over after the firmware. 855 */ 856 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 857 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 858 (HAS_PCH_CPT(i915) && 859 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 860 drm_info(&i915->drm, 861 "Display fused off, disabling\n"); 862 goto display_fused_off; 863 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 864 drm_info(&i915->drm, "PipeC fused off\n"); 865 display_runtime->pipe_mask &= ~BIT(PIPE_C); 866 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 867 } 868 } else if (DISPLAY_VER(i915) >= 9) { 869 u32 dfsm = intel_de_read(i915, SKL_DFSM); 870 871 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { 872 display_runtime->pipe_mask &= ~BIT(PIPE_A); 873 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); 874 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A); 875 } 876 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { 877 display_runtime->pipe_mask &= ~BIT(PIPE_B); 878 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); 879 } 880 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { 881 display_runtime->pipe_mask &= ~BIT(PIPE_C); 882 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 883 } 884 885 if (DISPLAY_VER(i915) >= 12 && 886 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 887 display_runtime->pipe_mask &= ~BIT(PIPE_D); 888 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); 889 } 890 891 if (!display_runtime->pipe_mask) 892 goto display_fused_off; 893 894 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 895 display_runtime->has_hdcp = 0; 896 897 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 898 display_runtime->fbc_mask = 0; 899 900 if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 901 display_runtime->has_dmc = 0; 902 903 if (IS_DISPLAY_VER(i915, 10, 12) && 904 (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) 905 display_runtime->has_dsc = 0; 906 } 907 908 return; 909 910 display_fused_off: 911 memset(display_runtime, 0, sizeof(*display_runtime)); 912 } 913