1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include <drm/drm_debugfs.h> 9 #include <drm/drm_fourcc.h> 10 11 #include "i915_debugfs.h" 12 #include "intel_de.h" 13 #include "intel_display_debugfs.h" 14 #include "intel_display_power.h" 15 #include "intel_display_power_well.h" 16 #include "intel_display_types.h" 17 #include "intel_dmc.h" 18 #include "intel_dp.h" 19 #include "intel_dp_mst.h" 20 #include "intel_drrs.h" 21 #include "intel_fbc.h" 22 #include "intel_fbdev.h" 23 #include "intel_hdcp.h" 24 #include "intel_hdmi.h" 25 #include "intel_panel.h" 26 #include "intel_pm.h" 27 #include "intel_psr.h" 28 #include "intel_sprite.h" 29 30 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 31 { 32 return to_i915(node->minor->dev); 33 } 34 35 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) 36 { 37 struct drm_i915_private *dev_priv = node_to_i915(m->private); 38 39 seq_printf(m, "FB tracking busy bits: 0x%08x\n", 40 dev_priv->fb_tracking.busy_bits); 41 42 seq_printf(m, "FB tracking flip bits: 0x%08x\n", 43 dev_priv->fb_tracking.flip_bits); 44 45 return 0; 46 } 47 48 static int i915_ips_status(struct seq_file *m, void *unused) 49 { 50 struct drm_i915_private *dev_priv = node_to_i915(m->private); 51 intel_wakeref_t wakeref; 52 53 if (!HAS_IPS(dev_priv)) 54 return -ENODEV; 55 56 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 57 58 seq_printf(m, "Enabled by kernel parameter: %s\n", 59 str_yes_no(dev_priv->params.enable_ips)); 60 61 if (DISPLAY_VER(dev_priv) >= 8) { 62 seq_puts(m, "Currently: unknown\n"); 63 } else { 64 if (intel_de_read(dev_priv, IPS_CTL) & IPS_ENABLE) 65 seq_puts(m, "Currently: enabled\n"); 66 else 67 seq_puts(m, "Currently: disabled\n"); 68 } 69 70 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 71 72 return 0; 73 } 74 75 static int i915_sr_status(struct seq_file *m, void *unused) 76 { 77 struct drm_i915_private *dev_priv = node_to_i915(m->private); 78 intel_wakeref_t wakeref; 79 bool sr_enabled = false; 80 81 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 82 83 if (DISPLAY_VER(dev_priv) >= 9) 84 /* no global SR status; inspect per-plane WM */; 85 else if (HAS_PCH_SPLIT(dev_priv)) 86 sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE; 87 else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || 88 IS_I945G(dev_priv) || IS_I945GM(dev_priv)) 89 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN; 90 else if (IS_I915GM(dev_priv)) 91 sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN; 92 else if (IS_PINEVIEW(dev_priv)) 93 sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN; 94 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 95 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; 96 97 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 98 99 seq_printf(m, "self-refresh: %s\n", str_enabled_disabled(sr_enabled)); 100 101 return 0; 102 } 103 104 static int i915_opregion(struct seq_file *m, void *unused) 105 { 106 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; 107 108 if (opregion->header) 109 seq_write(m, opregion->header, OPREGION_SIZE); 110 111 return 0; 112 } 113 114 static int i915_vbt(struct seq_file *m, void *unused) 115 { 116 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; 117 118 if (opregion->vbt) 119 seq_write(m, opregion->vbt, opregion->vbt_size); 120 121 return 0; 122 } 123 124 static int i915_gem_framebuffer_info(struct seq_file *m, void *data) 125 { 126 struct drm_i915_private *dev_priv = node_to_i915(m->private); 127 struct drm_device *dev = &dev_priv->drm; 128 struct intel_framebuffer *fbdev_fb = NULL; 129 struct drm_framebuffer *drm_fb; 130 131 #ifdef CONFIG_DRM_FBDEV_EMULATION 132 fbdev_fb = intel_fbdev_framebuffer(dev_priv->fbdev); 133 if (fbdev_fb) { 134 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 135 fbdev_fb->base.width, 136 fbdev_fb->base.height, 137 fbdev_fb->base.format->depth, 138 fbdev_fb->base.format->cpp[0] * 8, 139 fbdev_fb->base.modifier, 140 drm_framebuffer_read_refcount(&fbdev_fb->base)); 141 i915_debugfs_describe_obj(m, intel_fb_obj(&fbdev_fb->base)); 142 seq_putc(m, '\n'); 143 } 144 #endif 145 146 mutex_lock(&dev->mode_config.fb_lock); 147 drm_for_each_fb(drm_fb, dev) { 148 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); 149 if (fb == fbdev_fb) 150 continue; 151 152 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 153 fb->base.width, 154 fb->base.height, 155 fb->base.format->depth, 156 fb->base.format->cpp[0] * 8, 157 fb->base.modifier, 158 drm_framebuffer_read_refcount(&fb->base)); 159 i915_debugfs_describe_obj(m, intel_fb_obj(&fb->base)); 160 seq_putc(m, '\n'); 161 } 162 mutex_unlock(&dev->mode_config.fb_lock); 163 164 return 0; 165 } 166 167 static int i915_psr_sink_status_show(struct seq_file *m, void *data) 168 { 169 u8 val; 170 static const char * const sink_status[] = { 171 "inactive", 172 "transition to active, capture and display", 173 "active, display from RFB", 174 "active, capture and display on sink device timings", 175 "transition to inactive, capture and display, timing re-sync", 176 "reserved", 177 "reserved", 178 "sink internal error", 179 }; 180 struct drm_connector *connector = m->private; 181 struct intel_dp *intel_dp = 182 intel_attached_dp(to_intel_connector(connector)); 183 int ret; 184 185 if (!CAN_PSR(intel_dp)) { 186 seq_puts(m, "PSR Unsupported\n"); 187 return -ENODEV; 188 } 189 190 if (connector->status != connector_status_connected) 191 return -ENODEV; 192 193 ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val); 194 195 if (ret == 1) { 196 const char *str = "unknown"; 197 198 val &= DP_PSR_SINK_STATE_MASK; 199 if (val < ARRAY_SIZE(sink_status)) 200 str = sink_status[val]; 201 seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str); 202 } else { 203 return ret; 204 } 205 206 return 0; 207 } 208 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status); 209 210 static void 211 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) 212 { 213 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 214 const char *status = "unknown"; 215 u32 val, status_val; 216 217 if (intel_dp->psr.psr2_enabled) { 218 static const char * const live_status[] = { 219 "IDLE", 220 "CAPTURE", 221 "CAPTURE_FS", 222 "SLEEP", 223 "BUFON_FW", 224 "ML_UP", 225 "SU_STANDBY", 226 "FAST_SLEEP", 227 "DEEP_SLEEP", 228 "BUF_ON", 229 "TG_ON" 230 }; 231 val = intel_de_read(dev_priv, 232 EDP_PSR2_STATUS(intel_dp->psr.transcoder)); 233 status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val); 234 if (status_val < ARRAY_SIZE(live_status)) 235 status = live_status[status_val]; 236 } else { 237 static const char * const live_status[] = { 238 "IDLE", 239 "SRDONACK", 240 "SRDENT", 241 "BUFOFF", 242 "BUFON", 243 "AUXACK", 244 "SRDOFFACK", 245 "SRDENT_ON", 246 }; 247 val = intel_de_read(dev_priv, 248 EDP_PSR_STATUS(intel_dp->psr.transcoder)); 249 status_val = (val & EDP_PSR_STATUS_STATE_MASK) >> 250 EDP_PSR_STATUS_STATE_SHIFT; 251 if (status_val < ARRAY_SIZE(live_status)) 252 status = live_status[status_val]; 253 } 254 255 seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val); 256 } 257 258 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) 259 { 260 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 261 struct intel_psr *psr = &intel_dp->psr; 262 intel_wakeref_t wakeref; 263 const char *status; 264 bool enabled; 265 u32 val; 266 267 seq_printf(m, "Sink support: %s", str_yes_no(psr->sink_support)); 268 if (psr->sink_support) 269 seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); 270 seq_puts(m, "\n"); 271 272 if (!psr->sink_support) 273 return 0; 274 275 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 276 mutex_lock(&psr->lock); 277 278 if (psr->enabled) 279 status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled"; 280 else 281 status = "disabled"; 282 seq_printf(m, "PSR mode: %s\n", status); 283 284 if (!psr->enabled) { 285 seq_printf(m, "PSR sink not reliable: %s\n", 286 str_yes_no(psr->sink_not_reliable)); 287 288 goto unlock; 289 } 290 291 if (psr->psr2_enabled) { 292 val = intel_de_read(dev_priv, 293 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 294 enabled = val & EDP_PSR2_ENABLE; 295 } else { 296 val = intel_de_read(dev_priv, 297 EDP_PSR_CTL(intel_dp->psr.transcoder)); 298 enabled = val & EDP_PSR_ENABLE; 299 } 300 seq_printf(m, "Source PSR ctl: %s [0x%08x]\n", 301 str_enabled_disabled(enabled), val); 302 psr_source_status(intel_dp, m); 303 seq_printf(m, "Busy frontbuffer bits: 0x%08x\n", 304 psr->busy_frontbuffer_bits); 305 306 /* 307 * SKL+ Perf counter is reset to 0 everytime DC state is entered 308 */ 309 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 310 val = intel_de_read(dev_priv, 311 EDP_PSR_PERF_CNT(intel_dp->psr.transcoder)); 312 val &= EDP_PSR_PERF_CNT_MASK; 313 seq_printf(m, "Performance counter: %u\n", val); 314 } 315 316 if (psr->debug & I915_PSR_DEBUG_IRQ) { 317 seq_printf(m, "Last attempted entry at: %lld\n", 318 psr->last_entry_attempt); 319 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); 320 } 321 322 if (psr->psr2_enabled) { 323 u32 su_frames_val[3]; 324 int frame; 325 326 /* 327 * Reading all 3 registers before hand to minimize crossing a 328 * frame boundary between register reads 329 */ 330 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) { 331 val = intel_de_read(dev_priv, 332 PSR2_SU_STATUS(intel_dp->psr.transcoder, frame)); 333 su_frames_val[frame / 3] = val; 334 } 335 336 seq_puts(m, "Frame:\tPSR2 SU blocks:\n"); 337 338 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) { 339 u32 su_blocks; 340 341 su_blocks = su_frames_val[frame / 3] & 342 PSR2_SU_STATUS_MASK(frame); 343 su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); 344 seq_printf(m, "%d\t%d\n", frame, su_blocks); 345 } 346 347 seq_printf(m, "PSR2 selective fetch: %s\n", 348 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); 349 } 350 351 unlock: 352 mutex_unlock(&psr->lock); 353 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 354 355 return 0; 356 } 357 358 static int i915_edp_psr_status(struct seq_file *m, void *data) 359 { 360 struct drm_i915_private *dev_priv = node_to_i915(m->private); 361 struct intel_dp *intel_dp = NULL; 362 struct intel_encoder *encoder; 363 364 if (!HAS_PSR(dev_priv)) 365 return -ENODEV; 366 367 /* Find the first EDP which supports PSR */ 368 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 369 intel_dp = enc_to_intel_dp(encoder); 370 break; 371 } 372 373 if (!intel_dp) 374 return -ENODEV; 375 376 return intel_psr_status(m, intel_dp); 377 } 378 379 static int 380 i915_edp_psr_debug_set(void *data, u64 val) 381 { 382 struct drm_i915_private *dev_priv = data; 383 struct intel_encoder *encoder; 384 intel_wakeref_t wakeref; 385 int ret = -ENODEV; 386 387 if (!HAS_PSR(dev_priv)) 388 return ret; 389 390 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 391 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 392 393 drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val); 394 395 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 396 397 // TODO: split to each transcoder's PSR debug state 398 ret = intel_psr_debug_set(intel_dp, val); 399 400 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 401 } 402 403 return ret; 404 } 405 406 static int 407 i915_edp_psr_debug_get(void *data, u64 *val) 408 { 409 struct drm_i915_private *dev_priv = data; 410 struct intel_encoder *encoder; 411 412 if (!HAS_PSR(dev_priv)) 413 return -ENODEV; 414 415 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 416 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 417 418 // TODO: split to each transcoder's PSR debug state 419 *val = READ_ONCE(intel_dp->psr.debug); 420 return 0; 421 } 422 423 return -ENODEV; 424 } 425 426 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops, 427 i915_edp_psr_debug_get, i915_edp_psr_debug_set, 428 "%llu\n"); 429 430 static int i915_power_domain_info(struct seq_file *m, void *unused) 431 { 432 struct drm_i915_private *i915 = node_to_i915(m->private); 433 434 intel_display_power_debug(i915, m); 435 436 return 0; 437 } 438 439 static void intel_seq_print_mode(struct seq_file *m, int tabs, 440 const struct drm_display_mode *mode) 441 { 442 int i; 443 444 for (i = 0; i < tabs; i++) 445 seq_putc(m, '\t'); 446 447 seq_printf(m, DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); 448 } 449 450 static void intel_encoder_info(struct seq_file *m, 451 struct intel_crtc *crtc, 452 struct intel_encoder *encoder) 453 { 454 struct drm_i915_private *dev_priv = node_to_i915(m->private); 455 struct drm_connector_list_iter conn_iter; 456 struct drm_connector *connector; 457 458 seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n", 459 encoder->base.base.id, encoder->base.name); 460 461 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 462 drm_for_each_connector_iter(connector, &conn_iter) { 463 const struct drm_connector_state *conn_state = 464 connector->state; 465 466 if (conn_state->best_encoder != &encoder->base) 467 continue; 468 469 seq_printf(m, "\t\t[CONNECTOR:%d:%s]\n", 470 connector->base.id, connector->name); 471 } 472 drm_connector_list_iter_end(&conn_iter); 473 } 474 475 static void intel_panel_info(struct seq_file *m, 476 struct intel_connector *connector) 477 { 478 const struct drm_display_mode *fixed_mode; 479 480 if (list_empty(&connector->panel.fixed_modes)) 481 return; 482 483 seq_puts(m, "\tfixed modes:\n"); 484 485 list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) 486 intel_seq_print_mode(m, 2, fixed_mode); 487 } 488 489 static void intel_hdcp_info(struct seq_file *m, 490 struct intel_connector *intel_connector) 491 { 492 bool hdcp_cap, hdcp2_cap; 493 494 if (!intel_connector->hdcp.shim) { 495 seq_puts(m, "No Connector Support"); 496 goto out; 497 } 498 499 hdcp_cap = intel_hdcp_capable(intel_connector); 500 hdcp2_cap = intel_hdcp2_capable(intel_connector); 501 502 if (hdcp_cap) 503 seq_puts(m, "HDCP1.4 "); 504 if (hdcp2_cap) 505 seq_puts(m, "HDCP2.2 "); 506 507 if (!hdcp_cap && !hdcp2_cap) 508 seq_puts(m, "None"); 509 510 out: 511 seq_puts(m, "\n"); 512 } 513 514 static void intel_dp_info(struct seq_file *m, 515 struct intel_connector *intel_connector) 516 { 517 struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); 518 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); 519 const struct drm_property_blob *edid = intel_connector->base.edid_blob_ptr; 520 521 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); 522 seq_printf(m, "\taudio support: %s\n", 523 str_yes_no(intel_dp->has_audio)); 524 525 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, 526 edid ? edid->data : NULL, &intel_dp->aux); 527 } 528 529 static void intel_dp_mst_info(struct seq_file *m, 530 struct intel_connector *intel_connector) 531 { 532 bool has_audio = intel_connector->port->has_audio; 533 534 seq_printf(m, "\taudio support: %s\n", str_yes_no(has_audio)); 535 } 536 537 static void intel_hdmi_info(struct seq_file *m, 538 struct intel_connector *intel_connector) 539 { 540 struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); 541 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(intel_encoder); 542 543 seq_printf(m, "\taudio support: %s\n", 544 str_yes_no(intel_hdmi->has_audio)); 545 } 546 547 static void intel_connector_info(struct seq_file *m, 548 struct drm_connector *connector) 549 { 550 struct intel_connector *intel_connector = to_intel_connector(connector); 551 const struct drm_connector_state *conn_state = connector->state; 552 struct intel_encoder *encoder = 553 to_intel_encoder(conn_state->best_encoder); 554 const struct drm_display_mode *mode; 555 556 seq_printf(m, "[CONNECTOR:%d:%s]: status: %s\n", 557 connector->base.id, connector->name, 558 drm_get_connector_status_name(connector->status)); 559 560 if (connector->status == connector_status_disconnected) 561 return; 562 563 seq_printf(m, "\tphysical dimensions: %dx%dmm\n", 564 connector->display_info.width_mm, 565 connector->display_info.height_mm); 566 seq_printf(m, "\tsubpixel order: %s\n", 567 drm_get_subpixel_order_name(connector->display_info.subpixel_order)); 568 seq_printf(m, "\tCEA rev: %d\n", connector->display_info.cea_rev); 569 570 if (!encoder) 571 return; 572 573 switch (connector->connector_type) { 574 case DRM_MODE_CONNECTOR_DisplayPort: 575 case DRM_MODE_CONNECTOR_eDP: 576 if (encoder->type == INTEL_OUTPUT_DP_MST) 577 intel_dp_mst_info(m, intel_connector); 578 else 579 intel_dp_info(m, intel_connector); 580 break; 581 case DRM_MODE_CONNECTOR_HDMIA: 582 if (encoder->type == INTEL_OUTPUT_HDMI || 583 encoder->type == INTEL_OUTPUT_DDI) 584 intel_hdmi_info(m, intel_connector); 585 break; 586 default: 587 break; 588 } 589 590 seq_puts(m, "\tHDCP version: "); 591 intel_hdcp_info(m, intel_connector); 592 593 seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc); 594 595 intel_panel_info(m, intel_connector); 596 597 seq_printf(m, "\tmodes:\n"); 598 list_for_each_entry(mode, &connector->modes, head) 599 intel_seq_print_mode(m, 2, mode); 600 } 601 602 static const char *plane_type(enum drm_plane_type type) 603 { 604 switch (type) { 605 case DRM_PLANE_TYPE_OVERLAY: 606 return "OVL"; 607 case DRM_PLANE_TYPE_PRIMARY: 608 return "PRI"; 609 case DRM_PLANE_TYPE_CURSOR: 610 return "CUR"; 611 /* 612 * Deliberately omitting default: to generate compiler warnings 613 * when a new drm_plane_type gets added. 614 */ 615 } 616 617 return "unknown"; 618 } 619 620 static void plane_rotation(char *buf, size_t bufsize, unsigned int rotation) 621 { 622 /* 623 * According to doc only one DRM_MODE_ROTATE_ is allowed but this 624 * will print them all to visualize if the values are misused 625 */ 626 snprintf(buf, bufsize, 627 "%s%s%s%s%s%s(0x%08x)", 628 (rotation & DRM_MODE_ROTATE_0) ? "0 " : "", 629 (rotation & DRM_MODE_ROTATE_90) ? "90 " : "", 630 (rotation & DRM_MODE_ROTATE_180) ? "180 " : "", 631 (rotation & DRM_MODE_ROTATE_270) ? "270 " : "", 632 (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "", 633 (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "", 634 rotation); 635 } 636 637 static const char *plane_visibility(const struct intel_plane_state *plane_state) 638 { 639 if (plane_state->uapi.visible) 640 return "visible"; 641 642 if (plane_state->planar_slave) 643 return "planar-slave"; 644 645 return "hidden"; 646 } 647 648 static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane) 649 { 650 const struct intel_plane_state *plane_state = 651 to_intel_plane_state(plane->base.state); 652 const struct drm_framebuffer *fb = plane_state->uapi.fb; 653 struct drm_rect src, dst; 654 char rot_str[48]; 655 656 src = drm_plane_state_src(&plane_state->uapi); 657 dst = drm_plane_state_dest(&plane_state->uapi); 658 659 plane_rotation(rot_str, sizeof(rot_str), 660 plane_state->uapi.rotation); 661 662 seq_puts(m, "\t\tuapi: [FB:"); 663 if (fb) 664 seq_printf(m, "%d] %p4cc,0x%llx,%dx%d", fb->base.id, 665 &fb->format->format, fb->modifier, fb->width, 666 fb->height); 667 else 668 seq_puts(m, "0] n/a,0x0,0x0,"); 669 seq_printf(m, ", visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT 670 ", rotation=%s\n", plane_visibility(plane_state), 671 DRM_RECT_FP_ARG(&src), DRM_RECT_ARG(&dst), rot_str); 672 673 if (plane_state->planar_linked_plane) 674 seq_printf(m, "\t\tplanar: Linked to [PLANE:%d:%s] as a %s\n", 675 plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name, 676 plane_state->planar_slave ? "slave" : "master"); 677 } 678 679 static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane) 680 { 681 const struct intel_plane_state *plane_state = 682 to_intel_plane_state(plane->base.state); 683 const struct drm_framebuffer *fb = plane_state->hw.fb; 684 char rot_str[48]; 685 686 if (!fb) 687 return; 688 689 plane_rotation(rot_str, sizeof(rot_str), 690 plane_state->hw.rotation); 691 692 seq_printf(m, "\t\thw: [FB:%d] %p4cc,0x%llx,%dx%d, visible=%s, src=" 693 DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n", 694 fb->base.id, &fb->format->format, 695 fb->modifier, fb->width, fb->height, 696 str_yes_no(plane_state->uapi.visible), 697 DRM_RECT_FP_ARG(&plane_state->uapi.src), 698 DRM_RECT_ARG(&plane_state->uapi.dst), 699 rot_str); 700 } 701 702 static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc) 703 { 704 struct drm_i915_private *dev_priv = node_to_i915(m->private); 705 struct intel_plane *plane; 706 707 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 708 seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n", 709 plane->base.base.id, plane->base.name, 710 plane_type(plane->base.type)); 711 intel_plane_uapi_info(m, plane); 712 intel_plane_hw_info(m, plane); 713 } 714 } 715 716 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *crtc) 717 { 718 const struct intel_crtc_state *crtc_state = 719 to_intel_crtc_state(crtc->base.state); 720 int num_scalers = crtc->num_scalers; 721 int i; 722 723 /* Not all platformas have a scaler */ 724 if (num_scalers) { 725 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", 726 num_scalers, 727 crtc_state->scaler_state.scaler_users, 728 crtc_state->scaler_state.scaler_id); 729 730 for (i = 0; i < num_scalers; i++) { 731 const struct intel_scaler *sc = 732 &crtc_state->scaler_state.scalers[i]; 733 734 seq_printf(m, ", scalers[%d]: use=%s, mode=%x", 735 i, str_yes_no(sc->in_use), sc->mode); 736 } 737 seq_puts(m, "\n"); 738 } else { 739 seq_puts(m, "\tNo scalers available on this platform\n"); 740 } 741 } 742 743 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE) 744 static void crtc_updates_info(struct seq_file *m, 745 struct intel_crtc *crtc, 746 const char *hdr) 747 { 748 u64 count; 749 int row; 750 751 count = 0; 752 for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++) 753 count += crtc->debug.vbl.times[row]; 754 seq_printf(m, "%sUpdates: %llu\n", hdr, count); 755 if (!count) 756 return; 757 758 for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++) { 759 char columns[80] = " |"; 760 unsigned int x; 761 762 if (row & 1) { 763 const char *units; 764 765 if (row > 10) { 766 x = 1000000; 767 units = "ms"; 768 } else { 769 x = 1000; 770 units = "us"; 771 } 772 773 snprintf(columns, sizeof(columns), "%4ld%s |", 774 DIV_ROUND_CLOSEST(BIT(row + 9), x), units); 775 } 776 777 if (crtc->debug.vbl.times[row]) { 778 x = ilog2(crtc->debug.vbl.times[row]); 779 memset(columns + 8, '*', x); 780 columns[8 + x] = '\0'; 781 } 782 783 seq_printf(m, "%s%s\n", hdr, columns); 784 } 785 786 seq_printf(m, "%sMin update: %lluns\n", 787 hdr, crtc->debug.vbl.min); 788 seq_printf(m, "%sMax update: %lluns\n", 789 hdr, crtc->debug.vbl.max); 790 seq_printf(m, "%sAverage update: %lluns\n", 791 hdr, div64_u64(crtc->debug.vbl.sum, count)); 792 seq_printf(m, "%sOverruns > %uus: %u\n", 793 hdr, VBLANK_EVASION_TIME_US, crtc->debug.vbl.over); 794 } 795 796 static int crtc_updates_show(struct seq_file *m, void *data) 797 { 798 crtc_updates_info(m, m->private, ""); 799 return 0; 800 } 801 802 static int crtc_updates_open(struct inode *inode, struct file *file) 803 { 804 return single_open(file, crtc_updates_show, inode->i_private); 805 } 806 807 static ssize_t crtc_updates_write(struct file *file, 808 const char __user *ubuf, 809 size_t len, loff_t *offp) 810 { 811 struct seq_file *m = file->private_data; 812 struct intel_crtc *crtc = m->private; 813 814 /* May race with an update. Meh. */ 815 memset(&crtc->debug.vbl, 0, sizeof(crtc->debug.vbl)); 816 817 return len; 818 } 819 820 static const struct file_operations crtc_updates_fops = { 821 .owner = THIS_MODULE, 822 .open = crtc_updates_open, 823 .read = seq_read, 824 .llseek = seq_lseek, 825 .release = single_release, 826 .write = crtc_updates_write 827 }; 828 829 static void crtc_updates_add(struct drm_crtc *crtc) 830 { 831 debugfs_create_file("i915_update_info", 0644, crtc->debugfs_entry, 832 to_intel_crtc(crtc), &crtc_updates_fops); 833 } 834 835 #else 836 static void crtc_updates_info(struct seq_file *m, 837 struct intel_crtc *crtc, 838 const char *hdr) 839 { 840 } 841 842 static void crtc_updates_add(struct drm_crtc *crtc) 843 { 844 } 845 #endif 846 847 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) 848 { 849 struct drm_i915_private *dev_priv = node_to_i915(m->private); 850 const struct intel_crtc_state *crtc_state = 851 to_intel_crtc_state(crtc->base.state); 852 struct intel_encoder *encoder; 853 854 seq_printf(m, "[CRTC:%d:%s]:\n", 855 crtc->base.base.id, crtc->base.name); 856 857 seq_printf(m, "\tuapi: enable=%s, active=%s, mode=" DRM_MODE_FMT "\n", 858 str_yes_no(crtc_state->uapi.enable), 859 str_yes_no(crtc_state->uapi.active), 860 DRM_MODE_ARG(&crtc_state->uapi.mode)); 861 862 seq_printf(m, "\thw: enable=%s, active=%s\n", 863 str_yes_no(crtc_state->hw.enable), str_yes_no(crtc_state->hw.active)); 864 seq_printf(m, "\tadjusted_mode=" DRM_MODE_FMT "\n", 865 DRM_MODE_ARG(&crtc_state->hw.adjusted_mode)); 866 seq_printf(m, "\tpipe__mode=" DRM_MODE_FMT "\n", 867 DRM_MODE_ARG(&crtc_state->hw.pipe_mode)); 868 869 seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d\n", 870 DRM_RECT_ARG(&crtc_state->pipe_src), 871 str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); 872 873 intel_scaler_info(m, crtc); 874 875 if (crtc_state->bigjoiner_pipes) 876 seq_printf(m, "\tLinked to 0x%x pipes as a %s\n", 877 crtc_state->bigjoiner_pipes, 878 intel_crtc_is_bigjoiner_slave(crtc_state) ? "slave" : "master"); 879 880 for_each_intel_encoder_mask(&dev_priv->drm, encoder, 881 crtc_state->uapi.encoder_mask) 882 intel_encoder_info(m, crtc, encoder); 883 884 intel_plane_info(m, crtc); 885 886 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s\n", 887 str_yes_no(!crtc->cpu_fifo_underrun_disabled), 888 str_yes_no(!crtc->pch_fifo_underrun_disabled)); 889 890 crtc_updates_info(m, crtc, "\t"); 891 } 892 893 static int i915_display_info(struct seq_file *m, void *unused) 894 { 895 struct drm_i915_private *dev_priv = node_to_i915(m->private); 896 struct drm_device *dev = &dev_priv->drm; 897 struct intel_crtc *crtc; 898 struct drm_connector *connector; 899 struct drm_connector_list_iter conn_iter; 900 intel_wakeref_t wakeref; 901 902 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 903 904 drm_modeset_lock_all(dev); 905 906 seq_printf(m, "CRTC info\n"); 907 seq_printf(m, "---------\n"); 908 for_each_intel_crtc(dev, crtc) 909 intel_crtc_info(m, crtc); 910 911 seq_printf(m, "\n"); 912 seq_printf(m, "Connector info\n"); 913 seq_printf(m, "--------------\n"); 914 drm_connector_list_iter_begin(dev, &conn_iter); 915 drm_for_each_connector_iter(connector, &conn_iter) 916 intel_connector_info(m, connector); 917 drm_connector_list_iter_end(&conn_iter); 918 919 drm_modeset_unlock_all(dev); 920 921 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 922 923 return 0; 924 } 925 926 static int i915_shared_dplls_info(struct seq_file *m, void *unused) 927 { 928 struct drm_i915_private *dev_priv = node_to_i915(m->private); 929 struct drm_device *dev = &dev_priv->drm; 930 int i; 931 932 drm_modeset_lock_all(dev); 933 934 seq_printf(m, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n", 935 dev_priv->dpll.ref_clks.nssc, 936 dev_priv->dpll.ref_clks.ssc); 937 938 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { 939 struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i]; 940 941 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name, 942 pll->info->id); 943 seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n", 944 pll->state.pipe_mask, pll->active_mask, 945 str_yes_no(pll->on)); 946 seq_printf(m, " tracked hardware state:\n"); 947 seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); 948 seq_printf(m, " dpll_md: 0x%08x\n", 949 pll->state.hw_state.dpll_md); 950 seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); 951 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); 952 seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); 953 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); 954 seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); 955 seq_printf(m, " div0: 0x%08x\n", pll->state.hw_state.div0); 956 seq_printf(m, " mg_refclkin_ctl: 0x%08x\n", 957 pll->state.hw_state.mg_refclkin_ctl); 958 seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n", 959 pll->state.hw_state.mg_clktop2_coreclkctl1); 960 seq_printf(m, " mg_clktop2_hsclkctl: 0x%08x\n", 961 pll->state.hw_state.mg_clktop2_hsclkctl); 962 seq_printf(m, " mg_pll_div0: 0x%08x\n", 963 pll->state.hw_state.mg_pll_div0); 964 seq_printf(m, " mg_pll_div1: 0x%08x\n", 965 pll->state.hw_state.mg_pll_div1); 966 seq_printf(m, " mg_pll_lf: 0x%08x\n", 967 pll->state.hw_state.mg_pll_lf); 968 seq_printf(m, " mg_pll_frac_lock: 0x%08x\n", 969 pll->state.hw_state.mg_pll_frac_lock); 970 seq_printf(m, " mg_pll_ssc: 0x%08x\n", 971 pll->state.hw_state.mg_pll_ssc); 972 seq_printf(m, " mg_pll_bias: 0x%08x\n", 973 pll->state.hw_state.mg_pll_bias); 974 seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n", 975 pll->state.hw_state.mg_pll_tdc_coldst_bias); 976 } 977 drm_modeset_unlock_all(dev); 978 979 return 0; 980 } 981 982 static int i915_ipc_status_show(struct seq_file *m, void *data) 983 { 984 struct drm_i915_private *dev_priv = m->private; 985 986 seq_printf(m, "Isochronous Priority Control: %s\n", 987 str_yes_no(dev_priv->ipc_enabled)); 988 return 0; 989 } 990 991 static int i915_ipc_status_open(struct inode *inode, struct file *file) 992 { 993 struct drm_i915_private *dev_priv = inode->i_private; 994 995 if (!HAS_IPC(dev_priv)) 996 return -ENODEV; 997 998 return single_open(file, i915_ipc_status_show, dev_priv); 999 } 1000 1001 static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf, 1002 size_t len, loff_t *offp) 1003 { 1004 struct seq_file *m = file->private_data; 1005 struct drm_i915_private *dev_priv = m->private; 1006 intel_wakeref_t wakeref; 1007 bool enable; 1008 int ret; 1009 1010 ret = kstrtobool_from_user(ubuf, len, &enable); 1011 if (ret < 0) 1012 return ret; 1013 1014 with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { 1015 if (!dev_priv->ipc_enabled && enable) 1016 drm_info(&dev_priv->drm, 1017 "Enabling IPC: WM will be proper only after next commit\n"); 1018 dev_priv->ipc_enabled = enable; 1019 intel_enable_ipc(dev_priv); 1020 } 1021 1022 return len; 1023 } 1024 1025 static const struct file_operations i915_ipc_status_fops = { 1026 .owner = THIS_MODULE, 1027 .open = i915_ipc_status_open, 1028 .read = seq_read, 1029 .llseek = seq_lseek, 1030 .release = single_release, 1031 .write = i915_ipc_status_write 1032 }; 1033 1034 static int i915_ddb_info(struct seq_file *m, void *unused) 1035 { 1036 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1037 struct drm_device *dev = &dev_priv->drm; 1038 struct skl_ddb_entry *entry; 1039 struct intel_crtc *crtc; 1040 1041 if (DISPLAY_VER(dev_priv) < 9) 1042 return -ENODEV; 1043 1044 drm_modeset_lock_all(dev); 1045 1046 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); 1047 1048 for_each_intel_crtc(&dev_priv->drm, crtc) { 1049 struct intel_crtc_state *crtc_state = 1050 to_intel_crtc_state(crtc->base.state); 1051 enum pipe pipe = crtc->pipe; 1052 enum plane_id plane_id; 1053 1054 seq_printf(m, "Pipe %c\n", pipe_name(pipe)); 1055 1056 for_each_plane_id_on_crtc(crtc, plane_id) { 1057 entry = &crtc_state->wm.skl.plane_ddb[plane_id]; 1058 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1, 1059 entry->start, entry->end, 1060 skl_ddb_entry_size(entry)); 1061 } 1062 1063 entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 1064 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, 1065 entry->end, skl_ddb_entry_size(entry)); 1066 } 1067 1068 drm_modeset_unlock_all(dev); 1069 1070 return 0; 1071 } 1072 1073 static int i915_drrs_status(struct seq_file *m, void *unused) 1074 { 1075 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1076 struct drm_connector_list_iter conn_iter; 1077 struct intel_connector *connector; 1078 struct intel_crtc *crtc; 1079 1080 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 1081 for_each_intel_connector_iter(connector, &conn_iter) { 1082 seq_printf(m, "[CONNECTOR:%d:%s] DRRS type: %s\n", 1083 connector->base.base.id, connector->base.name, 1084 intel_drrs_type_str(intel_panel_drrs_type(connector))); 1085 } 1086 drm_connector_list_iter_end(&conn_iter); 1087 1088 seq_puts(m, "\n"); 1089 1090 for_each_intel_crtc(&dev_priv->drm, crtc) { 1091 const struct intel_crtc_state *crtc_state = 1092 to_intel_crtc_state(crtc->base.state); 1093 1094 seq_printf(m, "[CRTC:%d:%s]:\n", 1095 crtc->base.base.id, crtc->base.name); 1096 1097 mutex_lock(&crtc->drrs.mutex); 1098 1099 /* DRRS Supported */ 1100 seq_printf(m, "\tDRRS Enabled: %s\n", 1101 str_yes_no(crtc_state->has_drrs)); 1102 1103 seq_printf(m, "\tDRRS Active: %s\n", 1104 str_yes_no(intel_drrs_is_active(crtc))); 1105 1106 seq_printf(m, "\tBusy_frontbuffer_bits: 0x%X\n", 1107 crtc->drrs.busy_frontbuffer_bits); 1108 1109 seq_printf(m, "\tDRRS refresh rate: %s\n", 1110 crtc->drrs.refresh_rate == DRRS_REFRESH_RATE_LOW ? 1111 "low" : "high"); 1112 1113 mutex_unlock(&crtc->drrs.mutex); 1114 } 1115 1116 return 0; 1117 } 1118 1119 static bool 1120 intel_lpsp_power_well_enabled(struct drm_i915_private *i915, 1121 enum i915_power_well_id power_well_id) 1122 { 1123 intel_wakeref_t wakeref; 1124 bool is_enabled; 1125 1126 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 1127 is_enabled = intel_display_power_well_is_enabled(i915, 1128 power_well_id); 1129 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1130 1131 return is_enabled; 1132 } 1133 1134 static int i915_lpsp_status(struct seq_file *m, void *unused) 1135 { 1136 struct drm_i915_private *i915 = node_to_i915(m->private); 1137 bool lpsp_enabled = false; 1138 1139 if (DISPLAY_VER(i915) >= 13 || IS_DISPLAY_VER(i915, 9, 10)) { 1140 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, SKL_DISP_PW_2); 1141 } else if (IS_DISPLAY_VER(i915, 11, 12)) { 1142 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3); 1143 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 1144 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, HSW_DISP_PW_GLOBAL); 1145 } else { 1146 seq_puts(m, "LPSP: not supported\n"); 1147 return 0; 1148 } 1149 1150 seq_printf(m, "LPSP: %s\n", str_enabled_disabled(lpsp_enabled)); 1151 1152 return 0; 1153 } 1154 1155 static int i915_dp_mst_info(struct seq_file *m, void *unused) 1156 { 1157 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1158 struct drm_device *dev = &dev_priv->drm; 1159 struct intel_encoder *intel_encoder; 1160 struct intel_digital_port *dig_port; 1161 struct drm_connector *connector; 1162 struct drm_connector_list_iter conn_iter; 1163 1164 drm_connector_list_iter_begin(dev, &conn_iter); 1165 drm_for_each_connector_iter(connector, &conn_iter) { 1166 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 1167 continue; 1168 1169 intel_encoder = intel_attached_encoder(to_intel_connector(connector)); 1170 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) 1171 continue; 1172 1173 dig_port = enc_to_dig_port(intel_encoder); 1174 if (!intel_dp_mst_source_support(&dig_port->dp)) 1175 continue; 1176 1177 seq_printf(m, "MST Source Port [ENCODER:%d:%s]\n", 1178 dig_port->base.base.base.id, 1179 dig_port->base.base.name); 1180 drm_dp_mst_dump_topology(m, &dig_port->dp.mst_mgr); 1181 } 1182 drm_connector_list_iter_end(&conn_iter); 1183 1184 return 0; 1185 } 1186 1187 static ssize_t i915_displayport_test_active_write(struct file *file, 1188 const char __user *ubuf, 1189 size_t len, loff_t *offp) 1190 { 1191 char *input_buffer; 1192 int status = 0; 1193 struct drm_device *dev; 1194 struct drm_connector *connector; 1195 struct drm_connector_list_iter conn_iter; 1196 struct intel_dp *intel_dp; 1197 int val = 0; 1198 1199 dev = ((struct seq_file *)file->private_data)->private; 1200 1201 if (len == 0) 1202 return 0; 1203 1204 input_buffer = memdup_user_nul(ubuf, len); 1205 if (IS_ERR(input_buffer)) 1206 return PTR_ERR(input_buffer); 1207 1208 drm_dbg(&to_i915(dev)->drm, 1209 "Copied %d bytes from user\n", (unsigned int)len); 1210 1211 drm_connector_list_iter_begin(dev, &conn_iter); 1212 drm_for_each_connector_iter(connector, &conn_iter) { 1213 struct intel_encoder *encoder; 1214 1215 if (connector->connector_type != 1216 DRM_MODE_CONNECTOR_DisplayPort) 1217 continue; 1218 1219 encoder = to_intel_encoder(connector->encoder); 1220 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 1221 continue; 1222 1223 if (encoder && connector->status == connector_status_connected) { 1224 intel_dp = enc_to_intel_dp(encoder); 1225 status = kstrtoint(input_buffer, 10, &val); 1226 if (status < 0) 1227 break; 1228 drm_dbg(&to_i915(dev)->drm, 1229 "Got %d for test active\n", val); 1230 /* To prevent erroneous activation of the compliance 1231 * testing code, only accept an actual value of 1 here 1232 */ 1233 if (val == 1) 1234 intel_dp->compliance.test_active = true; 1235 else 1236 intel_dp->compliance.test_active = false; 1237 } 1238 } 1239 drm_connector_list_iter_end(&conn_iter); 1240 kfree(input_buffer); 1241 if (status < 0) 1242 return status; 1243 1244 *offp += len; 1245 return len; 1246 } 1247 1248 static int i915_displayport_test_active_show(struct seq_file *m, void *data) 1249 { 1250 struct drm_i915_private *dev_priv = m->private; 1251 struct drm_device *dev = &dev_priv->drm; 1252 struct drm_connector *connector; 1253 struct drm_connector_list_iter conn_iter; 1254 struct intel_dp *intel_dp; 1255 1256 drm_connector_list_iter_begin(dev, &conn_iter); 1257 drm_for_each_connector_iter(connector, &conn_iter) { 1258 struct intel_encoder *encoder; 1259 1260 if (connector->connector_type != 1261 DRM_MODE_CONNECTOR_DisplayPort) 1262 continue; 1263 1264 encoder = to_intel_encoder(connector->encoder); 1265 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 1266 continue; 1267 1268 if (encoder && connector->status == connector_status_connected) { 1269 intel_dp = enc_to_intel_dp(encoder); 1270 if (intel_dp->compliance.test_active) 1271 seq_puts(m, "1"); 1272 else 1273 seq_puts(m, "0"); 1274 } else 1275 seq_puts(m, "0"); 1276 } 1277 drm_connector_list_iter_end(&conn_iter); 1278 1279 return 0; 1280 } 1281 1282 static int i915_displayport_test_active_open(struct inode *inode, 1283 struct file *file) 1284 { 1285 return single_open(file, i915_displayport_test_active_show, 1286 inode->i_private); 1287 } 1288 1289 static const struct file_operations i915_displayport_test_active_fops = { 1290 .owner = THIS_MODULE, 1291 .open = i915_displayport_test_active_open, 1292 .read = seq_read, 1293 .llseek = seq_lseek, 1294 .release = single_release, 1295 .write = i915_displayport_test_active_write 1296 }; 1297 1298 static int i915_displayport_test_data_show(struct seq_file *m, void *data) 1299 { 1300 struct drm_i915_private *dev_priv = m->private; 1301 struct drm_device *dev = &dev_priv->drm; 1302 struct drm_connector *connector; 1303 struct drm_connector_list_iter conn_iter; 1304 struct intel_dp *intel_dp; 1305 1306 drm_connector_list_iter_begin(dev, &conn_iter); 1307 drm_for_each_connector_iter(connector, &conn_iter) { 1308 struct intel_encoder *encoder; 1309 1310 if (connector->connector_type != 1311 DRM_MODE_CONNECTOR_DisplayPort) 1312 continue; 1313 1314 encoder = to_intel_encoder(connector->encoder); 1315 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 1316 continue; 1317 1318 if (encoder && connector->status == connector_status_connected) { 1319 intel_dp = enc_to_intel_dp(encoder); 1320 if (intel_dp->compliance.test_type == 1321 DP_TEST_LINK_EDID_READ) 1322 seq_printf(m, "%lx", 1323 intel_dp->compliance.test_data.edid); 1324 else if (intel_dp->compliance.test_type == 1325 DP_TEST_LINK_VIDEO_PATTERN) { 1326 seq_printf(m, "hdisplay: %d\n", 1327 intel_dp->compliance.test_data.hdisplay); 1328 seq_printf(m, "vdisplay: %d\n", 1329 intel_dp->compliance.test_data.vdisplay); 1330 seq_printf(m, "bpc: %u\n", 1331 intel_dp->compliance.test_data.bpc); 1332 } else if (intel_dp->compliance.test_type == 1333 DP_TEST_LINK_PHY_TEST_PATTERN) { 1334 seq_printf(m, "pattern: %d\n", 1335 intel_dp->compliance.test_data.phytest.phy_pattern); 1336 seq_printf(m, "Number of lanes: %d\n", 1337 intel_dp->compliance.test_data.phytest.num_lanes); 1338 seq_printf(m, "Link Rate: %d\n", 1339 intel_dp->compliance.test_data.phytest.link_rate); 1340 seq_printf(m, "level: %02x\n", 1341 intel_dp->train_set[0]); 1342 } 1343 } else 1344 seq_puts(m, "0"); 1345 } 1346 drm_connector_list_iter_end(&conn_iter); 1347 1348 return 0; 1349 } 1350 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_data); 1351 1352 static int i915_displayport_test_type_show(struct seq_file *m, void *data) 1353 { 1354 struct drm_i915_private *dev_priv = m->private; 1355 struct drm_device *dev = &dev_priv->drm; 1356 struct drm_connector *connector; 1357 struct drm_connector_list_iter conn_iter; 1358 struct intel_dp *intel_dp; 1359 1360 drm_connector_list_iter_begin(dev, &conn_iter); 1361 drm_for_each_connector_iter(connector, &conn_iter) { 1362 struct intel_encoder *encoder; 1363 1364 if (connector->connector_type != 1365 DRM_MODE_CONNECTOR_DisplayPort) 1366 continue; 1367 1368 encoder = to_intel_encoder(connector->encoder); 1369 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 1370 continue; 1371 1372 if (encoder && connector->status == connector_status_connected) { 1373 intel_dp = enc_to_intel_dp(encoder); 1374 seq_printf(m, "%02lx\n", intel_dp->compliance.test_type); 1375 } else 1376 seq_puts(m, "0"); 1377 } 1378 drm_connector_list_iter_end(&conn_iter); 1379 1380 return 0; 1381 } 1382 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type); 1383 1384 static void wm_latency_show(struct seq_file *m, const u16 wm[8]) 1385 { 1386 struct drm_i915_private *dev_priv = m->private; 1387 struct drm_device *dev = &dev_priv->drm; 1388 int level; 1389 int num_levels; 1390 1391 if (IS_CHERRYVIEW(dev_priv)) 1392 num_levels = 3; 1393 else if (IS_VALLEYVIEW(dev_priv)) 1394 num_levels = 1; 1395 else if (IS_G4X(dev_priv)) 1396 num_levels = 3; 1397 else 1398 num_levels = ilk_wm_max_level(dev_priv) + 1; 1399 1400 drm_modeset_lock_all(dev); 1401 1402 for (level = 0; level < num_levels; level++) { 1403 unsigned int latency = wm[level]; 1404 1405 /* 1406 * - WM1+ latency values in 0.5us units 1407 * - latencies are in us on gen9/vlv/chv 1408 */ 1409 if (DISPLAY_VER(dev_priv) >= 9 || 1410 IS_VALLEYVIEW(dev_priv) || 1411 IS_CHERRYVIEW(dev_priv) || 1412 IS_G4X(dev_priv)) 1413 latency *= 10; 1414 else if (level > 0) 1415 latency *= 5; 1416 1417 seq_printf(m, "WM%d %u (%u.%u usec)\n", 1418 level, wm[level], latency / 10, latency % 10); 1419 } 1420 1421 drm_modeset_unlock_all(dev); 1422 } 1423 1424 static int pri_wm_latency_show(struct seq_file *m, void *data) 1425 { 1426 struct drm_i915_private *dev_priv = m->private; 1427 const u16 *latencies; 1428 1429 if (DISPLAY_VER(dev_priv) >= 9) 1430 latencies = dev_priv->wm.skl_latency; 1431 else 1432 latencies = dev_priv->wm.pri_latency; 1433 1434 wm_latency_show(m, latencies); 1435 1436 return 0; 1437 } 1438 1439 static int spr_wm_latency_show(struct seq_file *m, void *data) 1440 { 1441 struct drm_i915_private *dev_priv = m->private; 1442 const u16 *latencies; 1443 1444 if (DISPLAY_VER(dev_priv) >= 9) 1445 latencies = dev_priv->wm.skl_latency; 1446 else 1447 latencies = dev_priv->wm.spr_latency; 1448 1449 wm_latency_show(m, latencies); 1450 1451 return 0; 1452 } 1453 1454 static int cur_wm_latency_show(struct seq_file *m, void *data) 1455 { 1456 struct drm_i915_private *dev_priv = m->private; 1457 const u16 *latencies; 1458 1459 if (DISPLAY_VER(dev_priv) >= 9) 1460 latencies = dev_priv->wm.skl_latency; 1461 else 1462 latencies = dev_priv->wm.cur_latency; 1463 1464 wm_latency_show(m, latencies); 1465 1466 return 0; 1467 } 1468 1469 static int pri_wm_latency_open(struct inode *inode, struct file *file) 1470 { 1471 struct drm_i915_private *dev_priv = inode->i_private; 1472 1473 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) 1474 return -ENODEV; 1475 1476 return single_open(file, pri_wm_latency_show, dev_priv); 1477 } 1478 1479 static int spr_wm_latency_open(struct inode *inode, struct file *file) 1480 { 1481 struct drm_i915_private *dev_priv = inode->i_private; 1482 1483 if (HAS_GMCH(dev_priv)) 1484 return -ENODEV; 1485 1486 return single_open(file, spr_wm_latency_show, dev_priv); 1487 } 1488 1489 static int cur_wm_latency_open(struct inode *inode, struct file *file) 1490 { 1491 struct drm_i915_private *dev_priv = inode->i_private; 1492 1493 if (HAS_GMCH(dev_priv)) 1494 return -ENODEV; 1495 1496 return single_open(file, cur_wm_latency_show, dev_priv); 1497 } 1498 1499 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, 1500 size_t len, loff_t *offp, u16 wm[8]) 1501 { 1502 struct seq_file *m = file->private_data; 1503 struct drm_i915_private *dev_priv = m->private; 1504 struct drm_device *dev = &dev_priv->drm; 1505 u16 new[8] = { 0 }; 1506 int num_levels; 1507 int level; 1508 int ret; 1509 char tmp[32]; 1510 1511 if (IS_CHERRYVIEW(dev_priv)) 1512 num_levels = 3; 1513 else if (IS_VALLEYVIEW(dev_priv)) 1514 num_levels = 1; 1515 else if (IS_G4X(dev_priv)) 1516 num_levels = 3; 1517 else 1518 num_levels = ilk_wm_max_level(dev_priv) + 1; 1519 1520 if (len >= sizeof(tmp)) 1521 return -EINVAL; 1522 1523 if (copy_from_user(tmp, ubuf, len)) 1524 return -EFAULT; 1525 1526 tmp[len] = '\0'; 1527 1528 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", 1529 &new[0], &new[1], &new[2], &new[3], 1530 &new[4], &new[5], &new[6], &new[7]); 1531 if (ret != num_levels) 1532 return -EINVAL; 1533 1534 drm_modeset_lock_all(dev); 1535 1536 for (level = 0; level < num_levels; level++) 1537 wm[level] = new[level]; 1538 1539 drm_modeset_unlock_all(dev); 1540 1541 return len; 1542 } 1543 1544 1545 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, 1546 size_t len, loff_t *offp) 1547 { 1548 struct seq_file *m = file->private_data; 1549 struct drm_i915_private *dev_priv = m->private; 1550 u16 *latencies; 1551 1552 if (DISPLAY_VER(dev_priv) >= 9) 1553 latencies = dev_priv->wm.skl_latency; 1554 else 1555 latencies = dev_priv->wm.pri_latency; 1556 1557 return wm_latency_write(file, ubuf, len, offp, latencies); 1558 } 1559 1560 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, 1561 size_t len, loff_t *offp) 1562 { 1563 struct seq_file *m = file->private_data; 1564 struct drm_i915_private *dev_priv = m->private; 1565 u16 *latencies; 1566 1567 if (DISPLAY_VER(dev_priv) >= 9) 1568 latencies = dev_priv->wm.skl_latency; 1569 else 1570 latencies = dev_priv->wm.spr_latency; 1571 1572 return wm_latency_write(file, ubuf, len, offp, latencies); 1573 } 1574 1575 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, 1576 size_t len, loff_t *offp) 1577 { 1578 struct seq_file *m = file->private_data; 1579 struct drm_i915_private *dev_priv = m->private; 1580 u16 *latencies; 1581 1582 if (DISPLAY_VER(dev_priv) >= 9) 1583 latencies = dev_priv->wm.skl_latency; 1584 else 1585 latencies = dev_priv->wm.cur_latency; 1586 1587 return wm_latency_write(file, ubuf, len, offp, latencies); 1588 } 1589 1590 static const struct file_operations i915_pri_wm_latency_fops = { 1591 .owner = THIS_MODULE, 1592 .open = pri_wm_latency_open, 1593 .read = seq_read, 1594 .llseek = seq_lseek, 1595 .release = single_release, 1596 .write = pri_wm_latency_write 1597 }; 1598 1599 static const struct file_operations i915_spr_wm_latency_fops = { 1600 .owner = THIS_MODULE, 1601 .open = spr_wm_latency_open, 1602 .read = seq_read, 1603 .llseek = seq_lseek, 1604 .release = single_release, 1605 .write = spr_wm_latency_write 1606 }; 1607 1608 static const struct file_operations i915_cur_wm_latency_fops = { 1609 .owner = THIS_MODULE, 1610 .open = cur_wm_latency_open, 1611 .read = seq_read, 1612 .llseek = seq_lseek, 1613 .release = single_release, 1614 .write = cur_wm_latency_write 1615 }; 1616 1617 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) 1618 { 1619 struct drm_i915_private *dev_priv = m->private; 1620 struct i915_hotplug *hotplug = &dev_priv->hotplug; 1621 1622 /* Synchronize with everything first in case there's been an HPD 1623 * storm, but we haven't finished handling it in the kernel yet 1624 */ 1625 intel_synchronize_irq(dev_priv); 1626 flush_work(&dev_priv->hotplug.dig_port_work); 1627 flush_delayed_work(&dev_priv->hotplug.hotplug_work); 1628 1629 seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); 1630 seq_printf(m, "Detected: %s\n", 1631 str_yes_no(delayed_work_pending(&hotplug->reenable_work))); 1632 1633 return 0; 1634 } 1635 1636 static ssize_t i915_hpd_storm_ctl_write(struct file *file, 1637 const char __user *ubuf, size_t len, 1638 loff_t *offp) 1639 { 1640 struct seq_file *m = file->private_data; 1641 struct drm_i915_private *dev_priv = m->private; 1642 struct i915_hotplug *hotplug = &dev_priv->hotplug; 1643 unsigned int new_threshold; 1644 int i; 1645 char *newline; 1646 char tmp[16]; 1647 1648 if (len >= sizeof(tmp)) 1649 return -EINVAL; 1650 1651 if (copy_from_user(tmp, ubuf, len)) 1652 return -EFAULT; 1653 1654 tmp[len] = '\0'; 1655 1656 /* Strip newline, if any */ 1657 newline = strchr(tmp, '\n'); 1658 if (newline) 1659 *newline = '\0'; 1660 1661 if (strcmp(tmp, "reset") == 0) 1662 new_threshold = HPD_STORM_DEFAULT_THRESHOLD; 1663 else if (kstrtouint(tmp, 10, &new_threshold) != 0) 1664 return -EINVAL; 1665 1666 if (new_threshold > 0) 1667 drm_dbg_kms(&dev_priv->drm, 1668 "Setting HPD storm detection threshold to %d\n", 1669 new_threshold); 1670 else 1671 drm_dbg_kms(&dev_priv->drm, "Disabling HPD storm detection\n"); 1672 1673 spin_lock_irq(&dev_priv->irq_lock); 1674 hotplug->hpd_storm_threshold = new_threshold; 1675 /* Reset the HPD storm stats so we don't accidentally trigger a storm */ 1676 for_each_hpd_pin(i) 1677 hotplug->stats[i].count = 0; 1678 spin_unlock_irq(&dev_priv->irq_lock); 1679 1680 /* Re-enable hpd immediately if we were in an irq storm */ 1681 flush_delayed_work(&dev_priv->hotplug.reenable_work); 1682 1683 return len; 1684 } 1685 1686 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) 1687 { 1688 return single_open(file, i915_hpd_storm_ctl_show, inode->i_private); 1689 } 1690 1691 static const struct file_operations i915_hpd_storm_ctl_fops = { 1692 .owner = THIS_MODULE, 1693 .open = i915_hpd_storm_ctl_open, 1694 .read = seq_read, 1695 .llseek = seq_lseek, 1696 .release = single_release, 1697 .write = i915_hpd_storm_ctl_write 1698 }; 1699 1700 static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data) 1701 { 1702 struct drm_i915_private *dev_priv = m->private; 1703 1704 seq_printf(m, "Enabled: %s\n", 1705 str_yes_no(dev_priv->hotplug.hpd_short_storm_enabled)); 1706 1707 return 0; 1708 } 1709 1710 static int 1711 i915_hpd_short_storm_ctl_open(struct inode *inode, struct file *file) 1712 { 1713 return single_open(file, i915_hpd_short_storm_ctl_show, 1714 inode->i_private); 1715 } 1716 1717 static ssize_t i915_hpd_short_storm_ctl_write(struct file *file, 1718 const char __user *ubuf, 1719 size_t len, loff_t *offp) 1720 { 1721 struct seq_file *m = file->private_data; 1722 struct drm_i915_private *dev_priv = m->private; 1723 struct i915_hotplug *hotplug = &dev_priv->hotplug; 1724 char *newline; 1725 char tmp[16]; 1726 int i; 1727 bool new_state; 1728 1729 if (len >= sizeof(tmp)) 1730 return -EINVAL; 1731 1732 if (copy_from_user(tmp, ubuf, len)) 1733 return -EFAULT; 1734 1735 tmp[len] = '\0'; 1736 1737 /* Strip newline, if any */ 1738 newline = strchr(tmp, '\n'); 1739 if (newline) 1740 *newline = '\0'; 1741 1742 /* Reset to the "default" state for this system */ 1743 if (strcmp(tmp, "reset") == 0) 1744 new_state = !HAS_DP_MST(dev_priv); 1745 else if (kstrtobool(tmp, &new_state) != 0) 1746 return -EINVAL; 1747 1748 drm_dbg_kms(&dev_priv->drm, "%sabling HPD short storm detection\n", 1749 new_state ? "En" : "Dis"); 1750 1751 spin_lock_irq(&dev_priv->irq_lock); 1752 hotplug->hpd_short_storm_enabled = new_state; 1753 /* Reset the HPD storm stats so we don't accidentally trigger a storm */ 1754 for_each_hpd_pin(i) 1755 hotplug->stats[i].count = 0; 1756 spin_unlock_irq(&dev_priv->irq_lock); 1757 1758 /* Re-enable hpd immediately if we were in an irq storm */ 1759 flush_delayed_work(&dev_priv->hotplug.reenable_work); 1760 1761 return len; 1762 } 1763 1764 static const struct file_operations i915_hpd_short_storm_ctl_fops = { 1765 .owner = THIS_MODULE, 1766 .open = i915_hpd_short_storm_ctl_open, 1767 .read = seq_read, 1768 .llseek = seq_lseek, 1769 .release = single_release, 1770 .write = i915_hpd_short_storm_ctl_write, 1771 }; 1772 1773 static int i915_drrs_ctl_set(void *data, u64 val) 1774 { 1775 struct drm_i915_private *dev_priv = data; 1776 struct drm_device *dev = &dev_priv->drm; 1777 struct intel_crtc *crtc; 1778 1779 for_each_intel_crtc(dev, crtc) { 1780 struct intel_crtc_state *crtc_state; 1781 struct drm_crtc_commit *commit; 1782 int ret; 1783 1784 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); 1785 if (ret) 1786 return ret; 1787 1788 crtc_state = to_intel_crtc_state(crtc->base.state); 1789 1790 if (!crtc_state->hw.active || 1791 !crtc_state->has_drrs) 1792 goto out; 1793 1794 commit = crtc_state->uapi.commit; 1795 if (commit) { 1796 ret = wait_for_completion_interruptible(&commit->hw_done); 1797 if (ret) 1798 goto out; 1799 } 1800 1801 drm_dbg(&dev_priv->drm, 1802 "Manually %sactivating DRRS\n", val ? "" : "de"); 1803 1804 if (val) 1805 intel_drrs_activate(crtc_state); 1806 else 1807 intel_drrs_deactivate(crtc_state); 1808 1809 out: 1810 drm_modeset_unlock(&crtc->base.mutex); 1811 if (ret) 1812 return ret; 1813 } 1814 1815 return 0; 1816 } 1817 1818 DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n"); 1819 1820 static ssize_t 1821 i915_fifo_underrun_reset_write(struct file *filp, 1822 const char __user *ubuf, 1823 size_t cnt, loff_t *ppos) 1824 { 1825 struct drm_i915_private *dev_priv = filp->private_data; 1826 struct intel_crtc *crtc; 1827 struct drm_device *dev = &dev_priv->drm; 1828 int ret; 1829 bool reset; 1830 1831 ret = kstrtobool_from_user(ubuf, cnt, &reset); 1832 if (ret) 1833 return ret; 1834 1835 if (!reset) 1836 return cnt; 1837 1838 for_each_intel_crtc(dev, crtc) { 1839 struct drm_crtc_commit *commit; 1840 struct intel_crtc_state *crtc_state; 1841 1842 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); 1843 if (ret) 1844 return ret; 1845 1846 crtc_state = to_intel_crtc_state(crtc->base.state); 1847 commit = crtc_state->uapi.commit; 1848 if (commit) { 1849 ret = wait_for_completion_interruptible(&commit->hw_done); 1850 if (!ret) 1851 ret = wait_for_completion_interruptible(&commit->flip_done); 1852 } 1853 1854 if (!ret && crtc_state->hw.active) { 1855 drm_dbg_kms(&dev_priv->drm, 1856 "Re-arming FIFO underruns on pipe %c\n", 1857 pipe_name(crtc->pipe)); 1858 1859 intel_crtc_arm_fifo_underrun(crtc, crtc_state); 1860 } 1861 1862 drm_modeset_unlock(&crtc->base.mutex); 1863 1864 if (ret) 1865 return ret; 1866 } 1867 1868 intel_fbc_reset_underrun(dev_priv); 1869 1870 return cnt; 1871 } 1872 1873 static const struct file_operations i915_fifo_underrun_reset_ops = { 1874 .owner = THIS_MODULE, 1875 .open = simple_open, 1876 .write = i915_fifo_underrun_reset_write, 1877 .llseek = default_llseek, 1878 }; 1879 1880 static const struct drm_info_list intel_display_debugfs_list[] = { 1881 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, 1882 {"i915_ips_status", i915_ips_status, 0}, 1883 {"i915_sr_status", i915_sr_status, 0}, 1884 {"i915_opregion", i915_opregion, 0}, 1885 {"i915_vbt", i915_vbt, 0}, 1886 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, 1887 {"i915_edp_psr_status", i915_edp_psr_status, 0}, 1888 {"i915_power_domain_info", i915_power_domain_info, 0}, 1889 {"i915_display_info", i915_display_info, 0}, 1890 {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, 1891 {"i915_dp_mst_info", i915_dp_mst_info, 0}, 1892 {"i915_ddb_info", i915_ddb_info, 0}, 1893 {"i915_drrs_status", i915_drrs_status, 0}, 1894 {"i915_lpsp_status", i915_lpsp_status, 0}, 1895 }; 1896 1897 static const struct { 1898 const char *name; 1899 const struct file_operations *fops; 1900 } intel_display_debugfs_files[] = { 1901 {"i915_fifo_underrun_reset", &i915_fifo_underrun_reset_ops}, 1902 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, 1903 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, 1904 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, 1905 {"i915_dp_test_data", &i915_displayport_test_data_fops}, 1906 {"i915_dp_test_type", &i915_displayport_test_type_fops}, 1907 {"i915_dp_test_active", &i915_displayport_test_active_fops}, 1908 {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}, 1909 {"i915_hpd_short_storm_ctl", &i915_hpd_short_storm_ctl_fops}, 1910 {"i915_ipc_status", &i915_ipc_status_fops}, 1911 {"i915_drrs_ctl", &i915_drrs_ctl_fops}, 1912 {"i915_edp_psr_debug", &i915_edp_psr_debug_fops}, 1913 }; 1914 1915 void intel_display_debugfs_register(struct drm_i915_private *i915) 1916 { 1917 struct drm_minor *minor = i915->drm.primary; 1918 int i; 1919 1920 for (i = 0; i < ARRAY_SIZE(intel_display_debugfs_files); i++) { 1921 debugfs_create_file(intel_display_debugfs_files[i].name, 1922 S_IRUGO | S_IWUSR, 1923 minor->debugfs_root, 1924 to_i915(minor->dev), 1925 intel_display_debugfs_files[i].fops); 1926 } 1927 1928 drm_debugfs_create_files(intel_display_debugfs_list, 1929 ARRAY_SIZE(intel_display_debugfs_list), 1930 minor->debugfs_root, minor); 1931 1932 intel_dmc_debugfs_register(i915); 1933 intel_fbc_debugfs_register(i915); 1934 } 1935 1936 static int i915_panel_show(struct seq_file *m, void *data) 1937 { 1938 struct drm_connector *connector = m->private; 1939 struct intel_dp *intel_dp = 1940 intel_attached_dp(to_intel_connector(connector)); 1941 1942 if (connector->status != connector_status_connected) 1943 return -ENODEV; 1944 1945 seq_printf(m, "Panel power up delay: %d\n", 1946 intel_dp->pps.panel_power_up_delay); 1947 seq_printf(m, "Panel power down delay: %d\n", 1948 intel_dp->pps.panel_power_down_delay); 1949 seq_printf(m, "Backlight on delay: %d\n", 1950 intel_dp->pps.backlight_on_delay); 1951 seq_printf(m, "Backlight off delay: %d\n", 1952 intel_dp->pps.backlight_off_delay); 1953 1954 return 0; 1955 } 1956 DEFINE_SHOW_ATTRIBUTE(i915_panel); 1957 1958 static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data) 1959 { 1960 struct drm_connector *connector = m->private; 1961 struct drm_i915_private *i915 = to_i915(connector->dev); 1962 struct intel_connector *intel_connector = to_intel_connector(connector); 1963 int ret; 1964 1965 ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1966 if (ret) 1967 return ret; 1968 1969 if (!connector->encoder || connector->status != connector_status_connected) { 1970 ret = -ENODEV; 1971 goto out; 1972 } 1973 1974 seq_printf(m, "%s:%d HDCP version: ", connector->name, 1975 connector->base.id); 1976 intel_hdcp_info(m, intel_connector); 1977 1978 out: 1979 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1980 1981 return ret; 1982 } 1983 DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability); 1984 1985 static int i915_psr_status_show(struct seq_file *m, void *data) 1986 { 1987 struct drm_connector *connector = m->private; 1988 struct intel_dp *intel_dp = 1989 intel_attached_dp(to_intel_connector(connector)); 1990 1991 return intel_psr_status(m, intel_dp); 1992 } 1993 DEFINE_SHOW_ATTRIBUTE(i915_psr_status); 1994 1995 static int i915_lpsp_capability_show(struct seq_file *m, void *data) 1996 { 1997 struct drm_connector *connector = m->private; 1998 struct drm_i915_private *i915 = to_i915(connector->dev); 1999 struct intel_encoder *encoder; 2000 bool lpsp_capable = false; 2001 2002 encoder = intel_attached_encoder(to_intel_connector(connector)); 2003 if (!encoder) 2004 return -ENODEV; 2005 2006 if (connector->status != connector_status_connected) 2007 return -ENODEV; 2008 2009 if (DISPLAY_VER(i915) >= 13) 2010 lpsp_capable = encoder->port <= PORT_B; 2011 else if (DISPLAY_VER(i915) >= 12) 2012 /* 2013 * Actually TGL can drive LPSP on port till DDI_C 2014 * but there is no physical connected DDI_C on TGL sku's, 2015 * even driver is not initilizing DDI_C port for gen12. 2016 */ 2017 lpsp_capable = encoder->port <= PORT_B; 2018 else if (DISPLAY_VER(i915) == 11) 2019 lpsp_capable = (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 2020 connector->connector_type == DRM_MODE_CONNECTOR_eDP); 2021 else if (IS_DISPLAY_VER(i915, 9, 10)) 2022 lpsp_capable = (encoder->port == PORT_A && 2023 (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 2024 connector->connector_type == DRM_MODE_CONNECTOR_eDP || 2025 connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)); 2026 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 2027 lpsp_capable = connector->connector_type == DRM_MODE_CONNECTOR_eDP; 2028 2029 seq_printf(m, "LPSP: %s\n", lpsp_capable ? "capable" : "incapable"); 2030 2031 return 0; 2032 } 2033 DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability); 2034 2035 static int i915_dsc_fec_support_show(struct seq_file *m, void *data) 2036 { 2037 struct drm_connector *connector = m->private; 2038 struct drm_device *dev = connector->dev; 2039 struct drm_crtc *crtc; 2040 struct intel_dp *intel_dp; 2041 struct drm_modeset_acquire_ctx ctx; 2042 struct intel_crtc_state *crtc_state = NULL; 2043 int ret = 0; 2044 bool try_again = false; 2045 2046 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 2047 2048 do { 2049 try_again = false; 2050 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, 2051 &ctx); 2052 if (ret) { 2053 if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) { 2054 try_again = true; 2055 continue; 2056 } 2057 break; 2058 } 2059 crtc = connector->state->crtc; 2060 if (connector->status != connector_status_connected || !crtc) { 2061 ret = -ENODEV; 2062 break; 2063 } 2064 ret = drm_modeset_lock(&crtc->mutex, &ctx); 2065 if (ret == -EDEADLK) { 2066 ret = drm_modeset_backoff(&ctx); 2067 if (!ret) { 2068 try_again = true; 2069 continue; 2070 } 2071 break; 2072 } else if (ret) { 2073 break; 2074 } 2075 intel_dp = intel_attached_dp(to_intel_connector(connector)); 2076 crtc_state = to_intel_crtc_state(crtc->state); 2077 seq_printf(m, "DSC_Enabled: %s\n", 2078 str_yes_no(crtc_state->dsc.compression_enable)); 2079 seq_printf(m, "DSC_Sink_Support: %s\n", 2080 str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))); 2081 seq_printf(m, "Force_DSC_Enable: %s\n", 2082 str_yes_no(intel_dp->force_dsc_en)); 2083 if (!intel_dp_is_edp(intel_dp)) 2084 seq_printf(m, "FEC_Sink_Support: %s\n", 2085 str_yes_no(drm_dp_sink_supports_fec(intel_dp->fec_capable))); 2086 } while (try_again); 2087 2088 drm_modeset_drop_locks(&ctx); 2089 drm_modeset_acquire_fini(&ctx); 2090 2091 return ret; 2092 } 2093 2094 static ssize_t i915_dsc_fec_support_write(struct file *file, 2095 const char __user *ubuf, 2096 size_t len, loff_t *offp) 2097 { 2098 bool dsc_enable = false; 2099 int ret; 2100 struct drm_connector *connector = 2101 ((struct seq_file *)file->private_data)->private; 2102 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 2103 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2104 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2105 2106 if (len == 0) 2107 return 0; 2108 2109 drm_dbg(&i915->drm, 2110 "Copied %zu bytes from user to force DSC\n", len); 2111 2112 ret = kstrtobool_from_user(ubuf, len, &dsc_enable); 2113 if (ret < 0) 2114 return ret; 2115 2116 drm_dbg(&i915->drm, "Got %s for DSC Enable\n", 2117 (dsc_enable) ? "true" : "false"); 2118 intel_dp->force_dsc_en = dsc_enable; 2119 2120 *offp += len; 2121 return len; 2122 } 2123 2124 static int i915_dsc_fec_support_open(struct inode *inode, 2125 struct file *file) 2126 { 2127 return single_open(file, i915_dsc_fec_support_show, 2128 inode->i_private); 2129 } 2130 2131 static const struct file_operations i915_dsc_fec_support_fops = { 2132 .owner = THIS_MODULE, 2133 .open = i915_dsc_fec_support_open, 2134 .read = seq_read, 2135 .llseek = seq_lseek, 2136 .release = single_release, 2137 .write = i915_dsc_fec_support_write 2138 }; 2139 2140 static int i915_dsc_bpp_show(struct seq_file *m, void *data) 2141 { 2142 struct drm_connector *connector = m->private; 2143 struct drm_device *dev = connector->dev; 2144 struct drm_crtc *crtc; 2145 struct intel_crtc_state *crtc_state; 2146 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 2147 int ret; 2148 2149 if (!encoder) 2150 return -ENODEV; 2151 2152 ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex); 2153 if (ret) 2154 return ret; 2155 2156 crtc = connector->state->crtc; 2157 if (connector->status != connector_status_connected || !crtc) { 2158 ret = -ENODEV; 2159 goto out; 2160 } 2161 2162 crtc_state = to_intel_crtc_state(crtc->state); 2163 seq_printf(m, "Compressed_BPP: %d\n", crtc_state->dsc.compressed_bpp); 2164 2165 out: drm_modeset_unlock(&dev->mode_config.connection_mutex); 2166 2167 return ret; 2168 } 2169 2170 static ssize_t i915_dsc_bpp_write(struct file *file, 2171 const char __user *ubuf, 2172 size_t len, loff_t *offp) 2173 { 2174 struct drm_connector *connector = 2175 ((struct seq_file *)file->private_data)->private; 2176 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 2177 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2178 int dsc_bpp = 0; 2179 int ret; 2180 2181 ret = kstrtoint_from_user(ubuf, len, 0, &dsc_bpp); 2182 if (ret < 0) 2183 return ret; 2184 2185 intel_dp->force_dsc_bpp = dsc_bpp; 2186 *offp += len; 2187 2188 return len; 2189 } 2190 2191 static int i915_dsc_bpp_open(struct inode *inode, 2192 struct file *file) 2193 { 2194 return single_open(file, i915_dsc_bpp_show, 2195 inode->i_private); 2196 } 2197 2198 static const struct file_operations i915_dsc_bpp_fops = { 2199 .owner = THIS_MODULE, 2200 .open = i915_dsc_bpp_open, 2201 .read = seq_read, 2202 .llseek = seq_lseek, 2203 .release = single_release, 2204 .write = i915_dsc_bpp_write 2205 }; 2206 2207 /* 2208 * Returns the Current CRTC's bpc. 2209 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc 2210 */ 2211 static int i915_current_bpc_show(struct seq_file *m, void *data) 2212 { 2213 struct intel_crtc *crtc = to_intel_crtc(m->private); 2214 struct intel_crtc_state *crtc_state; 2215 int ret; 2216 2217 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); 2218 if (ret) 2219 return ret; 2220 2221 crtc_state = to_intel_crtc_state(crtc->base.state); 2222 seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3); 2223 2224 drm_modeset_unlock(&crtc->base.mutex); 2225 2226 return ret; 2227 } 2228 DEFINE_SHOW_ATTRIBUTE(i915_current_bpc); 2229 2230 /** 2231 * intel_connector_debugfs_add - add i915 specific connector debugfs files 2232 * @connector: pointer to a registered drm_connector 2233 * 2234 * Cleanup will be done by drm_connector_unregister() through a call to 2235 * drm_debugfs_connector_remove(). 2236 */ 2237 void intel_connector_debugfs_add(struct intel_connector *intel_connector) 2238 { 2239 struct drm_connector *connector = &intel_connector->base; 2240 struct dentry *root = connector->debugfs_entry; 2241 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2242 2243 /* The connector must have been registered beforehands. */ 2244 if (!root) 2245 return; 2246 2247 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 2248 debugfs_create_file("i915_panel_timings", S_IRUGO, root, 2249 connector, &i915_panel_fops); 2250 debugfs_create_file("i915_psr_sink_status", S_IRUGO, root, 2251 connector, &i915_psr_sink_status_fops); 2252 } 2253 2254 if (HAS_PSR(dev_priv) && 2255 connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 2256 debugfs_create_file("i915_psr_status", 0444, root, 2257 connector, &i915_psr_status_fops); 2258 } 2259 2260 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2261 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 2262 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) { 2263 debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root, 2264 connector, &i915_hdcp_sink_capability_fops); 2265 } 2266 2267 if (DISPLAY_VER(dev_priv) >= 11 && 2268 ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && 2269 !to_intel_connector(connector)->mst_port) || 2270 connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 2271 debugfs_create_file("i915_dsc_fec_support", 0644, root, 2272 connector, &i915_dsc_fec_support_fops); 2273 2274 debugfs_create_file("i915_dsc_bpp", 0644, root, 2275 connector, &i915_dsc_bpp_fops); 2276 } 2277 2278 if (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 2279 connector->connector_type == DRM_MODE_CONNECTOR_eDP || 2280 connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2281 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 2282 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 2283 debugfs_create_file("i915_lpsp_capability", 0444, root, 2284 connector, &i915_lpsp_capability_fops); 2285 } 2286 2287 /** 2288 * intel_crtc_debugfs_add - add i915 specific crtc debugfs files 2289 * @crtc: pointer to a drm_crtc 2290 * 2291 * Failure to add debugfs entries should generally be ignored. 2292 */ 2293 void intel_crtc_debugfs_add(struct drm_crtc *crtc) 2294 { 2295 if (!crtc->debugfs_entry) 2296 return; 2297 2298 crtc_updates_add(crtc); 2299 intel_fbc_crtc_debugfs_add(to_intel_crtc(crtc)); 2300 2301 debugfs_create_file("i915_current_bpc", 0444, crtc->debugfs_entry, crtc, 2302 &i915_current_bpc_fops); 2303 } 2304