1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include <drm/drm_debugfs.h> 9 #include <drm/drm_fourcc.h> 10 11 #include "hsw_ips.h" 12 #include "i915_debugfs.h" 13 #include "i915_irq.h" 14 #include "i915_reg.h" 15 #include "intel_de.h" 16 #include "intel_display_debugfs.h" 17 #include "intel_display_power.h" 18 #include "intel_display_power_well.h" 19 #include "intel_display_types.h" 20 #include "intel_dmc.h" 21 #include "intel_dp.h" 22 #include "intel_dp_mst.h" 23 #include "intel_drrs.h" 24 #include "intel_fbc.h" 25 #include "intel_fbdev.h" 26 #include "intel_hdcp.h" 27 #include "intel_hdmi.h" 28 #include "intel_hotplug.h" 29 #include "intel_panel.h" 30 #include "intel_psr.h" 31 #include "intel_sprite.h" 32 #include "intel_wm.h" 33 34 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 35 { 36 return to_i915(node->minor->dev); 37 } 38 39 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) 40 { 41 struct drm_i915_private *dev_priv = node_to_i915(m->private); 42 43 seq_printf(m, "FB tracking busy bits: 0x%08x\n", 44 dev_priv->display.fb_tracking.busy_bits); 45 46 seq_printf(m, "FB tracking flip bits: 0x%08x\n", 47 dev_priv->display.fb_tracking.flip_bits); 48 49 return 0; 50 } 51 52 static int i915_sr_status(struct seq_file *m, void *unused) 53 { 54 struct drm_i915_private *dev_priv = node_to_i915(m->private); 55 intel_wakeref_t wakeref; 56 bool sr_enabled = false; 57 58 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 59 60 if (DISPLAY_VER(dev_priv) >= 9) 61 /* no global SR status; inspect per-plane WM */; 62 else if (HAS_PCH_SPLIT(dev_priv)) 63 sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE; 64 else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || 65 IS_I945G(dev_priv) || IS_I945GM(dev_priv)) 66 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN; 67 else if (IS_I915GM(dev_priv)) 68 sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN; 69 else if (IS_PINEVIEW(dev_priv)) 70 sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN; 71 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 72 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; 73 74 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 75 76 seq_printf(m, "self-refresh: %s\n", str_enabled_disabled(sr_enabled)); 77 78 return 0; 79 } 80 81 static int i915_opregion(struct seq_file *m, void *unused) 82 { 83 struct drm_i915_private *i915 = node_to_i915(m->private); 84 struct intel_opregion *opregion = &i915->display.opregion; 85 86 if (opregion->header) 87 seq_write(m, opregion->header, OPREGION_SIZE); 88 89 return 0; 90 } 91 92 static int i915_vbt(struct seq_file *m, void *unused) 93 { 94 struct drm_i915_private *i915 = node_to_i915(m->private); 95 struct intel_opregion *opregion = &i915->display.opregion; 96 97 if (opregion->vbt) 98 seq_write(m, opregion->vbt, opregion->vbt_size); 99 100 return 0; 101 } 102 103 static int i915_gem_framebuffer_info(struct seq_file *m, void *data) 104 { 105 struct drm_i915_private *dev_priv = node_to_i915(m->private); 106 struct intel_framebuffer *fbdev_fb = NULL; 107 struct drm_framebuffer *drm_fb; 108 109 #ifdef CONFIG_DRM_FBDEV_EMULATION 110 fbdev_fb = intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev); 111 if (fbdev_fb) { 112 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 113 fbdev_fb->base.width, 114 fbdev_fb->base.height, 115 fbdev_fb->base.format->depth, 116 fbdev_fb->base.format->cpp[0] * 8, 117 fbdev_fb->base.modifier, 118 drm_framebuffer_read_refcount(&fbdev_fb->base)); 119 i915_debugfs_describe_obj(m, intel_fb_obj(&fbdev_fb->base)); 120 seq_putc(m, '\n'); 121 } 122 #endif 123 124 mutex_lock(&dev_priv->drm.mode_config.fb_lock); 125 drm_for_each_fb(drm_fb, &dev_priv->drm) { 126 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); 127 if (fb == fbdev_fb) 128 continue; 129 130 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 131 fb->base.width, 132 fb->base.height, 133 fb->base.format->depth, 134 fb->base.format->cpp[0] * 8, 135 fb->base.modifier, 136 drm_framebuffer_read_refcount(&fb->base)); 137 i915_debugfs_describe_obj(m, intel_fb_obj(&fb->base)); 138 seq_putc(m, '\n'); 139 } 140 mutex_unlock(&dev_priv->drm.mode_config.fb_lock); 141 142 return 0; 143 } 144 145 static int i915_power_domain_info(struct seq_file *m, void *unused) 146 { 147 struct drm_i915_private *i915 = node_to_i915(m->private); 148 149 intel_display_power_debug(i915, m); 150 151 return 0; 152 } 153 154 static void intel_seq_print_mode(struct seq_file *m, int tabs, 155 const struct drm_display_mode *mode) 156 { 157 int i; 158 159 for (i = 0; i < tabs; i++) 160 seq_putc(m, '\t'); 161 162 seq_printf(m, DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); 163 } 164 165 static void intel_encoder_info(struct seq_file *m, 166 struct intel_crtc *crtc, 167 struct intel_encoder *encoder) 168 { 169 struct drm_i915_private *dev_priv = node_to_i915(m->private); 170 struct drm_connector_list_iter conn_iter; 171 struct drm_connector *connector; 172 173 seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n", 174 encoder->base.base.id, encoder->base.name); 175 176 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 177 drm_for_each_connector_iter(connector, &conn_iter) { 178 const struct drm_connector_state *conn_state = 179 connector->state; 180 181 if (conn_state->best_encoder != &encoder->base) 182 continue; 183 184 seq_printf(m, "\t\t[CONNECTOR:%d:%s]\n", 185 connector->base.id, connector->name); 186 } 187 drm_connector_list_iter_end(&conn_iter); 188 } 189 190 static void intel_panel_info(struct seq_file *m, 191 struct intel_connector *connector) 192 { 193 const struct drm_display_mode *fixed_mode; 194 195 if (list_empty(&connector->panel.fixed_modes)) 196 return; 197 198 seq_puts(m, "\tfixed modes:\n"); 199 200 list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) 201 intel_seq_print_mode(m, 2, fixed_mode); 202 } 203 204 static void intel_hdcp_info(struct seq_file *m, 205 struct intel_connector *intel_connector) 206 { 207 bool hdcp_cap, hdcp2_cap; 208 209 if (!intel_connector->hdcp.shim) { 210 seq_puts(m, "No Connector Support"); 211 goto out; 212 } 213 214 hdcp_cap = intel_hdcp_capable(intel_connector); 215 hdcp2_cap = intel_hdcp2_capable(intel_connector); 216 217 if (hdcp_cap) 218 seq_puts(m, "HDCP1.4 "); 219 if (hdcp2_cap) 220 seq_puts(m, "HDCP2.2 "); 221 222 if (!hdcp_cap && !hdcp2_cap) 223 seq_puts(m, "None"); 224 225 out: 226 seq_puts(m, "\n"); 227 } 228 229 static void intel_dp_info(struct seq_file *m, 230 struct intel_connector *intel_connector) 231 { 232 struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); 233 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); 234 const struct drm_property_blob *edid = intel_connector->base.edid_blob_ptr; 235 236 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); 237 seq_printf(m, "\taudio support: %s\n", 238 str_yes_no(intel_dp->has_audio)); 239 240 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, 241 edid ? edid->data : NULL, &intel_dp->aux); 242 } 243 244 static void intel_dp_mst_info(struct seq_file *m, 245 struct intel_connector *intel_connector) 246 { 247 bool has_audio = intel_connector->port->has_audio; 248 249 seq_printf(m, "\taudio support: %s\n", str_yes_no(has_audio)); 250 } 251 252 static void intel_hdmi_info(struct seq_file *m, 253 struct intel_connector *intel_connector) 254 { 255 struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); 256 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(intel_encoder); 257 258 seq_printf(m, "\taudio support: %s\n", 259 str_yes_no(intel_hdmi->has_audio)); 260 } 261 262 static void intel_connector_info(struct seq_file *m, 263 struct drm_connector *connector) 264 { 265 struct intel_connector *intel_connector = to_intel_connector(connector); 266 const struct drm_connector_state *conn_state = connector->state; 267 struct intel_encoder *encoder = 268 to_intel_encoder(conn_state->best_encoder); 269 const struct drm_display_mode *mode; 270 271 seq_printf(m, "[CONNECTOR:%d:%s]: status: %s\n", 272 connector->base.id, connector->name, 273 drm_get_connector_status_name(connector->status)); 274 275 if (connector->status == connector_status_disconnected) 276 return; 277 278 seq_printf(m, "\tphysical dimensions: %dx%dmm\n", 279 connector->display_info.width_mm, 280 connector->display_info.height_mm); 281 seq_printf(m, "\tsubpixel order: %s\n", 282 drm_get_subpixel_order_name(connector->display_info.subpixel_order)); 283 seq_printf(m, "\tCEA rev: %d\n", connector->display_info.cea_rev); 284 285 if (!encoder) 286 return; 287 288 switch (connector->connector_type) { 289 case DRM_MODE_CONNECTOR_DisplayPort: 290 case DRM_MODE_CONNECTOR_eDP: 291 if (encoder->type == INTEL_OUTPUT_DP_MST) 292 intel_dp_mst_info(m, intel_connector); 293 else 294 intel_dp_info(m, intel_connector); 295 break; 296 case DRM_MODE_CONNECTOR_HDMIA: 297 if (encoder->type == INTEL_OUTPUT_HDMI || 298 encoder->type == INTEL_OUTPUT_DDI) 299 intel_hdmi_info(m, intel_connector); 300 break; 301 default: 302 break; 303 } 304 305 seq_puts(m, "\tHDCP version: "); 306 intel_hdcp_info(m, intel_connector); 307 308 seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc); 309 310 intel_panel_info(m, intel_connector); 311 312 seq_printf(m, "\tmodes:\n"); 313 list_for_each_entry(mode, &connector->modes, head) 314 intel_seq_print_mode(m, 2, mode); 315 } 316 317 static const char *plane_type(enum drm_plane_type type) 318 { 319 switch (type) { 320 case DRM_PLANE_TYPE_OVERLAY: 321 return "OVL"; 322 case DRM_PLANE_TYPE_PRIMARY: 323 return "PRI"; 324 case DRM_PLANE_TYPE_CURSOR: 325 return "CUR"; 326 /* 327 * Deliberately omitting default: to generate compiler warnings 328 * when a new drm_plane_type gets added. 329 */ 330 } 331 332 return "unknown"; 333 } 334 335 static void plane_rotation(char *buf, size_t bufsize, unsigned int rotation) 336 { 337 /* 338 * According to doc only one DRM_MODE_ROTATE_ is allowed but this 339 * will print them all to visualize if the values are misused 340 */ 341 snprintf(buf, bufsize, 342 "%s%s%s%s%s%s(0x%08x)", 343 (rotation & DRM_MODE_ROTATE_0) ? "0 " : "", 344 (rotation & DRM_MODE_ROTATE_90) ? "90 " : "", 345 (rotation & DRM_MODE_ROTATE_180) ? "180 " : "", 346 (rotation & DRM_MODE_ROTATE_270) ? "270 " : "", 347 (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "", 348 (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "", 349 rotation); 350 } 351 352 static const char *plane_visibility(const struct intel_plane_state *plane_state) 353 { 354 if (plane_state->uapi.visible) 355 return "visible"; 356 357 if (plane_state->planar_slave) 358 return "planar-slave"; 359 360 return "hidden"; 361 } 362 363 static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane) 364 { 365 const struct intel_plane_state *plane_state = 366 to_intel_plane_state(plane->base.state); 367 const struct drm_framebuffer *fb = plane_state->uapi.fb; 368 struct drm_rect src, dst; 369 char rot_str[48]; 370 371 src = drm_plane_state_src(&plane_state->uapi); 372 dst = drm_plane_state_dest(&plane_state->uapi); 373 374 plane_rotation(rot_str, sizeof(rot_str), 375 plane_state->uapi.rotation); 376 377 seq_puts(m, "\t\tuapi: [FB:"); 378 if (fb) 379 seq_printf(m, "%d] %p4cc,0x%llx,%dx%d", fb->base.id, 380 &fb->format->format, fb->modifier, fb->width, 381 fb->height); 382 else 383 seq_puts(m, "0] n/a,0x0,0x0,"); 384 seq_printf(m, ", visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT 385 ", rotation=%s\n", plane_visibility(plane_state), 386 DRM_RECT_FP_ARG(&src), DRM_RECT_ARG(&dst), rot_str); 387 388 if (plane_state->planar_linked_plane) 389 seq_printf(m, "\t\tplanar: Linked to [PLANE:%d:%s] as a %s\n", 390 plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name, 391 plane_state->planar_slave ? "slave" : "master"); 392 } 393 394 static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane) 395 { 396 const struct intel_plane_state *plane_state = 397 to_intel_plane_state(plane->base.state); 398 const struct drm_framebuffer *fb = plane_state->hw.fb; 399 char rot_str[48]; 400 401 if (!fb) 402 return; 403 404 plane_rotation(rot_str, sizeof(rot_str), 405 plane_state->hw.rotation); 406 407 seq_printf(m, "\t\thw: [FB:%d] %p4cc,0x%llx,%dx%d, visible=%s, src=" 408 DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n", 409 fb->base.id, &fb->format->format, 410 fb->modifier, fb->width, fb->height, 411 str_yes_no(plane_state->uapi.visible), 412 DRM_RECT_FP_ARG(&plane_state->uapi.src), 413 DRM_RECT_ARG(&plane_state->uapi.dst), 414 rot_str); 415 } 416 417 static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc) 418 { 419 struct drm_i915_private *dev_priv = node_to_i915(m->private); 420 struct intel_plane *plane; 421 422 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 423 seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n", 424 plane->base.base.id, plane->base.name, 425 plane_type(plane->base.type)); 426 intel_plane_uapi_info(m, plane); 427 intel_plane_hw_info(m, plane); 428 } 429 } 430 431 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *crtc) 432 { 433 const struct intel_crtc_state *crtc_state = 434 to_intel_crtc_state(crtc->base.state); 435 int num_scalers = crtc->num_scalers; 436 int i; 437 438 /* Not all platformas have a scaler */ 439 if (num_scalers) { 440 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d scaling_filter=%d", 441 num_scalers, 442 crtc_state->scaler_state.scaler_users, 443 crtc_state->scaler_state.scaler_id, 444 crtc_state->hw.scaling_filter); 445 446 for (i = 0; i < num_scalers; i++) { 447 const struct intel_scaler *sc = 448 &crtc_state->scaler_state.scalers[i]; 449 450 seq_printf(m, ", scalers[%d]: use=%s, mode=%x", 451 i, str_yes_no(sc->in_use), sc->mode); 452 } 453 seq_puts(m, "\n"); 454 } else { 455 seq_puts(m, "\tNo scalers available on this platform\n"); 456 } 457 } 458 459 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE) 460 static void crtc_updates_info(struct seq_file *m, 461 struct intel_crtc *crtc, 462 const char *hdr) 463 { 464 u64 count; 465 int row; 466 467 count = 0; 468 for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++) 469 count += crtc->debug.vbl.times[row]; 470 seq_printf(m, "%sUpdates: %llu\n", hdr, count); 471 if (!count) 472 return; 473 474 for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++) { 475 char columns[80] = " |"; 476 unsigned int x; 477 478 if (row & 1) { 479 const char *units; 480 481 if (row > 10) { 482 x = 1000000; 483 units = "ms"; 484 } else { 485 x = 1000; 486 units = "us"; 487 } 488 489 snprintf(columns, sizeof(columns), "%4ld%s |", 490 DIV_ROUND_CLOSEST(BIT(row + 9), x), units); 491 } 492 493 if (crtc->debug.vbl.times[row]) { 494 x = ilog2(crtc->debug.vbl.times[row]); 495 memset(columns + 8, '*', x); 496 columns[8 + x] = '\0'; 497 } 498 499 seq_printf(m, "%s%s\n", hdr, columns); 500 } 501 502 seq_printf(m, "%sMin update: %lluns\n", 503 hdr, crtc->debug.vbl.min); 504 seq_printf(m, "%sMax update: %lluns\n", 505 hdr, crtc->debug.vbl.max); 506 seq_printf(m, "%sAverage update: %lluns\n", 507 hdr, div64_u64(crtc->debug.vbl.sum, count)); 508 seq_printf(m, "%sOverruns > %uus: %u\n", 509 hdr, VBLANK_EVASION_TIME_US, crtc->debug.vbl.over); 510 } 511 512 static int crtc_updates_show(struct seq_file *m, void *data) 513 { 514 crtc_updates_info(m, m->private, ""); 515 return 0; 516 } 517 518 static int crtc_updates_open(struct inode *inode, struct file *file) 519 { 520 return single_open(file, crtc_updates_show, inode->i_private); 521 } 522 523 static ssize_t crtc_updates_write(struct file *file, 524 const char __user *ubuf, 525 size_t len, loff_t *offp) 526 { 527 struct seq_file *m = file->private_data; 528 struct intel_crtc *crtc = m->private; 529 530 /* May race with an update. Meh. */ 531 memset(&crtc->debug.vbl, 0, sizeof(crtc->debug.vbl)); 532 533 return len; 534 } 535 536 static const struct file_operations crtc_updates_fops = { 537 .owner = THIS_MODULE, 538 .open = crtc_updates_open, 539 .read = seq_read, 540 .llseek = seq_lseek, 541 .release = single_release, 542 .write = crtc_updates_write 543 }; 544 545 static void crtc_updates_add(struct intel_crtc *crtc) 546 { 547 debugfs_create_file("i915_update_info", 0644, crtc->base.debugfs_entry, 548 crtc, &crtc_updates_fops); 549 } 550 551 #else 552 static void crtc_updates_info(struct seq_file *m, 553 struct intel_crtc *crtc, 554 const char *hdr) 555 { 556 } 557 558 static void crtc_updates_add(struct intel_crtc *crtc) 559 { 560 } 561 #endif 562 563 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) 564 { 565 struct drm_i915_private *dev_priv = node_to_i915(m->private); 566 const struct intel_crtc_state *crtc_state = 567 to_intel_crtc_state(crtc->base.state); 568 struct intel_encoder *encoder; 569 570 seq_printf(m, "[CRTC:%d:%s]:\n", 571 crtc->base.base.id, crtc->base.name); 572 573 seq_printf(m, "\tuapi: enable=%s, active=%s, mode=" DRM_MODE_FMT "\n", 574 str_yes_no(crtc_state->uapi.enable), 575 str_yes_no(crtc_state->uapi.active), 576 DRM_MODE_ARG(&crtc_state->uapi.mode)); 577 578 seq_printf(m, "\thw: enable=%s, active=%s\n", 579 str_yes_no(crtc_state->hw.enable), str_yes_no(crtc_state->hw.active)); 580 seq_printf(m, "\tadjusted_mode=" DRM_MODE_FMT "\n", 581 DRM_MODE_ARG(&crtc_state->hw.adjusted_mode)); 582 seq_printf(m, "\tpipe__mode=" DRM_MODE_FMT "\n", 583 DRM_MODE_ARG(&crtc_state->hw.pipe_mode)); 584 585 seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d\n", 586 DRM_RECT_ARG(&crtc_state->pipe_src), 587 str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); 588 589 intel_scaler_info(m, crtc); 590 591 if (crtc_state->bigjoiner_pipes) 592 seq_printf(m, "\tLinked to 0x%x pipes as a %s\n", 593 crtc_state->bigjoiner_pipes, 594 intel_crtc_is_bigjoiner_slave(crtc_state) ? "slave" : "master"); 595 596 for_each_intel_encoder_mask(&dev_priv->drm, encoder, 597 crtc_state->uapi.encoder_mask) 598 intel_encoder_info(m, crtc, encoder); 599 600 intel_plane_info(m, crtc); 601 602 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s\n", 603 str_yes_no(!crtc->cpu_fifo_underrun_disabled), 604 str_yes_no(!crtc->pch_fifo_underrun_disabled)); 605 606 crtc_updates_info(m, crtc, "\t"); 607 } 608 609 static int i915_display_info(struct seq_file *m, void *unused) 610 { 611 struct drm_i915_private *dev_priv = node_to_i915(m->private); 612 struct intel_crtc *crtc; 613 struct drm_connector *connector; 614 struct drm_connector_list_iter conn_iter; 615 intel_wakeref_t wakeref; 616 617 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 618 619 drm_modeset_lock_all(&dev_priv->drm); 620 621 seq_printf(m, "CRTC info\n"); 622 seq_printf(m, "---------\n"); 623 for_each_intel_crtc(&dev_priv->drm, crtc) 624 intel_crtc_info(m, crtc); 625 626 seq_printf(m, "\n"); 627 seq_printf(m, "Connector info\n"); 628 seq_printf(m, "--------------\n"); 629 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 630 drm_for_each_connector_iter(connector, &conn_iter) 631 intel_connector_info(m, connector); 632 drm_connector_list_iter_end(&conn_iter); 633 634 drm_modeset_unlock_all(&dev_priv->drm); 635 636 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 637 638 return 0; 639 } 640 641 static int i915_shared_dplls_info(struct seq_file *m, void *unused) 642 { 643 struct drm_i915_private *dev_priv = node_to_i915(m->private); 644 int i; 645 646 drm_modeset_lock_all(&dev_priv->drm); 647 648 seq_printf(m, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n", 649 dev_priv->display.dpll.ref_clks.nssc, 650 dev_priv->display.dpll.ref_clks.ssc); 651 652 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { 653 struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; 654 655 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name, 656 pll->info->id); 657 seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n", 658 pll->state.pipe_mask, pll->active_mask, 659 str_yes_no(pll->on)); 660 seq_printf(m, " tracked hardware state:\n"); 661 seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); 662 seq_printf(m, " dpll_md: 0x%08x\n", 663 pll->state.hw_state.dpll_md); 664 seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); 665 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); 666 seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); 667 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); 668 seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); 669 seq_printf(m, " div0: 0x%08x\n", pll->state.hw_state.div0); 670 seq_printf(m, " mg_refclkin_ctl: 0x%08x\n", 671 pll->state.hw_state.mg_refclkin_ctl); 672 seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n", 673 pll->state.hw_state.mg_clktop2_coreclkctl1); 674 seq_printf(m, " mg_clktop2_hsclkctl: 0x%08x\n", 675 pll->state.hw_state.mg_clktop2_hsclkctl); 676 seq_printf(m, " mg_pll_div0: 0x%08x\n", 677 pll->state.hw_state.mg_pll_div0); 678 seq_printf(m, " mg_pll_div1: 0x%08x\n", 679 pll->state.hw_state.mg_pll_div1); 680 seq_printf(m, " mg_pll_lf: 0x%08x\n", 681 pll->state.hw_state.mg_pll_lf); 682 seq_printf(m, " mg_pll_frac_lock: 0x%08x\n", 683 pll->state.hw_state.mg_pll_frac_lock); 684 seq_printf(m, " mg_pll_ssc: 0x%08x\n", 685 pll->state.hw_state.mg_pll_ssc); 686 seq_printf(m, " mg_pll_bias: 0x%08x\n", 687 pll->state.hw_state.mg_pll_bias); 688 seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n", 689 pll->state.hw_state.mg_pll_tdc_coldst_bias); 690 } 691 drm_modeset_unlock_all(&dev_priv->drm); 692 693 return 0; 694 } 695 696 static int i915_ddb_info(struct seq_file *m, void *unused) 697 { 698 struct drm_i915_private *dev_priv = node_to_i915(m->private); 699 struct skl_ddb_entry *entry; 700 struct intel_crtc *crtc; 701 702 if (DISPLAY_VER(dev_priv) < 9) 703 return -ENODEV; 704 705 drm_modeset_lock_all(&dev_priv->drm); 706 707 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); 708 709 for_each_intel_crtc(&dev_priv->drm, crtc) { 710 struct intel_crtc_state *crtc_state = 711 to_intel_crtc_state(crtc->base.state); 712 enum pipe pipe = crtc->pipe; 713 enum plane_id plane_id; 714 715 seq_printf(m, "Pipe %c\n", pipe_name(pipe)); 716 717 for_each_plane_id_on_crtc(crtc, plane_id) { 718 entry = &crtc_state->wm.skl.plane_ddb[plane_id]; 719 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1, 720 entry->start, entry->end, 721 skl_ddb_entry_size(entry)); 722 } 723 724 entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 725 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, 726 entry->end, skl_ddb_entry_size(entry)); 727 } 728 729 drm_modeset_unlock_all(&dev_priv->drm); 730 731 return 0; 732 } 733 734 static bool 735 intel_lpsp_power_well_enabled(struct drm_i915_private *i915, 736 enum i915_power_well_id power_well_id) 737 { 738 intel_wakeref_t wakeref; 739 bool is_enabled; 740 741 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 742 is_enabled = intel_display_power_well_is_enabled(i915, 743 power_well_id); 744 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 745 746 return is_enabled; 747 } 748 749 static int i915_lpsp_status(struct seq_file *m, void *unused) 750 { 751 struct drm_i915_private *i915 = node_to_i915(m->private); 752 bool lpsp_enabled = false; 753 754 if (DISPLAY_VER(i915) >= 13 || IS_DISPLAY_VER(i915, 9, 10)) { 755 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, SKL_DISP_PW_2); 756 } else if (IS_DISPLAY_VER(i915, 11, 12)) { 757 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3); 758 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 759 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, HSW_DISP_PW_GLOBAL); 760 } else { 761 seq_puts(m, "LPSP: not supported\n"); 762 return 0; 763 } 764 765 seq_printf(m, "LPSP: %s\n", str_enabled_disabled(lpsp_enabled)); 766 767 return 0; 768 } 769 770 static int i915_dp_mst_info(struct seq_file *m, void *unused) 771 { 772 struct drm_i915_private *dev_priv = node_to_i915(m->private); 773 struct intel_encoder *intel_encoder; 774 struct intel_digital_port *dig_port; 775 struct drm_connector *connector; 776 struct drm_connector_list_iter conn_iter; 777 778 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 779 drm_for_each_connector_iter(connector, &conn_iter) { 780 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 781 continue; 782 783 intel_encoder = intel_attached_encoder(to_intel_connector(connector)); 784 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) 785 continue; 786 787 dig_port = enc_to_dig_port(intel_encoder); 788 if (!intel_dp_mst_source_support(&dig_port->dp)) 789 continue; 790 791 seq_printf(m, "MST Source Port [ENCODER:%d:%s]\n", 792 dig_port->base.base.base.id, 793 dig_port->base.base.name); 794 drm_dp_mst_dump_topology(m, &dig_port->dp.mst_mgr); 795 } 796 drm_connector_list_iter_end(&conn_iter); 797 798 return 0; 799 } 800 801 static ssize_t i915_displayport_test_active_write(struct file *file, 802 const char __user *ubuf, 803 size_t len, loff_t *offp) 804 { 805 char *input_buffer; 806 int status = 0; 807 struct drm_device *dev; 808 struct drm_connector *connector; 809 struct drm_connector_list_iter conn_iter; 810 struct intel_dp *intel_dp; 811 int val = 0; 812 813 dev = ((struct seq_file *)file->private_data)->private; 814 815 if (len == 0) 816 return 0; 817 818 input_buffer = memdup_user_nul(ubuf, len); 819 if (IS_ERR(input_buffer)) 820 return PTR_ERR(input_buffer); 821 822 drm_dbg(&to_i915(dev)->drm, 823 "Copied %d bytes from user\n", (unsigned int)len); 824 825 drm_connector_list_iter_begin(dev, &conn_iter); 826 drm_for_each_connector_iter(connector, &conn_iter) { 827 struct intel_encoder *encoder; 828 829 if (connector->connector_type != 830 DRM_MODE_CONNECTOR_DisplayPort) 831 continue; 832 833 encoder = to_intel_encoder(connector->encoder); 834 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 835 continue; 836 837 if (encoder && connector->status == connector_status_connected) { 838 intel_dp = enc_to_intel_dp(encoder); 839 status = kstrtoint(input_buffer, 10, &val); 840 if (status < 0) 841 break; 842 drm_dbg(&to_i915(dev)->drm, 843 "Got %d for test active\n", val); 844 /* To prevent erroneous activation of the compliance 845 * testing code, only accept an actual value of 1 here 846 */ 847 if (val == 1) 848 intel_dp->compliance.test_active = true; 849 else 850 intel_dp->compliance.test_active = false; 851 } 852 } 853 drm_connector_list_iter_end(&conn_iter); 854 kfree(input_buffer); 855 if (status < 0) 856 return status; 857 858 *offp += len; 859 return len; 860 } 861 862 static int i915_displayport_test_active_show(struct seq_file *m, void *data) 863 { 864 struct drm_i915_private *dev_priv = m->private; 865 struct drm_connector *connector; 866 struct drm_connector_list_iter conn_iter; 867 struct intel_dp *intel_dp; 868 869 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 870 drm_for_each_connector_iter(connector, &conn_iter) { 871 struct intel_encoder *encoder; 872 873 if (connector->connector_type != 874 DRM_MODE_CONNECTOR_DisplayPort) 875 continue; 876 877 encoder = to_intel_encoder(connector->encoder); 878 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 879 continue; 880 881 if (encoder && connector->status == connector_status_connected) { 882 intel_dp = enc_to_intel_dp(encoder); 883 if (intel_dp->compliance.test_active) 884 seq_puts(m, "1"); 885 else 886 seq_puts(m, "0"); 887 } else 888 seq_puts(m, "0"); 889 } 890 drm_connector_list_iter_end(&conn_iter); 891 892 return 0; 893 } 894 895 static int i915_displayport_test_active_open(struct inode *inode, 896 struct file *file) 897 { 898 return single_open(file, i915_displayport_test_active_show, 899 inode->i_private); 900 } 901 902 static const struct file_operations i915_displayport_test_active_fops = { 903 .owner = THIS_MODULE, 904 .open = i915_displayport_test_active_open, 905 .read = seq_read, 906 .llseek = seq_lseek, 907 .release = single_release, 908 .write = i915_displayport_test_active_write 909 }; 910 911 static int i915_displayport_test_data_show(struct seq_file *m, void *data) 912 { 913 struct drm_i915_private *dev_priv = m->private; 914 struct drm_connector *connector; 915 struct drm_connector_list_iter conn_iter; 916 struct intel_dp *intel_dp; 917 918 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 919 drm_for_each_connector_iter(connector, &conn_iter) { 920 struct intel_encoder *encoder; 921 922 if (connector->connector_type != 923 DRM_MODE_CONNECTOR_DisplayPort) 924 continue; 925 926 encoder = to_intel_encoder(connector->encoder); 927 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 928 continue; 929 930 if (encoder && connector->status == connector_status_connected) { 931 intel_dp = enc_to_intel_dp(encoder); 932 if (intel_dp->compliance.test_type == 933 DP_TEST_LINK_EDID_READ) 934 seq_printf(m, "%lx", 935 intel_dp->compliance.test_data.edid); 936 else if (intel_dp->compliance.test_type == 937 DP_TEST_LINK_VIDEO_PATTERN) { 938 seq_printf(m, "hdisplay: %d\n", 939 intel_dp->compliance.test_data.hdisplay); 940 seq_printf(m, "vdisplay: %d\n", 941 intel_dp->compliance.test_data.vdisplay); 942 seq_printf(m, "bpc: %u\n", 943 intel_dp->compliance.test_data.bpc); 944 } else if (intel_dp->compliance.test_type == 945 DP_TEST_LINK_PHY_TEST_PATTERN) { 946 seq_printf(m, "pattern: %d\n", 947 intel_dp->compliance.test_data.phytest.phy_pattern); 948 seq_printf(m, "Number of lanes: %d\n", 949 intel_dp->compliance.test_data.phytest.num_lanes); 950 seq_printf(m, "Link Rate: %d\n", 951 intel_dp->compliance.test_data.phytest.link_rate); 952 seq_printf(m, "level: %02x\n", 953 intel_dp->train_set[0]); 954 } 955 } else 956 seq_puts(m, "0"); 957 } 958 drm_connector_list_iter_end(&conn_iter); 959 960 return 0; 961 } 962 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_data); 963 964 static int i915_displayport_test_type_show(struct seq_file *m, void *data) 965 { 966 struct drm_i915_private *dev_priv = m->private; 967 struct drm_connector *connector; 968 struct drm_connector_list_iter conn_iter; 969 struct intel_dp *intel_dp; 970 971 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 972 drm_for_each_connector_iter(connector, &conn_iter) { 973 struct intel_encoder *encoder; 974 975 if (connector->connector_type != 976 DRM_MODE_CONNECTOR_DisplayPort) 977 continue; 978 979 encoder = to_intel_encoder(connector->encoder); 980 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 981 continue; 982 983 if (encoder && connector->status == connector_status_connected) { 984 intel_dp = enc_to_intel_dp(encoder); 985 seq_printf(m, "%02lx\n", intel_dp->compliance.test_type); 986 } else 987 seq_puts(m, "0"); 988 } 989 drm_connector_list_iter_end(&conn_iter); 990 991 return 0; 992 } 993 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type); 994 995 static ssize_t 996 i915_fifo_underrun_reset_write(struct file *filp, 997 const char __user *ubuf, 998 size_t cnt, loff_t *ppos) 999 { 1000 struct drm_i915_private *dev_priv = filp->private_data; 1001 struct intel_crtc *crtc; 1002 int ret; 1003 bool reset; 1004 1005 ret = kstrtobool_from_user(ubuf, cnt, &reset); 1006 if (ret) 1007 return ret; 1008 1009 if (!reset) 1010 return cnt; 1011 1012 for_each_intel_crtc(&dev_priv->drm, crtc) { 1013 struct drm_crtc_commit *commit; 1014 struct intel_crtc_state *crtc_state; 1015 1016 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); 1017 if (ret) 1018 return ret; 1019 1020 crtc_state = to_intel_crtc_state(crtc->base.state); 1021 commit = crtc_state->uapi.commit; 1022 if (commit) { 1023 ret = wait_for_completion_interruptible(&commit->hw_done); 1024 if (!ret) 1025 ret = wait_for_completion_interruptible(&commit->flip_done); 1026 } 1027 1028 if (!ret && crtc_state->hw.active) { 1029 drm_dbg_kms(&dev_priv->drm, 1030 "Re-arming FIFO underruns on pipe %c\n", 1031 pipe_name(crtc->pipe)); 1032 1033 intel_crtc_arm_fifo_underrun(crtc, crtc_state); 1034 } 1035 1036 drm_modeset_unlock(&crtc->base.mutex); 1037 1038 if (ret) 1039 return ret; 1040 } 1041 1042 intel_fbc_reset_underrun(dev_priv); 1043 1044 return cnt; 1045 } 1046 1047 static const struct file_operations i915_fifo_underrun_reset_ops = { 1048 .owner = THIS_MODULE, 1049 .open = simple_open, 1050 .write = i915_fifo_underrun_reset_write, 1051 .llseek = default_llseek, 1052 }; 1053 1054 static const struct drm_info_list intel_display_debugfs_list[] = { 1055 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, 1056 {"i915_sr_status", i915_sr_status, 0}, 1057 {"i915_opregion", i915_opregion, 0}, 1058 {"i915_vbt", i915_vbt, 0}, 1059 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, 1060 {"i915_power_domain_info", i915_power_domain_info, 0}, 1061 {"i915_display_info", i915_display_info, 0}, 1062 {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, 1063 {"i915_dp_mst_info", i915_dp_mst_info, 0}, 1064 {"i915_ddb_info", i915_ddb_info, 0}, 1065 {"i915_lpsp_status", i915_lpsp_status, 0}, 1066 }; 1067 1068 static const struct { 1069 const char *name; 1070 const struct file_operations *fops; 1071 } intel_display_debugfs_files[] = { 1072 {"i915_fifo_underrun_reset", &i915_fifo_underrun_reset_ops}, 1073 {"i915_dp_test_data", &i915_displayport_test_data_fops}, 1074 {"i915_dp_test_type", &i915_displayport_test_type_fops}, 1075 {"i915_dp_test_active", &i915_displayport_test_active_fops}, 1076 }; 1077 1078 void intel_display_debugfs_register(struct drm_i915_private *i915) 1079 { 1080 struct drm_minor *minor = i915->drm.primary; 1081 int i; 1082 1083 for (i = 0; i < ARRAY_SIZE(intel_display_debugfs_files); i++) { 1084 debugfs_create_file(intel_display_debugfs_files[i].name, 1085 S_IRUGO | S_IWUSR, 1086 minor->debugfs_root, 1087 to_i915(minor->dev), 1088 intel_display_debugfs_files[i].fops); 1089 } 1090 1091 drm_debugfs_create_files(intel_display_debugfs_list, 1092 ARRAY_SIZE(intel_display_debugfs_list), 1093 minor->debugfs_root, minor); 1094 1095 hsw_ips_debugfs_register(i915); 1096 intel_dmc_debugfs_register(i915); 1097 intel_fbc_debugfs_register(i915); 1098 intel_hpd_debugfs_register(i915); 1099 intel_psr_debugfs_register(i915); 1100 intel_wm_debugfs_register(i915); 1101 } 1102 1103 static int i915_panel_show(struct seq_file *m, void *data) 1104 { 1105 struct drm_connector *connector = m->private; 1106 struct intel_dp *intel_dp = 1107 intel_attached_dp(to_intel_connector(connector)); 1108 1109 if (connector->status != connector_status_connected) 1110 return -ENODEV; 1111 1112 seq_printf(m, "Panel power up delay: %d\n", 1113 intel_dp->pps.panel_power_up_delay); 1114 seq_printf(m, "Panel power down delay: %d\n", 1115 intel_dp->pps.panel_power_down_delay); 1116 seq_printf(m, "Backlight on delay: %d\n", 1117 intel_dp->pps.backlight_on_delay); 1118 seq_printf(m, "Backlight off delay: %d\n", 1119 intel_dp->pps.backlight_off_delay); 1120 1121 return 0; 1122 } 1123 DEFINE_SHOW_ATTRIBUTE(i915_panel); 1124 1125 static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data) 1126 { 1127 struct drm_connector *connector = m->private; 1128 struct drm_i915_private *i915 = to_i915(connector->dev); 1129 struct intel_connector *intel_connector = to_intel_connector(connector); 1130 int ret; 1131 1132 ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1133 if (ret) 1134 return ret; 1135 1136 if (!connector->encoder || connector->status != connector_status_connected) { 1137 ret = -ENODEV; 1138 goto out; 1139 } 1140 1141 seq_printf(m, "%s:%d HDCP version: ", connector->name, 1142 connector->base.id); 1143 intel_hdcp_info(m, intel_connector); 1144 1145 out: 1146 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1147 1148 return ret; 1149 } 1150 DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability); 1151 1152 static int i915_lpsp_capability_show(struct seq_file *m, void *data) 1153 { 1154 struct drm_connector *connector = m->private; 1155 struct drm_i915_private *i915 = to_i915(connector->dev); 1156 struct intel_encoder *encoder; 1157 bool lpsp_capable = false; 1158 1159 encoder = intel_attached_encoder(to_intel_connector(connector)); 1160 if (!encoder) 1161 return -ENODEV; 1162 1163 if (connector->status != connector_status_connected) 1164 return -ENODEV; 1165 1166 if (DISPLAY_VER(i915) >= 13) 1167 lpsp_capable = encoder->port <= PORT_B; 1168 else if (DISPLAY_VER(i915) >= 12) 1169 /* 1170 * Actually TGL can drive LPSP on port till DDI_C 1171 * but there is no physical connected DDI_C on TGL sku's, 1172 * even driver is not initilizing DDI_C port for gen12. 1173 */ 1174 lpsp_capable = encoder->port <= PORT_B; 1175 else if (DISPLAY_VER(i915) == 11) 1176 lpsp_capable = (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 1177 connector->connector_type == DRM_MODE_CONNECTOR_eDP); 1178 else if (IS_DISPLAY_VER(i915, 9, 10)) 1179 lpsp_capable = (encoder->port == PORT_A && 1180 (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 1181 connector->connector_type == DRM_MODE_CONNECTOR_eDP || 1182 connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)); 1183 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 1184 lpsp_capable = connector->connector_type == DRM_MODE_CONNECTOR_eDP; 1185 1186 seq_printf(m, "LPSP: %s\n", lpsp_capable ? "capable" : "incapable"); 1187 1188 return 0; 1189 } 1190 DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability); 1191 1192 static int i915_dsc_fec_support_show(struct seq_file *m, void *data) 1193 { 1194 struct drm_connector *connector = m->private; 1195 struct drm_device *dev = connector->dev; 1196 struct drm_crtc *crtc; 1197 struct intel_dp *intel_dp; 1198 struct drm_modeset_acquire_ctx ctx; 1199 struct intel_crtc_state *crtc_state = NULL; 1200 int ret = 0; 1201 bool try_again = false; 1202 1203 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1204 1205 do { 1206 try_again = false; 1207 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, 1208 &ctx); 1209 if (ret) { 1210 if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) { 1211 try_again = true; 1212 continue; 1213 } 1214 break; 1215 } 1216 crtc = connector->state->crtc; 1217 if (connector->status != connector_status_connected || !crtc) { 1218 ret = -ENODEV; 1219 break; 1220 } 1221 ret = drm_modeset_lock(&crtc->mutex, &ctx); 1222 if (ret == -EDEADLK) { 1223 ret = drm_modeset_backoff(&ctx); 1224 if (!ret) { 1225 try_again = true; 1226 continue; 1227 } 1228 break; 1229 } else if (ret) { 1230 break; 1231 } 1232 intel_dp = intel_attached_dp(to_intel_connector(connector)); 1233 crtc_state = to_intel_crtc_state(crtc->state); 1234 seq_printf(m, "DSC_Enabled: %s\n", 1235 str_yes_no(crtc_state->dsc.compression_enable)); 1236 seq_printf(m, "DSC_Sink_Support: %s\n", 1237 str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))); 1238 seq_printf(m, "Force_DSC_Enable: %s\n", 1239 str_yes_no(intel_dp->force_dsc_en)); 1240 if (!intel_dp_is_edp(intel_dp)) 1241 seq_printf(m, "FEC_Sink_Support: %s\n", 1242 str_yes_no(drm_dp_sink_supports_fec(intel_dp->fec_capable))); 1243 } while (try_again); 1244 1245 drm_modeset_drop_locks(&ctx); 1246 drm_modeset_acquire_fini(&ctx); 1247 1248 return ret; 1249 } 1250 1251 static ssize_t i915_dsc_fec_support_write(struct file *file, 1252 const char __user *ubuf, 1253 size_t len, loff_t *offp) 1254 { 1255 bool dsc_enable = false; 1256 int ret; 1257 struct drm_connector *connector = 1258 ((struct seq_file *)file->private_data)->private; 1259 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 1260 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1261 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1262 1263 if (len == 0) 1264 return 0; 1265 1266 drm_dbg(&i915->drm, 1267 "Copied %zu bytes from user to force DSC\n", len); 1268 1269 ret = kstrtobool_from_user(ubuf, len, &dsc_enable); 1270 if (ret < 0) 1271 return ret; 1272 1273 drm_dbg(&i915->drm, "Got %s for DSC Enable\n", 1274 (dsc_enable) ? "true" : "false"); 1275 intel_dp->force_dsc_en = dsc_enable; 1276 1277 *offp += len; 1278 return len; 1279 } 1280 1281 static int i915_dsc_fec_support_open(struct inode *inode, 1282 struct file *file) 1283 { 1284 return single_open(file, i915_dsc_fec_support_show, 1285 inode->i_private); 1286 } 1287 1288 static const struct file_operations i915_dsc_fec_support_fops = { 1289 .owner = THIS_MODULE, 1290 .open = i915_dsc_fec_support_open, 1291 .read = seq_read, 1292 .llseek = seq_lseek, 1293 .release = single_release, 1294 .write = i915_dsc_fec_support_write 1295 }; 1296 1297 static int i915_dsc_bpc_show(struct seq_file *m, void *data) 1298 { 1299 struct drm_connector *connector = m->private; 1300 struct drm_device *dev = connector->dev; 1301 struct drm_crtc *crtc; 1302 struct intel_crtc_state *crtc_state; 1303 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 1304 int ret; 1305 1306 if (!encoder) 1307 return -ENODEV; 1308 1309 ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex); 1310 if (ret) 1311 return ret; 1312 1313 crtc = connector->state->crtc; 1314 if (connector->status != connector_status_connected || !crtc) { 1315 ret = -ENODEV; 1316 goto out; 1317 } 1318 1319 crtc_state = to_intel_crtc_state(crtc->state); 1320 seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component); 1321 1322 out: drm_modeset_unlock(&dev->mode_config.connection_mutex); 1323 1324 return ret; 1325 } 1326 1327 static ssize_t i915_dsc_bpc_write(struct file *file, 1328 const char __user *ubuf, 1329 size_t len, loff_t *offp) 1330 { 1331 struct drm_connector *connector = 1332 ((struct seq_file *)file->private_data)->private; 1333 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 1334 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1335 int dsc_bpc = 0; 1336 int ret; 1337 1338 ret = kstrtoint_from_user(ubuf, len, 0, &dsc_bpc); 1339 if (ret < 0) 1340 return ret; 1341 1342 intel_dp->force_dsc_bpc = dsc_bpc; 1343 *offp += len; 1344 1345 return len; 1346 } 1347 1348 static int i915_dsc_bpc_open(struct inode *inode, 1349 struct file *file) 1350 { 1351 return single_open(file, i915_dsc_bpc_show, inode->i_private); 1352 } 1353 1354 static const struct file_operations i915_dsc_bpc_fops = { 1355 .owner = THIS_MODULE, 1356 .open = i915_dsc_bpc_open, 1357 .read = seq_read, 1358 .llseek = seq_lseek, 1359 .release = single_release, 1360 .write = i915_dsc_bpc_write 1361 }; 1362 1363 /* 1364 * Returns the Current CRTC's bpc. 1365 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc 1366 */ 1367 static int i915_current_bpc_show(struct seq_file *m, void *data) 1368 { 1369 struct intel_crtc *crtc = m->private; 1370 struct intel_crtc_state *crtc_state; 1371 int ret; 1372 1373 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); 1374 if (ret) 1375 return ret; 1376 1377 crtc_state = to_intel_crtc_state(crtc->base.state); 1378 seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3); 1379 1380 drm_modeset_unlock(&crtc->base.mutex); 1381 1382 return ret; 1383 } 1384 DEFINE_SHOW_ATTRIBUTE(i915_current_bpc); 1385 1386 /* Pipe may differ from crtc index if pipes are fused off */ 1387 static int intel_crtc_pipe_show(struct seq_file *m, void *unused) 1388 { 1389 struct intel_crtc *crtc = m->private; 1390 1391 seq_printf(m, "%c\n", pipe_name(crtc->pipe)); 1392 1393 return 0; 1394 } 1395 DEFINE_SHOW_ATTRIBUTE(intel_crtc_pipe); 1396 1397 /** 1398 * intel_connector_debugfs_add - add i915 specific connector debugfs files 1399 * @connector: pointer to a registered drm_connector 1400 * 1401 * Cleanup will be done by drm_connector_unregister() through a call to 1402 * drm_debugfs_connector_remove(). 1403 */ 1404 void intel_connector_debugfs_add(struct intel_connector *intel_connector) 1405 { 1406 struct drm_connector *connector = &intel_connector->base; 1407 struct dentry *root = connector->debugfs_entry; 1408 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1409 1410 /* The connector must have been registered beforehands. */ 1411 if (!root) 1412 return; 1413 1414 intel_drrs_connector_debugfs_add(intel_connector); 1415 intel_psr_connector_debugfs_add(intel_connector); 1416 1417 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 1418 debugfs_create_file("i915_panel_timings", S_IRUGO, root, 1419 connector, &i915_panel_fops); 1420 1421 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1422 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 1423 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) { 1424 debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root, 1425 connector, &i915_hdcp_sink_capability_fops); 1426 } 1427 1428 if (DISPLAY_VER(dev_priv) >= 11 && 1429 ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && 1430 !to_intel_connector(connector)->mst_port) || 1431 connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 1432 debugfs_create_file("i915_dsc_fec_support", 0644, root, 1433 connector, &i915_dsc_fec_support_fops); 1434 1435 debugfs_create_file("i915_dsc_bpc", 0644, root, 1436 connector, &i915_dsc_bpc_fops); 1437 } 1438 1439 if (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 1440 connector->connector_type == DRM_MODE_CONNECTOR_eDP || 1441 connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1442 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 1443 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 1444 debugfs_create_file("i915_lpsp_capability", 0444, root, 1445 connector, &i915_lpsp_capability_fops); 1446 } 1447 1448 /** 1449 * intel_crtc_debugfs_add - add i915 specific crtc debugfs files 1450 * @crtc: pointer to a drm_crtc 1451 * 1452 * Failure to add debugfs entries should generally be ignored. 1453 */ 1454 void intel_crtc_debugfs_add(struct intel_crtc *crtc) 1455 { 1456 struct dentry *root = crtc->base.debugfs_entry; 1457 1458 if (!root) 1459 return; 1460 1461 crtc_updates_add(crtc); 1462 intel_drrs_crtc_debugfs_add(crtc); 1463 intel_fbc_crtc_debugfs_add(crtc); 1464 1465 debugfs_create_file("i915_current_bpc", 0444, root, crtc, 1466 &i915_current_bpc_fops); 1467 debugfs_create_file("i915_pipe", 0444, root, crtc, 1468 &intel_crtc_pipe_fops); 1469 } 1470