1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef __INTEL_DISPLAY_CORE_H__
7 #define __INTEL_DISPLAY_CORE_H__
8 
9 #include <linux/list.h>
10 #include <linux/llist.h>
11 #include <linux/mutex.h>
12 #include <linux/types.h>
13 #include <linux/wait.h>
14 #include <linux/workqueue.h>
15 
16 #include <drm/drm_connector.h>
17 #include <drm/drm_modeset_lock.h>
18 
19 #include "intel_cdclk.h"
20 #include "intel_display_limits.h"
21 #include "intel_display_power.h"
22 #include "intel_dmc.h"
23 #include "intel_dpll_mgr.h"
24 #include "intel_fbc.h"
25 #include "intel_global_state.h"
26 #include "intel_gmbus.h"
27 #include "intel_opregion.h"
28 #include "intel_pm_types.h"
29 
30 struct drm_i915_private;
31 struct drm_property;
32 struct drm_property_blob;
33 struct i915_audio_component;
34 struct i915_hdcp_comp_master;
35 struct intel_atomic_state;
36 struct intel_audio_funcs;
37 struct intel_bios_encoder_data;
38 struct intel_cdclk_funcs;
39 struct intel_cdclk_vals;
40 struct intel_color_funcs;
41 struct intel_crtc;
42 struct intel_crtc_state;
43 struct intel_dpll_funcs;
44 struct intel_dpll_mgr;
45 struct intel_fbdev;
46 struct intel_fdi_funcs;
47 struct intel_hotplug_funcs;
48 struct intel_initial_plane_config;
49 struct intel_overlay;
50 
51 /* Amount of SAGV/QGV points, BSpec precisely defines this */
52 #define I915_NUM_QGV_POINTS 8
53 
54 /* Amount of PSF GV points, BSpec precisely defines this */
55 #define I915_NUM_PSF_GV_POINTS 3
56 
57 struct intel_display_funcs {
58 	/*
59 	 * Returns the active state of the crtc, and if the crtc is active,
60 	 * fills out the pipe-config with the hw state.
61 	 */
62 	bool (*get_pipe_config)(struct intel_crtc *,
63 				struct intel_crtc_state *);
64 	void (*get_initial_plane_config)(struct intel_crtc *,
65 					 struct intel_initial_plane_config *);
66 	void (*crtc_enable)(struct intel_atomic_state *state,
67 			    struct intel_crtc *crtc);
68 	void (*crtc_disable)(struct intel_atomic_state *state,
69 			     struct intel_crtc *crtc);
70 	void (*commit_modeset_enables)(struct intel_atomic_state *state);
71 };
72 
73 /* functions used for watermark calcs for display. */
74 struct intel_wm_funcs {
75 	/* update_wm is for legacy wm management */
76 	void (*update_wm)(struct drm_i915_private *dev_priv);
77 	int (*compute_pipe_wm)(struct intel_atomic_state *state,
78 			       struct intel_crtc *crtc);
79 	int (*compute_intermediate_wm)(struct intel_atomic_state *state,
80 				       struct intel_crtc *crtc);
81 	void (*initial_watermarks)(struct intel_atomic_state *state,
82 				   struct intel_crtc *crtc);
83 	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
84 					 struct intel_crtc *crtc);
85 	void (*optimize_watermarks)(struct intel_atomic_state *state,
86 				    struct intel_crtc *crtc);
87 	int (*compute_global_watermarks)(struct intel_atomic_state *state);
88 };
89 
90 struct intel_audio_state {
91 	struct intel_encoder *encoder;
92 	u8 eld[MAX_ELD_BYTES];
93 };
94 
95 struct intel_audio {
96 	/* hda/i915 audio component */
97 	struct i915_audio_component *component;
98 	bool component_registered;
99 	/* mutex for audio/video sync */
100 	struct mutex mutex;
101 	int power_refcount;
102 	u32 freq_cntrl;
103 
104 	/* current audio state for the audio component hooks */
105 	struct intel_audio_state state[I915_MAX_PIPES];
106 
107 	/* necessary resource sharing with HDMI LPE audio driver. */
108 	struct {
109 		struct platform_device *platdev;
110 		int irq;
111 	} lpe;
112 };
113 
114 /*
115  * dpll and cdclk state is protected by connection_mutex dpll.lock serializes
116  * intel_{prepare,enable,disable}_shared_dpll.  Must be global rather than per
117  * dpll, because on some platforms plls share registers.
118  */
119 struct intel_dpll {
120 	struct mutex lock;
121 
122 	int num_shared_dpll;
123 	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
124 	const struct intel_dpll_mgr *mgr;
125 
126 	struct {
127 		int nssc;
128 		int ssc;
129 	} ref_clks;
130 
131 	/*
132 	 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id.
133 	 */
134 	u8 pch_ssc_use;
135 };
136 
137 struct intel_frontbuffer_tracking {
138 	spinlock_t lock;
139 
140 	/*
141 	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
142 	 * scheduled flips.
143 	 */
144 	unsigned busy_bits;
145 	unsigned flip_bits;
146 };
147 
148 struct intel_hotplug {
149 	struct delayed_work hotplug_work;
150 
151 	const u32 *hpd, *pch_hpd;
152 
153 	struct {
154 		unsigned long last_jiffies;
155 		int count;
156 		enum {
157 			HPD_ENABLED = 0,
158 			HPD_DISABLED = 1,
159 			HPD_MARK_DISABLED = 2
160 		} state;
161 	} stats[HPD_NUM_PINS];
162 	u32 event_bits;
163 	u32 retry_bits;
164 	struct delayed_work reenable_work;
165 
166 	u32 long_port_mask;
167 	u32 short_port_mask;
168 	struct work_struct dig_port_work;
169 
170 	struct work_struct poll_init_work;
171 	bool poll_enabled;
172 
173 	unsigned int hpd_storm_threshold;
174 	/* Whether or not to count short HPD IRQs in HPD storms */
175 	u8 hpd_short_storm_enabled;
176 
177 	/*
178 	 * if we get a HPD irq from DP and a HPD irq from non-DP
179 	 * the non-DP HPD could block the workqueue on a mode config
180 	 * mutex getting, that userspace may have taken. However
181 	 * userspace is waiting on the DP workqueue to run which is
182 	 * blocked behind the non-DP one.
183 	 */
184 	struct workqueue_struct *dp_wq;
185 };
186 
187 struct intel_vbt_data {
188 	/* bdb version */
189 	u16 version;
190 
191 	/* Feature bits */
192 	unsigned int int_tv_support:1;
193 	unsigned int int_crt_support:1;
194 	unsigned int lvds_use_ssc:1;
195 	unsigned int int_lvds_support:1;
196 	unsigned int display_clock_mode:1;
197 	unsigned int fdi_rx_polarity_inverted:1;
198 	int lvds_ssc_freq;
199 	enum drm_panel_orientation orientation;
200 
201 	bool override_afc_startup;
202 	u8 override_afc_startup_val;
203 
204 	int crt_ddc_pin;
205 
206 	struct list_head display_devices;
207 	struct list_head bdb_blocks;
208 
209 	struct intel_bios_encoder_data *ports[I915_MAX_PORTS]; /* Non-NULL if port present. */
210 	struct sdvo_device_mapping {
211 		u8 initialized;
212 		u8 dvo_port;
213 		u8 slave_addr;
214 		u8 dvo_wiring;
215 		u8 i2c_pin;
216 		u8 ddc_pin;
217 	} sdvo_mappings[2];
218 };
219 
220 struct intel_wm {
221 	/*
222 	 * Raw watermark latency values:
223 	 * in 0.1us units for WM0,
224 	 * in 0.5us units for WM1+.
225 	 */
226 	/* primary */
227 	u16 pri_latency[5];
228 	/* sprite */
229 	u16 spr_latency[5];
230 	/* cursor */
231 	u16 cur_latency[5];
232 	/*
233 	 * Raw watermark memory latency values
234 	 * for SKL for all 8 levels
235 	 * in 1us units.
236 	 */
237 	u16 skl_latency[8];
238 
239 	/* current hardware state */
240 	union {
241 		struct ilk_wm_values hw;
242 		struct vlv_wm_values vlv;
243 		struct g4x_wm_values g4x;
244 	};
245 
246 	u8 max_level;
247 
248 	/*
249 	 * Should be held around atomic WM register writing; also
250 	 * protects * intel_crtc->wm.active and
251 	 * crtc_state->wm.need_postvbl_update.
252 	 */
253 	struct mutex wm_mutex;
254 
255 	bool ipc_enabled;
256 };
257 
258 struct intel_display {
259 	/* Display functions */
260 	struct {
261 		/* Top level crtc-ish functions */
262 		const struct intel_display_funcs *display;
263 
264 		/* Display CDCLK functions */
265 		const struct intel_cdclk_funcs *cdclk;
266 
267 		/* Display pll funcs */
268 		const struct intel_dpll_funcs *dpll;
269 
270 		/* irq display functions */
271 		const struct intel_hotplug_funcs *hotplug;
272 
273 		/* pm display functions */
274 		const struct intel_wm_funcs *wm;
275 
276 		/* fdi display functions */
277 		const struct intel_fdi_funcs *fdi;
278 
279 		/* Display internal color functions */
280 		const struct intel_color_funcs *color;
281 
282 		/* Display internal audio functions */
283 		const struct intel_audio_funcs *audio;
284 	} funcs;
285 
286 	/* Grouping using anonymous structs. Keep sorted. */
287 	struct intel_atomic_helper {
288 		struct llist_head free_list;
289 		struct work_struct free_work;
290 	} atomic_helper;
291 
292 	struct {
293 		/* backlight registers and fields in struct intel_panel */
294 		struct mutex lock;
295 	} backlight;
296 
297 	struct {
298 		struct intel_global_obj obj;
299 
300 		struct intel_bw_info {
301 			/* for each QGV point */
302 			unsigned int deratedbw[I915_NUM_QGV_POINTS];
303 			/* for each PSF GV point */
304 			unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
305 			u8 num_qgv_points;
306 			u8 num_psf_gv_points;
307 			u8 num_planes;
308 		} max[6];
309 	} bw;
310 
311 	struct {
312 		/* The current hardware cdclk configuration */
313 		struct intel_cdclk_config hw;
314 
315 		/* cdclk, divider, and ratio table from bspec */
316 		const struct intel_cdclk_vals *table;
317 
318 		struct intel_global_obj obj;
319 
320 		unsigned int max_cdclk_freq;
321 	} cdclk;
322 
323 	struct {
324 		struct drm_property_blob *glk_linear_degamma_lut;
325 	} color;
326 
327 	struct {
328 		/* The current hardware dbuf configuration */
329 		u8 enabled_slices;
330 
331 		struct intel_global_obj obj;
332 	} dbuf;
333 
334 	struct {
335 		/*
336 		 * dkl.phy_lock protects against concurrent access of the
337 		 * Dekel TypeC PHYs.
338 		 */
339 		spinlock_t phy_lock;
340 	} dkl;
341 
342 	struct {
343 		/* VLV/CHV/BXT/GLK DSI MMIO register base address */
344 		u32 mmio_base;
345 	} dsi;
346 
347 	struct {
348 		/* list of fbdev register on this device */
349 		struct intel_fbdev *fbdev;
350 		struct work_struct suspend_work;
351 	} fbdev;
352 
353 	struct {
354 		unsigned int pll_freq;
355 		u32 rx_config;
356 	} fdi;
357 
358 	struct {
359 		struct list_head obj_list;
360 	} global;
361 
362 	struct {
363 		/*
364 		 * Base address of where the gmbus and gpio blocks are located
365 		 * (either on PCH or on SoC for platforms without PCH).
366 		 */
367 		u32 mmio_base;
368 
369 		/*
370 		 * gmbus.mutex protects against concurrent usage of the single
371 		 * hw gmbus controller on different i2c buses.
372 		 */
373 		struct mutex mutex;
374 
375 		struct intel_gmbus *bus[GMBUS_NUM_PINS];
376 
377 		wait_queue_head_t wait_queue;
378 	} gmbus;
379 
380 	struct {
381 		struct i915_hdcp_comp_master *master;
382 		bool comp_added;
383 
384 		/* Mutex to protect the above hdcp component related values. */
385 		struct mutex comp_mutex;
386 	} hdcp;
387 
388 	struct {
389 		/*
390 		 * HTI (aka HDPORT) state read during initial hw readout. Most
391 		 * platforms don't have HTI, so this will just stay 0. Those
392 		 * that do will use this later to figure out which PLLs and PHYs
393 		 * are unavailable for driver usage.
394 		 */
395 		u32 state;
396 	} hti;
397 
398 	struct {
399 		struct i915_power_domains domains;
400 
401 		/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
402 		u32 chv_phy_control;
403 
404 		/* perform PHY state sanity checks? */
405 		bool chv_phy_assert[2];
406 	} power;
407 
408 	struct {
409 		u32 mmio_base;
410 
411 		/* protects panel power sequencer state */
412 		struct mutex mutex;
413 	} pps;
414 
415 	struct {
416 		struct drm_property *broadcast_rgb;
417 		struct drm_property *force_audio;
418 	} properties;
419 
420 	struct {
421 		unsigned long mask;
422 	} quirks;
423 
424 	struct {
425 		/* restore state for suspend/resume and display reset */
426 		struct drm_atomic_state *modeset_state;
427 		struct drm_modeset_acquire_ctx reset_ctx;
428 	} restore;
429 
430 	struct {
431 		enum {
432 			I915_SAGV_UNKNOWN = 0,
433 			I915_SAGV_DISABLED,
434 			I915_SAGV_ENABLED,
435 			I915_SAGV_NOT_CONTROLLED
436 		} status;
437 
438 		u32 block_time_us;
439 	} sagv;
440 
441 	struct {
442 		/*
443 		 * DG2: Mask of PHYs that were not calibrated by the firmware
444 		 * and should not be used.
445 		 */
446 		u8 phy_failed_calibration;
447 	} snps;
448 
449 	struct {
450 		/*
451 		 * Shadows for CHV DPLL_MD regs to keep the state
452 		 * checker somewhat working in the presence hardware
453 		 * crappiness (can't read out DPLL_MD for pipes B & C).
454 		 */
455 		u32 chv_dpll_md[I915_MAX_PIPES];
456 		u32 bxt_phy_grc;
457 	} state;
458 
459 	struct {
460 		/* ordered wq for modesets */
461 		struct workqueue_struct *modeset;
462 
463 		/* unbound hipri wq for page flips/plane updates */
464 		struct workqueue_struct *flip;
465 	} wq;
466 
467 	/* Grouping using named structs. Keep sorted. */
468 	struct intel_audio audio;
469 	struct intel_dmc dmc;
470 	struct intel_dpll dpll;
471 	struct intel_fbc *fbc[I915_MAX_FBCS];
472 	struct intel_frontbuffer_tracking fb_tracking;
473 	struct intel_hotplug hotplug;
474 	struct intel_opregion opregion;
475 	struct intel_overlay *overlay;
476 	struct intel_vbt_data vbt;
477 	struct intel_wm wm;
478 };
479 
480 #endif /* __INTEL_DISPLAY_CORE_H__ */
481