1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef __INTEL_DISPLAY_CORE_H__
7 #define __INTEL_DISPLAY_CORE_H__
8 
9 #include <linux/list.h>
10 #include <linux/llist.h>
11 #include <linux/mutex.h>
12 #include <linux/types.h>
13 #include <linux/wait.h>
14 #include <linux/workqueue.h>
15 
16 #include <drm/drm_connector.h>
17 #include <drm/drm_modeset_lock.h>
18 
19 #include "intel_cdclk.h"
20 #include "intel_display.h"
21 #include "intel_display_power.h"
22 #include "intel_dmc.h"
23 #include "intel_dpll_mgr.h"
24 #include "intel_fbc.h"
25 #include "intel_global_state.h"
26 #include "intel_gmbus.h"
27 #include "intel_opregion.h"
28 #include "intel_pm_types.h"
29 
30 struct drm_i915_private;
31 struct drm_property;
32 struct drm_property_blob;
33 struct i915_audio_component;
34 struct i915_hdcp_comp_master;
35 struct intel_atomic_state;
36 struct intel_audio_funcs;
37 struct intel_bios_encoder_data;
38 struct intel_cdclk_funcs;
39 struct intel_cdclk_vals;
40 struct intel_color_funcs;
41 struct intel_crtc;
42 struct intel_crtc_state;
43 struct intel_dpll_funcs;
44 struct intel_dpll_mgr;
45 struct intel_fbdev;
46 struct intel_fdi_funcs;
47 struct intel_hotplug_funcs;
48 struct intel_initial_plane_config;
49 struct intel_overlay;
50 
51 /* Amount of SAGV/QGV points, BSpec precisely defines this */
52 #define I915_NUM_QGV_POINTS 8
53 
54 /* Amount of PSF GV points, BSpec precisely defines this */
55 #define I915_NUM_PSF_GV_POINTS 3
56 
57 struct intel_display_funcs {
58 	/*
59 	 * Returns the active state of the crtc, and if the crtc is active,
60 	 * fills out the pipe-config with the hw state.
61 	 */
62 	bool (*get_pipe_config)(struct intel_crtc *,
63 				struct intel_crtc_state *);
64 	void (*get_initial_plane_config)(struct intel_crtc *,
65 					 struct intel_initial_plane_config *);
66 	void (*crtc_enable)(struct intel_atomic_state *state,
67 			    struct intel_crtc *crtc);
68 	void (*crtc_disable)(struct intel_atomic_state *state,
69 			     struct intel_crtc *crtc);
70 	void (*commit_modeset_enables)(struct intel_atomic_state *state);
71 };
72 
73 /* functions used for watermark calcs for display. */
74 struct intel_wm_funcs {
75 	/* update_wm is for legacy wm management */
76 	void (*update_wm)(struct drm_i915_private *dev_priv);
77 	int (*compute_pipe_wm)(struct intel_atomic_state *state,
78 			       struct intel_crtc *crtc);
79 	int (*compute_intermediate_wm)(struct intel_atomic_state *state,
80 				       struct intel_crtc *crtc);
81 	void (*initial_watermarks)(struct intel_atomic_state *state,
82 				   struct intel_crtc *crtc);
83 	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
84 					 struct intel_crtc *crtc);
85 	void (*optimize_watermarks)(struct intel_atomic_state *state,
86 				    struct intel_crtc *crtc);
87 	int (*compute_global_watermarks)(struct intel_atomic_state *state);
88 };
89 
90 struct intel_audio {
91 	/* hda/i915 audio component */
92 	struct i915_audio_component *component;
93 	bool component_registered;
94 	/* mutex for audio/video sync */
95 	struct mutex mutex;
96 	int power_refcount;
97 	u32 freq_cntrl;
98 
99 	/* Used to save the pipe-to-encoder mapping for audio */
100 	struct intel_encoder *encoder_map[I915_MAX_PIPES];
101 
102 	/* necessary resource sharing with HDMI LPE audio driver. */
103 	struct {
104 		struct platform_device *platdev;
105 		int irq;
106 	} lpe;
107 };
108 
109 /*
110  * dpll and cdclk state is protected by connection_mutex dpll.lock serializes
111  * intel_{prepare,enable,disable}_shared_dpll.  Must be global rather than per
112  * dpll, because on some platforms plls share registers.
113  */
114 struct intel_dpll {
115 	struct mutex lock;
116 
117 	int num_shared_dpll;
118 	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
119 	const struct intel_dpll_mgr *mgr;
120 
121 	struct {
122 		int nssc;
123 		int ssc;
124 	} ref_clks;
125 };
126 
127 struct intel_frontbuffer_tracking {
128 	spinlock_t lock;
129 
130 	/*
131 	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
132 	 * scheduled flips.
133 	 */
134 	unsigned busy_bits;
135 	unsigned flip_bits;
136 };
137 
138 struct intel_hotplug {
139 	struct delayed_work hotplug_work;
140 
141 	const u32 *hpd, *pch_hpd;
142 
143 	struct {
144 		unsigned long last_jiffies;
145 		int count;
146 		enum {
147 			HPD_ENABLED = 0,
148 			HPD_DISABLED = 1,
149 			HPD_MARK_DISABLED = 2
150 		} state;
151 	} stats[HPD_NUM_PINS];
152 	u32 event_bits;
153 	u32 retry_bits;
154 	struct delayed_work reenable_work;
155 
156 	u32 long_port_mask;
157 	u32 short_port_mask;
158 	struct work_struct dig_port_work;
159 
160 	struct work_struct poll_init_work;
161 	bool poll_enabled;
162 
163 	unsigned int hpd_storm_threshold;
164 	/* Whether or not to count short HPD IRQs in HPD storms */
165 	u8 hpd_short_storm_enabled;
166 
167 	/*
168 	 * if we get a HPD irq from DP and a HPD irq from non-DP
169 	 * the non-DP HPD could block the workqueue on a mode config
170 	 * mutex getting, that userspace may have taken. However
171 	 * userspace is waiting on the DP workqueue to run which is
172 	 * blocked behind the non-DP one.
173 	 */
174 	struct workqueue_struct *dp_wq;
175 };
176 
177 struct intel_vbt_data {
178 	/* bdb version */
179 	u16 version;
180 
181 	/* Feature bits */
182 	unsigned int int_tv_support:1;
183 	unsigned int int_crt_support:1;
184 	unsigned int lvds_use_ssc:1;
185 	unsigned int int_lvds_support:1;
186 	unsigned int display_clock_mode:1;
187 	unsigned int fdi_rx_polarity_inverted:1;
188 	int lvds_ssc_freq;
189 	enum drm_panel_orientation orientation;
190 
191 	bool override_afc_startup;
192 	u8 override_afc_startup_val;
193 
194 	int crt_ddc_pin;
195 
196 	struct list_head display_devices;
197 	struct list_head bdb_blocks;
198 
199 	struct intel_bios_encoder_data *ports[I915_MAX_PORTS]; /* Non-NULL if port present. */
200 	struct sdvo_device_mapping {
201 		u8 initialized;
202 		u8 dvo_port;
203 		u8 slave_addr;
204 		u8 dvo_wiring;
205 		u8 i2c_pin;
206 		u8 ddc_pin;
207 	} sdvo_mappings[2];
208 };
209 
210 struct intel_wm {
211 	/*
212 	 * Raw watermark latency values:
213 	 * in 0.1us units for WM0,
214 	 * in 0.5us units for WM1+.
215 	 */
216 	/* primary */
217 	u16 pri_latency[5];
218 	/* sprite */
219 	u16 spr_latency[5];
220 	/* cursor */
221 	u16 cur_latency[5];
222 	/*
223 	 * Raw watermark memory latency values
224 	 * for SKL for all 8 levels
225 	 * in 1us units.
226 	 */
227 	u16 skl_latency[8];
228 
229 	/* current hardware state */
230 	union {
231 		struct ilk_wm_values hw;
232 		struct vlv_wm_values vlv;
233 		struct g4x_wm_values g4x;
234 	};
235 
236 	u8 max_level;
237 
238 	/*
239 	 * Should be held around atomic WM register writing; also
240 	 * protects * intel_crtc->wm.active and
241 	 * crtc_state->wm.need_postvbl_update.
242 	 */
243 	struct mutex wm_mutex;
244 
245 	bool ipc_enabled;
246 };
247 
248 struct intel_display {
249 	/* Display functions */
250 	struct {
251 		/* Top level crtc-ish functions */
252 		const struct intel_display_funcs *display;
253 
254 		/* Display CDCLK functions */
255 		const struct intel_cdclk_funcs *cdclk;
256 
257 		/* Display pll funcs */
258 		const struct intel_dpll_funcs *dpll;
259 
260 		/* irq display functions */
261 		const struct intel_hotplug_funcs *hotplug;
262 
263 		/* pm display functions */
264 		const struct intel_wm_funcs *wm;
265 
266 		/* fdi display functions */
267 		const struct intel_fdi_funcs *fdi;
268 
269 		/* Display internal color functions */
270 		const struct intel_color_funcs *color;
271 
272 		/* Display internal audio functions */
273 		const struct intel_audio_funcs *audio;
274 	} funcs;
275 
276 	/* Grouping using anonymous structs. Keep sorted. */
277 	struct intel_atomic_helper {
278 		struct llist_head free_list;
279 		struct work_struct free_work;
280 	} atomic_helper;
281 
282 	struct {
283 		/* backlight registers and fields in struct intel_panel */
284 		struct mutex lock;
285 	} backlight;
286 
287 	struct {
288 		struct intel_global_obj obj;
289 
290 		struct intel_bw_info {
291 			/* for each QGV point */
292 			unsigned int deratedbw[I915_NUM_QGV_POINTS];
293 			/* for each PSF GV point */
294 			unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
295 			u8 num_qgv_points;
296 			u8 num_psf_gv_points;
297 			u8 num_planes;
298 		} max[6];
299 	} bw;
300 
301 	struct {
302 		/* The current hardware cdclk configuration */
303 		struct intel_cdclk_config hw;
304 
305 		/* cdclk, divider, and ratio table from bspec */
306 		const struct intel_cdclk_vals *table;
307 
308 		struct intel_global_obj obj;
309 
310 		unsigned int max_cdclk_freq;
311 	} cdclk;
312 
313 	struct {
314 		struct drm_property_blob *glk_linear_degamma_lut;
315 	} color;
316 
317 	struct {
318 		/* The current hardware dbuf configuration */
319 		u8 enabled_slices;
320 
321 		struct intel_global_obj obj;
322 	} dbuf;
323 
324 	struct {
325 		/*
326 		 * dkl.phy_lock protects against concurrent access of the
327 		 * Dekel TypeC PHYs.
328 		 */
329 		spinlock_t phy_lock;
330 	} dkl;
331 
332 	struct {
333 		/* VLV/CHV/BXT/GLK DSI MMIO register base address */
334 		u32 mmio_base;
335 	} dsi;
336 
337 	struct {
338 		/* list of fbdev register on this device */
339 		struct intel_fbdev *fbdev;
340 		struct work_struct suspend_work;
341 	} fbdev;
342 
343 	struct {
344 		unsigned int pll_freq;
345 		u32 rx_config;
346 	} fdi;
347 
348 	struct {
349 		struct list_head obj_list;
350 	} global;
351 
352 	struct {
353 		/*
354 		 * Base address of where the gmbus and gpio blocks are located
355 		 * (either on PCH or on SoC for platforms without PCH).
356 		 */
357 		u32 mmio_base;
358 
359 		/*
360 		 * gmbus.mutex protects against concurrent usage of the single
361 		 * hw gmbus controller on different i2c buses.
362 		 */
363 		struct mutex mutex;
364 
365 		struct intel_gmbus *bus[GMBUS_NUM_PINS];
366 
367 		wait_queue_head_t wait_queue;
368 	} gmbus;
369 
370 	struct {
371 		struct i915_hdcp_comp_master *master;
372 		bool comp_added;
373 
374 		/* Mutex to protect the above hdcp component related values. */
375 		struct mutex comp_mutex;
376 	} hdcp;
377 
378 	struct {
379 		/*
380 		 * HTI (aka HDPORT) state read during initial hw readout. Most
381 		 * platforms don't have HTI, so this will just stay 0. Those
382 		 * that do will use this later to figure out which PLLs and PHYs
383 		 * are unavailable for driver usage.
384 		 */
385 		u32 state;
386 	} hti;
387 
388 	struct {
389 		struct i915_power_domains domains;
390 
391 		/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
392 		u32 chv_phy_control;
393 
394 		/* perform PHY state sanity checks? */
395 		bool chv_phy_assert[2];
396 	} power;
397 
398 	struct {
399 		u32 mmio_base;
400 
401 		/* protects panel power sequencer state */
402 		struct mutex mutex;
403 	} pps;
404 
405 	struct {
406 		struct drm_property *broadcast_rgb;
407 		struct drm_property *force_audio;
408 	} properties;
409 
410 	struct {
411 		unsigned long mask;
412 	} quirks;
413 
414 	struct {
415 		/* restore state for suspend/resume and display reset */
416 		struct drm_atomic_state *modeset_state;
417 		struct drm_modeset_acquire_ctx reset_ctx;
418 	} restore;
419 
420 	struct {
421 		enum {
422 			I915_SAGV_UNKNOWN = 0,
423 			I915_SAGV_DISABLED,
424 			I915_SAGV_ENABLED,
425 			I915_SAGV_NOT_CONTROLLED
426 		} status;
427 
428 		u32 block_time_us;
429 	} sagv;
430 
431 	struct {
432 		/* ordered wq for modesets */
433 		struct workqueue_struct *modeset;
434 
435 		/* unbound hipri wq for page flips/plane updates */
436 		struct workqueue_struct *flip;
437 	} wq;
438 
439 	/* Grouping using named structs. Keep sorted. */
440 	struct intel_audio audio;
441 	struct intel_dmc dmc;
442 	struct intel_dpll dpll;
443 	struct intel_fbc *fbc[I915_MAX_FBCS];
444 	struct intel_frontbuffer_tracking fb_tracking;
445 	struct intel_hotplug hotplug;
446 	struct intel_opregion opregion;
447 	struct intel_overlay *overlay;
448 	struct intel_vbt_data vbt;
449 	struct intel_wm wm;
450 };
451 
452 #endif /* __INTEL_DISPLAY_CORE_H__ */
453