1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_CORE_H__ 7 #define __INTEL_DISPLAY_CORE_H__ 8 9 #include <linux/list.h> 10 #include <linux/llist.h> 11 #include <linux/mutex.h> 12 #include <linux/types.h> 13 #include <linux/wait.h> 14 #include <linux/workqueue.h> 15 16 #include <drm/drm_connector.h> 17 #include <drm/drm_modeset_lock.h> 18 19 #include "intel_cdclk.h" 20 #include "intel_display_limits.h" 21 #include "intel_display_power.h" 22 #include "intel_dpll_mgr.h" 23 #include "intel_fbc.h" 24 #include "intel_global_state.h" 25 #include "intel_gmbus.h" 26 #include "intel_opregion.h" 27 #include "intel_wm_types.h" 28 29 struct drm_i915_private; 30 struct drm_property; 31 struct drm_property_blob; 32 struct i915_audio_component; 33 struct i915_hdcp_comp_master; 34 struct intel_atomic_state; 35 struct intel_audio_funcs; 36 struct intel_bios_encoder_data; 37 struct intel_cdclk_funcs; 38 struct intel_cdclk_vals; 39 struct intel_color_funcs; 40 struct intel_crtc; 41 struct intel_crtc_state; 42 struct intel_dmc; 43 struct intel_dpll_funcs; 44 struct intel_dpll_mgr; 45 struct intel_fbdev; 46 struct intel_fdi_funcs; 47 struct intel_hotplug_funcs; 48 struct intel_initial_plane_config; 49 struct intel_overlay; 50 51 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 52 #define I915_NUM_QGV_POINTS 8 53 54 /* Amount of PSF GV points, BSpec precisely defines this */ 55 #define I915_NUM_PSF_GV_POINTS 3 56 57 struct intel_display_funcs { 58 /* 59 * Returns the active state of the crtc, and if the crtc is active, 60 * fills out the pipe-config with the hw state. 61 */ 62 bool (*get_pipe_config)(struct intel_crtc *, 63 struct intel_crtc_state *); 64 void (*get_initial_plane_config)(struct intel_crtc *, 65 struct intel_initial_plane_config *); 66 void (*crtc_enable)(struct intel_atomic_state *state, 67 struct intel_crtc *crtc); 68 void (*crtc_disable)(struct intel_atomic_state *state, 69 struct intel_crtc *crtc); 70 void (*commit_modeset_enables)(struct intel_atomic_state *state); 71 }; 72 73 /* functions used for watermark calcs for display. */ 74 struct intel_wm_funcs { 75 /* update_wm is for legacy wm management */ 76 void (*update_wm)(struct drm_i915_private *dev_priv); 77 int (*compute_pipe_wm)(struct intel_atomic_state *state, 78 struct intel_crtc *crtc); 79 int (*compute_intermediate_wm)(struct intel_atomic_state *state, 80 struct intel_crtc *crtc); 81 void (*initial_watermarks)(struct intel_atomic_state *state, 82 struct intel_crtc *crtc); 83 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 84 struct intel_crtc *crtc); 85 void (*optimize_watermarks)(struct intel_atomic_state *state, 86 struct intel_crtc *crtc); 87 int (*compute_global_watermarks)(struct intel_atomic_state *state); 88 void (*get_hw_state)(struct drm_i915_private *i915); 89 }; 90 91 struct intel_audio_state { 92 struct intel_encoder *encoder; 93 u8 eld[MAX_ELD_BYTES]; 94 }; 95 96 struct intel_audio { 97 /* hda/i915 audio component */ 98 struct i915_audio_component *component; 99 bool component_registered; 100 /* mutex for audio/video sync */ 101 struct mutex mutex; 102 int power_refcount; 103 u32 freq_cntrl; 104 105 /* current audio state for the audio component hooks */ 106 struct intel_audio_state state[I915_MAX_TRANSCODERS]; 107 108 /* necessary resource sharing with HDMI LPE audio driver. */ 109 struct { 110 struct platform_device *platdev; 111 int irq; 112 } lpe; 113 }; 114 115 /* 116 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes 117 * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per 118 * dpll, because on some platforms plls share registers. 119 */ 120 struct intel_dpll { 121 struct mutex lock; 122 123 int num_shared_dpll; 124 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 125 const struct intel_dpll_mgr *mgr; 126 127 struct { 128 int nssc; 129 int ssc; 130 } ref_clks; 131 132 /* 133 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id. 134 */ 135 u8 pch_ssc_use; 136 }; 137 138 struct intel_frontbuffer_tracking { 139 spinlock_t lock; 140 141 /* 142 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 143 * scheduled flips. 144 */ 145 unsigned busy_bits; 146 unsigned flip_bits; 147 }; 148 149 struct intel_hotplug { 150 struct delayed_work hotplug_work; 151 152 const u32 *hpd, *pch_hpd; 153 154 struct { 155 unsigned long last_jiffies; 156 int count; 157 enum { 158 HPD_ENABLED = 0, 159 HPD_DISABLED = 1, 160 HPD_MARK_DISABLED = 2 161 } state; 162 } stats[HPD_NUM_PINS]; 163 u32 event_bits; 164 u32 retry_bits; 165 struct delayed_work reenable_work; 166 167 u32 long_port_mask; 168 u32 short_port_mask; 169 struct work_struct dig_port_work; 170 171 struct work_struct poll_init_work; 172 bool poll_enabled; 173 174 unsigned int hpd_storm_threshold; 175 /* Whether or not to count short HPD IRQs in HPD storms */ 176 u8 hpd_short_storm_enabled; 177 178 /* 179 * if we get a HPD irq from DP and a HPD irq from non-DP 180 * the non-DP HPD could block the workqueue on a mode config 181 * mutex getting, that userspace may have taken. However 182 * userspace is waiting on the DP workqueue to run which is 183 * blocked behind the non-DP one. 184 */ 185 struct workqueue_struct *dp_wq; 186 187 /* 188 * Flag to track if long HPDs need not to be processed 189 * 190 * Some panels generate long HPDs while keep connected to the port. 191 * This can cause issues with CI tests results. In CI systems we 192 * don't expect to disconnect the panels and could ignore the long 193 * HPDs generated from the faulty panels. This flag can be used as 194 * cue to ignore the long HPDs and can be set / unset using debugfs. 195 */ 196 bool ignore_long_hpd; 197 }; 198 199 struct intel_vbt_data { 200 /* bdb version */ 201 u16 version; 202 203 /* Feature bits */ 204 unsigned int int_tv_support:1; 205 unsigned int int_crt_support:1; 206 unsigned int lvds_use_ssc:1; 207 unsigned int int_lvds_support:1; 208 unsigned int display_clock_mode:1; 209 unsigned int fdi_rx_polarity_inverted:1; 210 int lvds_ssc_freq; 211 enum drm_panel_orientation orientation; 212 213 bool override_afc_startup; 214 u8 override_afc_startup_val; 215 216 int crt_ddc_pin; 217 218 struct list_head display_devices; 219 struct list_head bdb_blocks; 220 221 struct intel_bios_encoder_data *ports[I915_MAX_PORTS]; /* Non-NULL if port present. */ 222 struct sdvo_device_mapping { 223 u8 initialized; 224 u8 dvo_port; 225 u8 slave_addr; 226 u8 dvo_wiring; 227 u8 i2c_pin; 228 u8 ddc_pin; 229 } sdvo_mappings[2]; 230 }; 231 232 struct intel_wm { 233 /* 234 * Raw watermark latency values: 235 * in 0.1us units for WM0, 236 * in 0.5us units for WM1+. 237 */ 238 /* primary */ 239 u16 pri_latency[5]; 240 /* sprite */ 241 u16 spr_latency[5]; 242 /* cursor */ 243 u16 cur_latency[5]; 244 /* 245 * Raw watermark memory latency values 246 * for SKL for all 8 levels 247 * in 1us units. 248 */ 249 u16 skl_latency[8]; 250 251 /* current hardware state */ 252 union { 253 struct ilk_wm_values hw; 254 struct vlv_wm_values vlv; 255 struct g4x_wm_values g4x; 256 }; 257 258 u8 num_levels; 259 260 /* 261 * Should be held around atomic WM register writing; also 262 * protects * intel_crtc->wm.active and 263 * crtc_state->wm.need_postvbl_update. 264 */ 265 struct mutex wm_mutex; 266 267 bool ipc_enabled; 268 }; 269 270 struct intel_display { 271 /* Display functions */ 272 struct { 273 /* Top level crtc-ish functions */ 274 const struct intel_display_funcs *display; 275 276 /* Display CDCLK functions */ 277 const struct intel_cdclk_funcs *cdclk; 278 279 /* Display pll funcs */ 280 const struct intel_dpll_funcs *dpll; 281 282 /* irq display functions */ 283 const struct intel_hotplug_funcs *hotplug; 284 285 /* pm display functions */ 286 const struct intel_wm_funcs *wm; 287 288 /* fdi display functions */ 289 const struct intel_fdi_funcs *fdi; 290 291 /* Display internal color functions */ 292 const struct intel_color_funcs *color; 293 294 /* Display internal audio functions */ 295 const struct intel_audio_funcs *audio; 296 } funcs; 297 298 /* Grouping using anonymous structs. Keep sorted. */ 299 struct intel_atomic_helper { 300 struct llist_head free_list; 301 struct work_struct free_work; 302 } atomic_helper; 303 304 struct { 305 /* backlight registers and fields in struct intel_panel */ 306 struct mutex lock; 307 } backlight; 308 309 struct { 310 struct intel_global_obj obj; 311 312 struct intel_bw_info { 313 /* for each QGV point */ 314 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 315 /* for each PSF GV point */ 316 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS]; 317 u8 num_qgv_points; 318 u8 num_psf_gv_points; 319 u8 num_planes; 320 } max[6]; 321 } bw; 322 323 struct { 324 /* The current hardware cdclk configuration */ 325 struct intel_cdclk_config hw; 326 327 /* cdclk, divider, and ratio table from bspec */ 328 const struct intel_cdclk_vals *table; 329 330 struct intel_global_obj obj; 331 332 unsigned int max_cdclk_freq; 333 } cdclk; 334 335 struct { 336 struct drm_property_blob *glk_linear_degamma_lut; 337 } color; 338 339 struct { 340 /* The current hardware dbuf configuration */ 341 u8 enabled_slices; 342 343 struct intel_global_obj obj; 344 } dbuf; 345 346 struct { 347 /* 348 * dkl.phy_lock protects against concurrent access of the 349 * Dekel TypeC PHYs. 350 */ 351 spinlock_t phy_lock; 352 } dkl; 353 354 struct { 355 struct intel_dmc *dmc; 356 intel_wakeref_t wakeref; 357 } dmc; 358 359 struct { 360 /* VLV/CHV/BXT/GLK DSI MMIO register base address */ 361 u32 mmio_base; 362 } dsi; 363 364 struct { 365 /* list of fbdev register on this device */ 366 struct intel_fbdev *fbdev; 367 struct work_struct suspend_work; 368 } fbdev; 369 370 struct { 371 unsigned int pll_freq; 372 u32 rx_config; 373 } fdi; 374 375 struct { 376 struct list_head obj_list; 377 } global; 378 379 struct { 380 /* 381 * Base address of where the gmbus and gpio blocks are located 382 * (either on PCH or on SoC for platforms without PCH). 383 */ 384 u32 mmio_base; 385 386 /* 387 * gmbus.mutex protects against concurrent usage of the single 388 * hw gmbus controller on different i2c buses. 389 */ 390 struct mutex mutex; 391 392 struct intel_gmbus *bus[GMBUS_NUM_PINS]; 393 394 wait_queue_head_t wait_queue; 395 } gmbus; 396 397 struct { 398 struct i915_hdcp_master *master; 399 bool comp_added; 400 401 /* 402 * HDCP message struct for allocation of memory which can be 403 * reused when sending message to gsc cs. 404 * this is only populated post Meteorlake 405 */ 406 struct intel_hdcp_gsc_message *hdcp_message; 407 /* Mutex to protect the above hdcp component related values. */ 408 struct mutex comp_mutex; 409 } hdcp; 410 411 struct { 412 /* 413 * HTI (aka HDPORT) state read during initial hw readout. Most 414 * platforms don't have HTI, so this will just stay 0. Those 415 * that do will use this later to figure out which PLLs and PHYs 416 * are unavailable for driver usage. 417 */ 418 u32 state; 419 } hti; 420 421 struct { 422 bool false_color; 423 } ips; 424 425 struct { 426 struct i915_power_domains domains; 427 428 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 429 u32 chv_phy_control; 430 431 /* perform PHY state sanity checks? */ 432 bool chv_phy_assert[2]; 433 } power; 434 435 struct { 436 u32 mmio_base; 437 438 /* protects panel power sequencer state */ 439 struct mutex mutex; 440 } pps; 441 442 struct { 443 struct drm_property *broadcast_rgb; 444 struct drm_property *force_audio; 445 } properties; 446 447 struct { 448 unsigned long mask; 449 } quirks; 450 451 struct { 452 /* restore state for suspend/resume and display reset */ 453 struct drm_atomic_state *modeset_state; 454 struct drm_modeset_acquire_ctx reset_ctx; 455 } restore; 456 457 struct { 458 enum { 459 I915_SAGV_UNKNOWN = 0, 460 I915_SAGV_DISABLED, 461 I915_SAGV_ENABLED, 462 I915_SAGV_NOT_CONTROLLED 463 } status; 464 465 u32 block_time_us; 466 } sagv; 467 468 struct { 469 /* 470 * DG2: Mask of PHYs that were not calibrated by the firmware 471 * and should not be used. 472 */ 473 u8 phy_failed_calibration; 474 } snps; 475 476 struct { 477 /* 478 * Shadows for CHV DPLL_MD regs to keep the state 479 * checker somewhat working in the presence hardware 480 * crappiness (can't read out DPLL_MD for pipes B & C). 481 */ 482 u32 chv_dpll_md[I915_MAX_PIPES]; 483 u32 bxt_phy_grc; 484 } state; 485 486 struct { 487 /* ordered wq for modesets */ 488 struct workqueue_struct *modeset; 489 490 /* unbound hipri wq for page flips/plane updates */ 491 struct workqueue_struct *flip; 492 } wq; 493 494 /* Grouping using named structs. Keep sorted. */ 495 struct intel_audio audio; 496 struct intel_dpll dpll; 497 struct intel_fbc *fbc[I915_MAX_FBCS]; 498 struct intel_frontbuffer_tracking fb_tracking; 499 struct intel_hotplug hotplug; 500 struct intel_opregion opregion; 501 struct intel_overlay *overlay; 502 struct intel_vbt_data vbt; 503 struct intel_wm wm; 504 }; 505 506 #endif /* __INTEL_DISPLAY_CORE_H__ */ 507