1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 30 enum link_m_n_set; 31 enum drm_scaling_filter; 32 struct dpll; 33 struct drm_connector; 34 struct drm_device; 35 struct drm_display_mode; 36 struct drm_encoder; 37 struct drm_file; 38 struct drm_format_info; 39 struct drm_framebuffer; 40 struct drm_i915_gem_object; 41 struct drm_i915_private; 42 struct drm_mode_fb_cmd2; 43 struct drm_modeset_acquire_ctx; 44 struct drm_plane; 45 struct drm_plane_state; 46 struct i915_address_space; 47 struct i915_ggtt_view; 48 struct intel_atomic_state; 49 struct intel_crtc; 50 struct intel_crtc_state; 51 struct intel_digital_port; 52 struct intel_dp; 53 struct intel_encoder; 54 struct intel_initial_plane_config; 55 struct intel_load_detect_pipe; 56 struct intel_plane; 57 struct intel_plane_state; 58 struct intel_remapped_info; 59 struct intel_rotation_info; 60 61 enum i915_gpio { 62 GPIOA, 63 GPIOB, 64 GPIOC, 65 GPIOD, 66 GPIOE, 67 GPIOF, 68 GPIOG, 69 GPIOH, 70 __GPIOI_UNUSED, 71 GPIOJ, 72 GPIOK, 73 GPIOL, 74 GPIOM, 75 GPION, 76 GPIOO, 77 }; 78 79 /* 80 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 81 * rest have consecutive values and match the enum values of transcoders 82 * with a 1:1 transcoder -> pipe mapping. 83 */ 84 enum pipe { 85 INVALID_PIPE = -1, 86 87 PIPE_A = 0, 88 PIPE_B, 89 PIPE_C, 90 PIPE_D, 91 _PIPE_EDP, 92 93 I915_MAX_PIPES = _PIPE_EDP 94 }; 95 96 #define pipe_name(p) ((p) + 'A') 97 98 enum transcoder { 99 INVALID_TRANSCODER = -1, 100 /* 101 * The following transcoders have a 1:1 transcoder -> pipe mapping, 102 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 103 * rest have consecutive values and match the enum values of the pipes 104 * they map to. 105 */ 106 TRANSCODER_A = PIPE_A, 107 TRANSCODER_B = PIPE_B, 108 TRANSCODER_C = PIPE_C, 109 TRANSCODER_D = PIPE_D, 110 111 /* 112 * The following transcoders can map to any pipe, their enum value 113 * doesn't need to stay fixed. 114 */ 115 TRANSCODER_EDP, 116 TRANSCODER_DSI_0, 117 TRANSCODER_DSI_1, 118 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 119 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 120 121 I915_MAX_TRANSCODERS 122 }; 123 124 static inline const char *transcoder_name(enum transcoder transcoder) 125 { 126 switch (transcoder) { 127 case TRANSCODER_A: 128 return "A"; 129 case TRANSCODER_B: 130 return "B"; 131 case TRANSCODER_C: 132 return "C"; 133 case TRANSCODER_D: 134 return "D"; 135 case TRANSCODER_EDP: 136 return "EDP"; 137 case TRANSCODER_DSI_A: 138 return "DSI A"; 139 case TRANSCODER_DSI_C: 140 return "DSI C"; 141 default: 142 return "<invalid>"; 143 } 144 } 145 146 static inline bool transcoder_is_dsi(enum transcoder transcoder) 147 { 148 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 149 } 150 151 /* 152 * Global legacy plane identifier. Valid only for primary/sprite 153 * planes on pre-g4x, and only for primary planes on g4x-bdw. 154 */ 155 enum i9xx_plane_id { 156 PLANE_A, 157 PLANE_B, 158 PLANE_C, 159 }; 160 161 #define plane_name(p) ((p) + 'A') 162 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 163 164 /* 165 * Per-pipe plane identifier. 166 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 167 * number of planes per CRTC. Not all platforms really have this many planes, 168 * which means some arrays of size I915_MAX_PLANES may have unused entries 169 * between the topmost sprite plane and the cursor plane. 170 * 171 * This is expected to be passed to various register macros 172 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 173 */ 174 enum plane_id { 175 PLANE_PRIMARY, 176 PLANE_SPRITE0, 177 PLANE_SPRITE1, 178 PLANE_SPRITE2, 179 PLANE_SPRITE3, 180 PLANE_SPRITE4, 181 PLANE_SPRITE5, 182 PLANE_CURSOR, 183 184 I915_MAX_PLANES, 185 }; 186 187 #define for_each_plane_id_on_crtc(__crtc, __p) \ 188 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 189 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 190 191 #define for_each_dbuf_slice(__dev_priv, __slice) \ 192 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \ 193 for_each_if(INTEL_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice)) 194 195 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \ 196 for_each_dbuf_slice((__dev_priv), (__slice)) \ 197 for_each_if((__mask) & BIT(__slice)) 198 199 enum port { 200 PORT_NONE = -1, 201 202 PORT_A = 0, 203 PORT_B, 204 PORT_C, 205 PORT_D, 206 PORT_E, 207 PORT_F, 208 PORT_G, 209 PORT_H, 210 PORT_I, 211 212 /* tgl+ */ 213 PORT_TC1 = PORT_D, 214 PORT_TC2, 215 PORT_TC3, 216 PORT_TC4, 217 PORT_TC5, 218 PORT_TC6, 219 220 /* XE_LPD repositions D/E offsets and bitfields */ 221 PORT_D_XELPD = PORT_TC5, 222 PORT_E_XELPD, 223 224 I915_MAX_PORTS 225 }; 226 227 #define port_name(p) ((p) + 'A') 228 229 /* 230 * Ports identifier referenced from other drivers. 231 * Expected to remain stable over time 232 */ 233 static inline const char *port_identifier(enum port port) 234 { 235 switch (port) { 236 case PORT_A: 237 return "Port A"; 238 case PORT_B: 239 return "Port B"; 240 case PORT_C: 241 return "Port C"; 242 case PORT_D: 243 return "Port D"; 244 case PORT_E: 245 return "Port E"; 246 case PORT_F: 247 return "Port F"; 248 case PORT_G: 249 return "Port G"; 250 case PORT_H: 251 return "Port H"; 252 case PORT_I: 253 return "Port I"; 254 default: 255 return "<invalid>"; 256 } 257 } 258 259 enum tc_port { 260 TC_PORT_NONE = -1, 261 262 TC_PORT_1 = 0, 263 TC_PORT_2, 264 TC_PORT_3, 265 TC_PORT_4, 266 TC_PORT_5, 267 TC_PORT_6, 268 269 I915_MAX_TC_PORTS 270 }; 271 272 enum tc_port_mode { 273 TC_PORT_DISCONNECTED, 274 TC_PORT_TBT_ALT, 275 TC_PORT_DP_ALT, 276 TC_PORT_LEGACY, 277 }; 278 279 enum dpio_channel { 280 DPIO_CH0, 281 DPIO_CH1 282 }; 283 284 enum dpio_phy { 285 DPIO_PHY0, 286 DPIO_PHY1, 287 DPIO_PHY2, 288 }; 289 290 enum aux_ch { 291 AUX_CH_A, 292 AUX_CH_B, 293 AUX_CH_C, 294 AUX_CH_D, 295 AUX_CH_E, /* ICL+ */ 296 AUX_CH_F, 297 AUX_CH_G, 298 AUX_CH_H, 299 AUX_CH_I, 300 301 /* tgl+ */ 302 AUX_CH_USBC1 = AUX_CH_D, 303 AUX_CH_USBC2, 304 AUX_CH_USBC3, 305 AUX_CH_USBC4, 306 AUX_CH_USBC5, 307 AUX_CH_USBC6, 308 309 /* XE_LPD repositions D/E offsets and bitfields */ 310 AUX_CH_D_XELPD = AUX_CH_USBC5, 311 AUX_CH_E_XELPD, 312 }; 313 314 #define aux_ch_name(a) ((a) + 'A') 315 316 /* Used by dp and fdi links */ 317 struct intel_link_m_n { 318 u32 tu; 319 u32 gmch_m; 320 u32 gmch_n; 321 u32 link_m; 322 u32 link_n; 323 }; 324 325 enum phy { 326 PHY_NONE = -1, 327 328 PHY_A = 0, 329 PHY_B, 330 PHY_C, 331 PHY_D, 332 PHY_E, 333 PHY_F, 334 PHY_G, 335 PHY_H, 336 PHY_I, 337 338 I915_MAX_PHYS 339 }; 340 341 #define phy_name(a) ((a) + 'A') 342 343 enum phy_fia { 344 FIA1, 345 FIA2, 346 FIA3, 347 }; 348 349 #define for_each_pipe(__dev_priv, __p) \ 350 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ 351 for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p)) 352 353 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 354 for_each_pipe(__dev_priv, __p) \ 355 for_each_if((__mask) & BIT(__p)) 356 357 #define for_each_cpu_transcoder(__dev_priv, __t) \ 358 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 359 for_each_if (INTEL_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t)) 360 361 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 362 for_each_cpu_transcoder(__dev_priv, __t) \ 363 for_each_if ((__mask) & BIT(__t)) 364 365 #define for_each_sprite(__dev_priv, __p, __s) \ 366 for ((__s) = 0; \ 367 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 368 (__s)++) 369 370 #define for_each_port(__port) \ 371 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 372 373 #define for_each_port_masked(__port, __ports_mask) \ 374 for_each_port(__port) \ 375 for_each_if((__ports_mask) & BIT(__port)) 376 377 #define for_each_phy_masked(__phy, __phys_mask) \ 378 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 379 for_each_if((__phys_mask) & BIT(__phy)) 380 381 #define for_each_crtc(dev, crtc) \ 382 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 383 384 #define for_each_intel_plane(dev, intel_plane) \ 385 list_for_each_entry(intel_plane, \ 386 &(dev)->mode_config.plane_list, \ 387 base.head) 388 389 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 390 list_for_each_entry(intel_plane, \ 391 &(dev)->mode_config.plane_list, \ 392 base.head) \ 393 for_each_if((plane_mask) & \ 394 drm_plane_mask(&intel_plane->base)) 395 396 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 397 list_for_each_entry(intel_plane, \ 398 &(dev)->mode_config.plane_list, \ 399 base.head) \ 400 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 401 402 #define for_each_intel_crtc(dev, intel_crtc) \ 403 list_for_each_entry(intel_crtc, \ 404 &(dev)->mode_config.crtc_list, \ 405 base.head) 406 407 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ 408 list_for_each_entry(intel_crtc, \ 409 &(dev)->mode_config.crtc_list, \ 410 base.head) \ 411 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base)) 412 413 #define for_each_intel_encoder(dev, intel_encoder) \ 414 list_for_each_entry(intel_encoder, \ 415 &(dev)->mode_config.encoder_list, \ 416 base.head) 417 418 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 419 list_for_each_entry(intel_encoder, \ 420 &(dev)->mode_config.encoder_list, \ 421 base.head) \ 422 for_each_if((encoder_mask) & \ 423 drm_encoder_mask(&intel_encoder->base)) 424 425 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \ 426 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 427 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \ 428 intel_encoder_can_psr(intel_encoder)) 429 430 #define for_each_intel_dp(dev, intel_encoder) \ 431 for_each_intel_encoder(dev, intel_encoder) \ 432 for_each_if(intel_encoder_is_dp(intel_encoder)) 433 434 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \ 435 for_each_intel_encoder((dev), (intel_encoder)) \ 436 for_each_if(intel_encoder_can_psr(intel_encoder)) 437 438 #define for_each_intel_connector_iter(intel_connector, iter) \ 439 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 440 441 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 442 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 443 for_each_if((intel_encoder)->base.crtc == (__crtc)) 444 445 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 446 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 447 for_each_if((intel_connector)->base.encoder == (__encoder)) 448 449 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 450 for ((__i) = 0; \ 451 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 452 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 453 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 454 (__i)++) \ 455 for_each_if(plane) 456 457 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 458 for ((__i) = 0; \ 459 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 460 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 461 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 462 (__i)++) \ 463 for_each_if(plane) 464 465 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 466 for ((__i) = 0; \ 467 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 468 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 469 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 470 (__i)++) \ 471 for_each_if(crtc) 472 473 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 474 for ((__i) = 0; \ 475 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 476 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 477 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 478 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 479 (__i)++) \ 480 for_each_if(plane) 481 482 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 483 for ((__i) = 0; \ 484 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 485 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 486 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 487 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 488 (__i)++) \ 489 for_each_if(crtc) 490 491 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 492 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 493 (__i) >= 0 && \ 494 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 495 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 496 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 497 (__i)--) \ 498 for_each_if(crtc) 499 500 #define intel_atomic_crtc_state_for_each_plane_state( \ 501 plane, plane_state, \ 502 crtc_state) \ 503 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 504 ((crtc_state)->uapi.plane_mask)) \ 505 for_each_if ((plane_state = \ 506 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) 507 508 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 509 for ((__i) = 0; \ 510 (__i) < (__state)->base.num_connector; \ 511 (__i)++) \ 512 for_each_if ((__state)->base.connectors[__i].ptr && \ 513 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 514 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 515 516 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 517 struct intel_crtc *crtc); 518 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 519 u8 active_pipes); 520 void intel_link_compute_m_n(u16 bpp, int nlanes, 521 int pixel_clock, int link_clock, 522 struct intel_link_m_n *m_n, 523 bool constant_n, bool fec_enable); 524 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); 525 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 526 u32 pixel_format, u64 modifier); 527 enum drm_mode_status 528 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 529 const struct drm_display_mode *mode, 530 bool bigjoiner); 531 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 532 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 533 534 void intel_plane_destroy(struct drm_plane *plane); 535 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); 536 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state); 537 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 538 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 539 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); 540 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 541 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 542 const char *name, u32 reg, int ref_freq); 543 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 544 const char *name, u32 reg); 545 void lpt_pch_enable(const struct intel_crtc_state *crtc_state); 546 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); 547 void lpt_disable_iclkip(struct drm_i915_private *dev_priv); 548 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 549 unsigned int intel_fb_xy_to_linear(int x, int y, 550 const struct intel_plane_state *state, 551 int plane); 552 void intel_add_fb_offsets(int *x, int *y, 553 const struct intel_plane_state *state, int plane); 554 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 555 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); 556 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 557 int intel_display_suspend(struct drm_device *dev); 558 void intel_encoder_destroy(struct drm_encoder *encoder); 559 struct drm_display_mode * 560 intel_encoder_current_mode(struct intel_encoder *encoder); 561 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); 562 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); 563 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy); 564 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, 565 enum port port); 566 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 567 struct drm_file *file_priv); 568 569 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 570 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 571 struct intel_digital_port *dig_port, 572 unsigned int expected_mask); 573 int intel_get_load_detect_pipe(struct drm_connector *connector, 574 struct intel_load_detect_pipe *old, 575 struct drm_modeset_acquire_ctx *ctx); 576 void intel_release_load_detect_pipe(struct drm_connector *connector, 577 struct intel_load_detect_pipe *old, 578 struct drm_modeset_acquire_ctx *ctx); 579 struct drm_framebuffer * 580 intel_framebuffer_create(struct drm_i915_gem_object *obj, 581 struct drm_mode_fb_cmd2 *mode_cmd); 582 583 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 584 enum pipe pipe); 585 586 int lpt_get_iclkip(struct drm_i915_private *dev_priv); 587 bool intel_fuzzy_clock_check(int clock1, int clock2); 588 589 void intel_display_prepare_reset(struct drm_i915_private *dev_priv); 590 void intel_display_finish_reset(struct drm_i915_private *dev_priv); 591 void intel_dp_get_m_n(struct intel_crtc *crtc, 592 struct intel_crtc_state *pipe_config); 593 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, 594 enum link_m_n_set m_n); 595 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 596 597 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); 598 void hsw_enable_ips(const struct intel_crtc_state *crtc_state); 599 void hsw_disable_ips(const struct intel_crtc_state *crtc_state); 600 enum intel_display_power_domain intel_port_to_power_domain(enum port port); 601 enum intel_display_power_domain 602 intel_aux_power_domain(struct intel_digital_port *dig_port); 603 enum intel_display_power_domain 604 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch); 605 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 606 struct intel_crtc_state *crtc_state); 607 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); 608 609 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); 610 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state); 611 612 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state); 613 bool 614 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, 615 u64 modifier); 616 617 struct intel_encoder * 618 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 619 const struct intel_crtc_state *crtc_state); 620 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 621 struct intel_plane *plane); 622 623 void intel_display_driver_register(struct drm_i915_private *i915); 624 void intel_display_driver_unregister(struct drm_i915_private *i915); 625 626 /* modesetting */ 627 void intel_modeset_init_hw(struct drm_i915_private *i915); 628 int intel_modeset_init_noirq(struct drm_i915_private *i915); 629 int intel_modeset_init_nogem(struct drm_i915_private *i915); 630 int intel_modeset_init(struct drm_i915_private *i915); 631 void intel_modeset_driver_remove(struct drm_i915_private *i915); 632 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915); 633 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915); 634 void intel_display_resume(struct drm_device *dev); 635 void intel_init_pch_refclk(struct drm_i915_private *dev_priv); 636 int intel_modeset_all_pipes(struct intel_atomic_state *state); 637 638 /* modesetting asserts */ 639 void assert_transcoder(struct drm_i915_private *dev_priv, 640 enum transcoder cpu_transcoder, bool state); 641 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true) 642 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false) 643 644 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 645 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 646 * which may not necessarily be a user visible problem. This will either 647 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 648 * enable distros and users to tailor their preferred amount of i915 abrt 649 * spam. 650 */ 651 #define I915_STATE_WARN(condition, format...) ({ \ 652 int __ret_warn_on = !!(condition); \ 653 if (unlikely(__ret_warn_on)) \ 654 if (!WARN(i915_modparams.verbose_state_checks, format)) \ 655 DRM_ERROR(format); \ 656 unlikely(__ret_warn_on); \ 657 }) 658 659 #define I915_STATE_WARN_ON(x) \ 660 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 661 662 #endif 663