1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 #include <drm/i915_drm.h> 30 31 struct drm_i915_private; 32 struct intel_plane_state; 33 34 enum i915_gpio { 35 GPIOA, 36 GPIOB, 37 GPIOC, 38 GPIOD, 39 GPIOE, 40 GPIOF, 41 GPIOG, 42 GPIOH, 43 __GPIOI_UNUSED, 44 GPIOJ, 45 GPIOK, 46 GPIOL, 47 GPIOM, 48 }; 49 50 /* 51 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 52 * rest have consecutive values and match the enum values of transcoders 53 * with a 1:1 transcoder -> pipe mapping. 54 */ 55 enum pipe { 56 INVALID_PIPE = -1, 57 58 PIPE_A = 0, 59 PIPE_B, 60 PIPE_C, 61 _PIPE_EDP, 62 63 I915_MAX_PIPES = _PIPE_EDP 64 }; 65 66 #define pipe_name(p) ((p) + 'A') 67 68 enum transcoder { 69 /* 70 * The following transcoders have a 1:1 transcoder -> pipe mapping, 71 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 72 * rest have consecutive values and match the enum values of the pipes 73 * they map to. 74 */ 75 TRANSCODER_A = PIPE_A, 76 TRANSCODER_B = PIPE_B, 77 TRANSCODER_C = PIPE_C, 78 79 /* 80 * The following transcoders can map to any pipe, their enum value 81 * doesn't need to stay fixed. 82 */ 83 TRANSCODER_EDP, 84 TRANSCODER_DSI_0, 85 TRANSCODER_DSI_1, 86 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 87 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 88 89 I915_MAX_TRANSCODERS 90 }; 91 92 static inline const char *transcoder_name(enum transcoder transcoder) 93 { 94 switch (transcoder) { 95 case TRANSCODER_A: 96 return "A"; 97 case TRANSCODER_B: 98 return "B"; 99 case TRANSCODER_C: 100 return "C"; 101 case TRANSCODER_EDP: 102 return "EDP"; 103 case TRANSCODER_DSI_A: 104 return "DSI A"; 105 case TRANSCODER_DSI_C: 106 return "DSI C"; 107 default: 108 return "<invalid>"; 109 } 110 } 111 112 static inline bool transcoder_is_dsi(enum transcoder transcoder) 113 { 114 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 115 } 116 117 /* 118 * Global legacy plane identifier. Valid only for primary/sprite 119 * planes on pre-g4x, and only for primary planes on g4x-bdw. 120 */ 121 enum i9xx_plane_id { 122 PLANE_A, 123 PLANE_B, 124 PLANE_C, 125 }; 126 127 #define plane_name(p) ((p) + 'A') 128 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 129 130 /* 131 * Per-pipe plane identifier. 132 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 133 * number of planes per CRTC. Not all platforms really have this many planes, 134 * which means some arrays of size I915_MAX_PLANES may have unused entries 135 * between the topmost sprite plane and the cursor plane. 136 * 137 * This is expected to be passed to various register macros 138 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 139 */ 140 enum plane_id { 141 PLANE_PRIMARY, 142 PLANE_SPRITE0, 143 PLANE_SPRITE1, 144 PLANE_SPRITE2, 145 PLANE_SPRITE3, 146 PLANE_SPRITE4, 147 PLANE_SPRITE5, 148 PLANE_CURSOR, 149 150 I915_MAX_PLANES, 151 }; 152 153 #define for_each_plane_id_on_crtc(__crtc, __p) \ 154 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 155 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 156 157 /* 158 * Ports identifier referenced from other drivers. 159 * Expected to remain stable over time 160 */ 161 static inline const char *port_identifier(enum port port) 162 { 163 switch (port) { 164 case PORT_A: 165 return "Port A"; 166 case PORT_B: 167 return "Port B"; 168 case PORT_C: 169 return "Port C"; 170 case PORT_D: 171 return "Port D"; 172 case PORT_E: 173 return "Port E"; 174 case PORT_F: 175 return "Port F"; 176 default: 177 return "<invalid>"; 178 } 179 } 180 181 enum tc_port { 182 PORT_TC_NONE = -1, 183 184 PORT_TC1 = 0, 185 PORT_TC2, 186 PORT_TC3, 187 PORT_TC4, 188 189 I915_MAX_TC_PORTS 190 }; 191 192 enum tc_port_type { 193 TC_PORT_UNKNOWN = 0, 194 TC_PORT_TYPEC, 195 TC_PORT_TBT, 196 TC_PORT_LEGACY, 197 }; 198 199 enum dpio_channel { 200 DPIO_CH0, 201 DPIO_CH1 202 }; 203 204 enum dpio_phy { 205 DPIO_PHY0, 206 DPIO_PHY1, 207 DPIO_PHY2, 208 }; 209 210 #define I915_NUM_PHYS_VLV 2 211 212 enum aux_ch { 213 AUX_CH_A, 214 AUX_CH_B, 215 AUX_CH_C, 216 AUX_CH_D, 217 AUX_CH_E, /* ICL+ */ 218 AUX_CH_F, 219 }; 220 221 #define aux_ch_name(a) ((a) + 'A') 222 223 /* Used by dp and fdi links */ 224 struct intel_link_m_n { 225 u32 tu; 226 u32 gmch_m; 227 u32 gmch_n; 228 u32 link_m; 229 u32 link_n; 230 }; 231 232 #define for_each_pipe(__dev_priv, __p) \ 233 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) 234 235 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 236 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ 237 for_each_if((__mask) & BIT(__p)) 238 239 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 240 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 241 for_each_if ((__mask) & (1 << (__t))) 242 243 #define for_each_universal_plane(__dev_priv, __pipe, __p) \ 244 for ((__p) = 0; \ 245 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ 246 (__p)++) 247 248 #define for_each_sprite(__dev_priv, __p, __s) \ 249 for ((__s) = 0; \ 250 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 251 (__s)++) 252 253 #define for_each_port_masked(__port, __ports_mask) \ 254 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ 255 for_each_if((__ports_mask) & BIT(__port)) 256 257 #define for_each_crtc(dev, crtc) \ 258 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 259 260 #define for_each_intel_plane(dev, intel_plane) \ 261 list_for_each_entry(intel_plane, \ 262 &(dev)->mode_config.plane_list, \ 263 base.head) 264 265 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 266 list_for_each_entry(intel_plane, \ 267 &(dev)->mode_config.plane_list, \ 268 base.head) \ 269 for_each_if((plane_mask) & \ 270 drm_plane_mask(&intel_plane->base))) 271 272 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 273 list_for_each_entry(intel_plane, \ 274 &(dev)->mode_config.plane_list, \ 275 base.head) \ 276 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 277 278 #define for_each_intel_crtc(dev, intel_crtc) \ 279 list_for_each_entry(intel_crtc, \ 280 &(dev)->mode_config.crtc_list, \ 281 base.head) 282 283 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ 284 list_for_each_entry(intel_crtc, \ 285 &(dev)->mode_config.crtc_list, \ 286 base.head) \ 287 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base)) 288 289 #define for_each_intel_encoder(dev, intel_encoder) \ 290 list_for_each_entry(intel_encoder, \ 291 &(dev)->mode_config.encoder_list, \ 292 base.head) 293 294 #define for_each_intel_dp(dev, intel_encoder) \ 295 for_each_intel_encoder(dev, intel_encoder) \ 296 for_each_if(intel_encoder_is_dp(intel_encoder)) 297 298 #define for_each_intel_connector_iter(intel_connector, iter) \ 299 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 300 301 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 302 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 303 for_each_if((intel_encoder)->base.crtc == (__crtc)) 304 305 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 306 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 307 for_each_if((intel_connector)->base.encoder == (__encoder)) 308 309 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 310 for ((__i) = 0; \ 311 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 312 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 313 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 314 (__i)++) \ 315 for_each_if(plane) 316 317 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 318 for ((__i) = 0; \ 319 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 320 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 321 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 322 (__i)++) \ 323 for_each_if(plane) 324 325 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 326 for ((__i) = 0; \ 327 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 328 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 329 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 330 (__i)++) \ 331 for_each_if(crtc) 332 333 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 334 for ((__i) = 0; \ 335 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 336 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 337 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 338 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 339 (__i)++) \ 340 for_each_if(plane) 341 342 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 343 for ((__i) = 0; \ 344 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 345 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 346 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 347 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 348 (__i)++) \ 349 for_each_if(crtc) 350 351 void intel_link_compute_m_n(u16 bpp, int nlanes, 352 int pixel_clock, int link_clock, 353 struct intel_link_m_n *m_n, 354 bool constant_n); 355 bool is_ccs_modifier(u64 modifier); 356 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); 357 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 358 u32 pixel_format, u64 modifier); 359 bool intel_plane_can_remap(const struct intel_plane_state *plane_state); 360 361 #endif 362