1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 #include <drm/i915_drm.h> 30 31 struct drm_i915_private; 32 struct intel_plane_state; 33 34 enum i915_gpio { 35 GPIOA, 36 GPIOB, 37 GPIOC, 38 GPIOD, 39 GPIOE, 40 GPIOF, 41 GPIOG, 42 GPIOH, 43 __GPIOI_UNUSED, 44 GPIOJ, 45 GPIOK, 46 GPIOL, 47 GPIOM, 48 GPION, 49 GPIOO, 50 }; 51 52 /* 53 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 54 * rest have consecutive values and match the enum values of transcoders 55 * with a 1:1 transcoder -> pipe mapping. 56 */ 57 enum pipe { 58 INVALID_PIPE = -1, 59 60 PIPE_A = 0, 61 PIPE_B, 62 PIPE_C, 63 PIPE_D, 64 _PIPE_EDP, 65 66 I915_MAX_PIPES = _PIPE_EDP 67 }; 68 69 #define pipe_name(p) ((p) + 'A') 70 71 enum transcoder { 72 /* 73 * The following transcoders have a 1:1 transcoder -> pipe mapping, 74 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 75 * rest have consecutive values and match the enum values of the pipes 76 * they map to. 77 */ 78 TRANSCODER_A = PIPE_A, 79 TRANSCODER_B = PIPE_B, 80 TRANSCODER_C = PIPE_C, 81 TRANSCODER_D = PIPE_D, 82 83 /* 84 * The following transcoders can map to any pipe, their enum value 85 * doesn't need to stay fixed. 86 */ 87 TRANSCODER_EDP, 88 TRANSCODER_DSI_0, 89 TRANSCODER_DSI_1, 90 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 91 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 92 93 I915_MAX_TRANSCODERS 94 }; 95 96 static inline const char *transcoder_name(enum transcoder transcoder) 97 { 98 switch (transcoder) { 99 case TRANSCODER_A: 100 return "A"; 101 case TRANSCODER_B: 102 return "B"; 103 case TRANSCODER_C: 104 return "C"; 105 case TRANSCODER_D: 106 return "D"; 107 case TRANSCODER_EDP: 108 return "EDP"; 109 case TRANSCODER_DSI_A: 110 return "DSI A"; 111 case TRANSCODER_DSI_C: 112 return "DSI C"; 113 default: 114 return "<invalid>"; 115 } 116 } 117 118 static inline bool transcoder_is_dsi(enum transcoder transcoder) 119 { 120 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 121 } 122 123 /* 124 * Global legacy plane identifier. Valid only for primary/sprite 125 * planes on pre-g4x, and only for primary planes on g4x-bdw. 126 */ 127 enum i9xx_plane_id { 128 PLANE_A, 129 PLANE_B, 130 PLANE_C, 131 }; 132 133 #define plane_name(p) ((p) + 'A') 134 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 135 136 /* 137 * Per-pipe plane identifier. 138 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 139 * number of planes per CRTC. Not all platforms really have this many planes, 140 * which means some arrays of size I915_MAX_PLANES may have unused entries 141 * between the topmost sprite plane and the cursor plane. 142 * 143 * This is expected to be passed to various register macros 144 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 145 */ 146 enum plane_id { 147 PLANE_PRIMARY, 148 PLANE_SPRITE0, 149 PLANE_SPRITE1, 150 PLANE_SPRITE2, 151 PLANE_SPRITE3, 152 PLANE_SPRITE4, 153 PLANE_SPRITE5, 154 PLANE_CURSOR, 155 156 I915_MAX_PLANES, 157 }; 158 159 #define for_each_plane_id_on_crtc(__crtc, __p) \ 160 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 161 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 162 163 /* 164 * Ports identifier referenced from other drivers. 165 * Expected to remain stable over time 166 */ 167 static inline const char *port_identifier(enum port port) 168 { 169 switch (port) { 170 case PORT_A: 171 return "Port A"; 172 case PORT_B: 173 return "Port B"; 174 case PORT_C: 175 return "Port C"; 176 case PORT_D: 177 return "Port D"; 178 case PORT_E: 179 return "Port E"; 180 case PORT_F: 181 return "Port F"; 182 case PORT_G: 183 return "Port G"; 184 case PORT_H: 185 return "Port H"; 186 case PORT_I: 187 return "Port I"; 188 default: 189 return "<invalid>"; 190 } 191 } 192 193 enum tc_port { 194 PORT_TC_NONE = -1, 195 196 PORT_TC1 = 0, 197 PORT_TC2, 198 PORT_TC3, 199 PORT_TC4, 200 PORT_TC5, 201 PORT_TC6, 202 203 I915_MAX_TC_PORTS 204 }; 205 206 enum tc_port_mode { 207 TC_PORT_TBT_ALT, 208 TC_PORT_DP_ALT, 209 TC_PORT_LEGACY, 210 }; 211 212 enum dpio_channel { 213 DPIO_CH0, 214 DPIO_CH1 215 }; 216 217 enum dpio_phy { 218 DPIO_PHY0, 219 DPIO_PHY1, 220 DPIO_PHY2, 221 }; 222 223 #define I915_NUM_PHYS_VLV 2 224 225 enum aux_ch { 226 AUX_CH_A, 227 AUX_CH_B, 228 AUX_CH_C, 229 AUX_CH_D, 230 AUX_CH_E, /* ICL+ */ 231 AUX_CH_F, 232 }; 233 234 #define aux_ch_name(a) ((a) + 'A') 235 236 /* Used by dp and fdi links */ 237 struct intel_link_m_n { 238 u32 tu; 239 u32 gmch_m; 240 u32 gmch_n; 241 u32 link_m; 242 u32 link_n; 243 }; 244 245 enum phy { 246 PHY_NONE = -1, 247 248 PHY_A = 0, 249 PHY_B, 250 PHY_C, 251 PHY_D, 252 PHY_E, 253 PHY_F, 254 PHY_G, 255 PHY_H, 256 PHY_I, 257 258 I915_MAX_PHYS 259 }; 260 261 #define phy_name(a) ((a) + 'A') 262 263 enum phy_fia { 264 FIA1, 265 FIA2, 266 FIA3, 267 }; 268 269 #define for_each_pipe(__dev_priv, __p) \ 270 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) 271 272 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 273 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ 274 for_each_if((__mask) & BIT(__p)) 275 276 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 277 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 278 for_each_if ((__mask) & (1 << (__t))) 279 280 #define for_each_universal_plane(__dev_priv, __pipe, __p) \ 281 for ((__p) = 0; \ 282 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ 283 (__p)++) 284 285 #define for_each_sprite(__dev_priv, __p, __s) \ 286 for ((__s) = 0; \ 287 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 288 (__s)++) 289 290 #define for_each_port_masked(__port, __ports_mask) \ 291 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ 292 for_each_if((__ports_mask) & BIT(__port)) 293 294 #define for_each_phy_masked(__phy, __phys_mask) \ 295 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 296 for_each_if((__phys_mask) & BIT(__phy)) 297 298 #define for_each_crtc(dev, crtc) \ 299 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 300 301 #define for_each_intel_plane(dev, intel_plane) \ 302 list_for_each_entry(intel_plane, \ 303 &(dev)->mode_config.plane_list, \ 304 base.head) 305 306 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 307 list_for_each_entry(intel_plane, \ 308 &(dev)->mode_config.plane_list, \ 309 base.head) \ 310 for_each_if((plane_mask) & \ 311 drm_plane_mask(&intel_plane->base))) 312 313 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 314 list_for_each_entry(intel_plane, \ 315 &(dev)->mode_config.plane_list, \ 316 base.head) \ 317 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 318 319 #define for_each_intel_crtc(dev, intel_crtc) \ 320 list_for_each_entry(intel_crtc, \ 321 &(dev)->mode_config.crtc_list, \ 322 base.head) 323 324 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ 325 list_for_each_entry(intel_crtc, \ 326 &(dev)->mode_config.crtc_list, \ 327 base.head) \ 328 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base)) 329 330 #define for_each_intel_encoder(dev, intel_encoder) \ 331 list_for_each_entry(intel_encoder, \ 332 &(dev)->mode_config.encoder_list, \ 333 base.head) 334 335 #define for_each_intel_dp(dev, intel_encoder) \ 336 for_each_intel_encoder(dev, intel_encoder) \ 337 for_each_if(intel_encoder_is_dp(intel_encoder)) 338 339 #define for_each_intel_connector_iter(intel_connector, iter) \ 340 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 341 342 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 343 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 344 for_each_if((intel_encoder)->base.crtc == (__crtc)) 345 346 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 347 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 348 for_each_if((intel_connector)->base.encoder == (__encoder)) 349 350 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 351 for ((__i) = 0; \ 352 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 353 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 354 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 355 (__i)++) \ 356 for_each_if(plane) 357 358 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 359 for ((__i) = 0; \ 360 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 361 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 362 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 363 (__i)++) \ 364 for_each_if(plane) 365 366 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 367 for ((__i) = 0; \ 368 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 369 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 370 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 371 (__i)++) \ 372 for_each_if(crtc) 373 374 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 375 for ((__i) = 0; \ 376 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 377 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 378 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 379 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 380 (__i)++) \ 381 for_each_if(plane) 382 383 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 384 for ((__i) = 0; \ 385 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 386 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 387 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 388 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 389 (__i)++) \ 390 for_each_if(crtc) 391 392 void intel_link_compute_m_n(u16 bpp, int nlanes, 393 int pixel_clock, int link_clock, 394 struct intel_link_m_n *m_n, 395 bool constant_n); 396 bool is_ccs_modifier(u64 modifier); 397 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); 398 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 399 u32 pixel_format, u64 modifier); 400 bool intel_plane_can_remap(const struct intel_plane_state *plane_state); 401 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 402 403 #endif 404