1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 30 #include "i915_reg_defs.h" 31 #include "intel_display_limits.h" 32 33 enum drm_scaling_filter; 34 struct dpll; 35 struct drm_atomic_state; 36 struct drm_connector; 37 struct drm_device; 38 struct drm_display_mode; 39 struct drm_encoder; 40 struct drm_file; 41 struct drm_format_info; 42 struct drm_framebuffer; 43 struct drm_i915_gem_object; 44 struct drm_i915_private; 45 struct drm_mode_fb_cmd2; 46 struct drm_modeset_acquire_ctx; 47 struct drm_plane; 48 struct drm_plane_state; 49 struct i915_address_space; 50 struct i915_gtt_view; 51 struct intel_atomic_state; 52 struct intel_crtc; 53 struct intel_crtc_state; 54 struct intel_digital_port; 55 struct intel_dp; 56 struct intel_encoder; 57 struct intel_initial_plane_config; 58 struct intel_link_m_n; 59 struct intel_load_detect_pipe; 60 struct intel_plane; 61 struct intel_plane_state; 62 struct intel_power_domain_mask; 63 struct intel_remapped_info; 64 struct intel_rotation_info; 65 struct pci_dev; 66 67 68 #define pipe_name(p) ((p) + 'A') 69 70 static inline const char *transcoder_name(enum transcoder transcoder) 71 { 72 switch (transcoder) { 73 case TRANSCODER_A: 74 return "A"; 75 case TRANSCODER_B: 76 return "B"; 77 case TRANSCODER_C: 78 return "C"; 79 case TRANSCODER_D: 80 return "D"; 81 case TRANSCODER_EDP: 82 return "EDP"; 83 case TRANSCODER_DSI_A: 84 return "DSI A"; 85 case TRANSCODER_DSI_C: 86 return "DSI C"; 87 default: 88 return "<invalid>"; 89 } 90 } 91 92 static inline bool transcoder_is_dsi(enum transcoder transcoder) 93 { 94 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 95 } 96 97 /* 98 * Global legacy plane identifier. Valid only for primary/sprite 99 * planes on pre-g4x, and only for primary planes on g4x-bdw. 100 */ 101 enum i9xx_plane_id { 102 PLANE_A, 103 PLANE_B, 104 PLANE_C, 105 }; 106 107 #define plane_name(p) ((p) + 'A') 108 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 109 110 #define for_each_plane_id_on_crtc(__crtc, __p) \ 111 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 112 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 113 114 #define for_each_dbuf_slice(__dev_priv, __slice) \ 115 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \ 116 for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice)) 117 118 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \ 119 for_each_dbuf_slice((__dev_priv), (__slice)) \ 120 for_each_if((__mask) & BIT(__slice)) 121 122 #define port_name(p) ((p) + 'A') 123 124 /* 125 * Ports identifier referenced from other drivers. 126 * Expected to remain stable over time 127 */ 128 static inline const char *port_identifier(enum port port) 129 { 130 switch (port) { 131 case PORT_A: 132 return "Port A"; 133 case PORT_B: 134 return "Port B"; 135 case PORT_C: 136 return "Port C"; 137 case PORT_D: 138 return "Port D"; 139 case PORT_E: 140 return "Port E"; 141 case PORT_F: 142 return "Port F"; 143 case PORT_G: 144 return "Port G"; 145 case PORT_H: 146 return "Port H"; 147 case PORT_I: 148 return "Port I"; 149 default: 150 return "<invalid>"; 151 } 152 } 153 154 enum tc_port { 155 TC_PORT_NONE = -1, 156 157 TC_PORT_1 = 0, 158 TC_PORT_2, 159 TC_PORT_3, 160 TC_PORT_4, 161 TC_PORT_5, 162 TC_PORT_6, 163 164 I915_MAX_TC_PORTS 165 }; 166 167 enum tc_port_mode { 168 TC_PORT_DISCONNECTED, 169 TC_PORT_TBT_ALT, 170 TC_PORT_DP_ALT, 171 TC_PORT_LEGACY, 172 }; 173 174 enum aux_ch { 175 AUX_CH_NONE = -1, 176 177 AUX_CH_A, 178 AUX_CH_B, 179 AUX_CH_C, 180 AUX_CH_D, 181 AUX_CH_E, /* ICL+ */ 182 AUX_CH_F, 183 AUX_CH_G, 184 AUX_CH_H, 185 AUX_CH_I, 186 187 /* tgl+ */ 188 AUX_CH_USBC1 = AUX_CH_D, 189 AUX_CH_USBC2, 190 AUX_CH_USBC3, 191 AUX_CH_USBC4, 192 AUX_CH_USBC5, 193 AUX_CH_USBC6, 194 195 /* XE_LPD repositions D/E offsets and bitfields */ 196 AUX_CH_D_XELPD = AUX_CH_USBC5, 197 AUX_CH_E_XELPD, 198 }; 199 200 #define aux_ch_name(a) ((a) + 'A') 201 202 enum phy { 203 PHY_NONE = -1, 204 205 PHY_A = 0, 206 PHY_B, 207 PHY_C, 208 PHY_D, 209 PHY_E, 210 PHY_F, 211 PHY_G, 212 PHY_H, 213 PHY_I, 214 215 I915_MAX_PHYS 216 }; 217 218 #define phy_name(a) ((a) + 'A') 219 220 enum phy_fia { 221 FIA1, 222 FIA2, 223 FIA3, 224 }; 225 226 #define for_each_hpd_pin(__pin) \ 227 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 228 229 #define for_each_pipe(__dev_priv, __p) \ 230 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ 231 for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p)) 232 233 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 234 for_each_pipe(__dev_priv, __p) \ 235 for_each_if((__mask) & BIT(__p)) 236 237 #define for_each_cpu_transcoder(__dev_priv, __t) \ 238 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 239 for_each_if (RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t)) 240 241 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 242 for_each_cpu_transcoder(__dev_priv, __t) \ 243 for_each_if ((__mask) & BIT(__t)) 244 245 #define for_each_sprite(__dev_priv, __p, __s) \ 246 for ((__s) = 0; \ 247 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 248 (__s)++) 249 250 #define for_each_port(__port) \ 251 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 252 253 #define for_each_port_masked(__port, __ports_mask) \ 254 for_each_port(__port) \ 255 for_each_if((__ports_mask) & BIT(__port)) 256 257 #define for_each_phy_masked(__phy, __phys_mask) \ 258 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 259 for_each_if((__phys_mask) & BIT(__phy)) 260 261 #define for_each_crtc(dev, crtc) \ 262 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 263 264 #define for_each_intel_plane(dev, intel_plane) \ 265 list_for_each_entry(intel_plane, \ 266 &(dev)->mode_config.plane_list, \ 267 base.head) 268 269 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 270 list_for_each_entry(intel_plane, \ 271 &(dev)->mode_config.plane_list, \ 272 base.head) \ 273 for_each_if((plane_mask) & \ 274 drm_plane_mask(&intel_plane->base)) 275 276 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 277 list_for_each_entry(intel_plane, \ 278 &(dev)->mode_config.plane_list, \ 279 base.head) \ 280 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 281 282 #define for_each_intel_crtc(dev, intel_crtc) \ 283 list_for_each_entry(intel_crtc, \ 284 &(dev)->mode_config.crtc_list, \ 285 base.head) 286 287 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \ 288 list_for_each_entry(intel_crtc, \ 289 &(dev)->mode_config.crtc_list, \ 290 base.head) \ 291 for_each_if((pipe_mask) & BIT(intel_crtc->pipe)) 292 293 #define for_each_intel_encoder(dev, intel_encoder) \ 294 list_for_each_entry(intel_encoder, \ 295 &(dev)->mode_config.encoder_list, \ 296 base.head) 297 298 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 299 list_for_each_entry(intel_encoder, \ 300 &(dev)->mode_config.encoder_list, \ 301 base.head) \ 302 for_each_if((encoder_mask) & \ 303 drm_encoder_mask(&intel_encoder->base)) 304 305 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \ 306 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 307 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \ 308 intel_encoder_can_psr(intel_encoder)) 309 310 #define for_each_intel_dp(dev, intel_encoder) \ 311 for_each_intel_encoder(dev, intel_encoder) \ 312 for_each_if(intel_encoder_is_dp(intel_encoder)) 313 314 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \ 315 for_each_intel_encoder((dev), (intel_encoder)) \ 316 for_each_if(intel_encoder_can_psr(intel_encoder)) 317 318 #define for_each_intel_connector_iter(intel_connector, iter) \ 319 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 320 321 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 322 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 323 for_each_if((intel_encoder)->base.crtc == (__crtc)) 324 325 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 326 for ((__i) = 0; \ 327 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 328 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 329 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 330 (__i)++) \ 331 for_each_if(plane) 332 333 #define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \ 334 for ((__i) = 0; \ 335 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 336 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 337 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \ 338 (__i)++) \ 339 for_each_if(crtc) 340 341 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 342 for ((__i) = 0; \ 343 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 344 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 345 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 346 (__i)++) \ 347 for_each_if(plane) 348 349 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 350 for ((__i) = 0; \ 351 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 352 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 353 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 354 (__i)++) \ 355 for_each_if(crtc) 356 357 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 358 for ((__i) = 0; \ 359 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 360 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 361 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 362 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 363 (__i)++) \ 364 for_each_if(plane) 365 366 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 367 for ((__i) = 0; \ 368 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 369 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 370 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 371 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 372 (__i)++) \ 373 for_each_if(crtc) 374 375 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 376 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 377 (__i) >= 0 && \ 378 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 379 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 380 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 381 (__i)--) \ 382 for_each_if(crtc) 383 384 #define intel_atomic_crtc_state_for_each_plane_state( \ 385 plane, plane_state, \ 386 crtc_state) \ 387 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 388 ((crtc_state)->uapi.plane_mask)) \ 389 for_each_if ((plane_state = \ 390 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) 391 392 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 393 for ((__i) = 0; \ 394 (__i) < (__state)->base.num_connector; \ 395 (__i)++) \ 396 for_each_if ((__state)->base.connectors[__i].ptr && \ 397 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 398 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 399 400 int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 401 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 402 struct intel_crtc *crtc); 403 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 404 u8 active_pipes); 405 void intel_link_compute_m_n(u16 bpp, int nlanes, 406 int pixel_clock, int link_clock, 407 struct intel_link_m_n *m_n, 408 bool fec_enable); 409 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 410 u32 pixel_format, u64 modifier); 411 enum drm_mode_status 412 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 413 const struct drm_display_mode *mode, 414 bool bigjoiner); 415 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 416 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 417 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state); 418 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state); 419 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state); 420 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state); 421 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); 422 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, 423 const struct intel_crtc_state *pipe_config, 424 bool fastset); 425 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state); 426 427 void intel_plane_destroy(struct drm_plane *plane); 428 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 429 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 430 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); 431 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state); 432 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 433 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 434 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 435 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 436 const char *name, u32 reg, int ref_freq); 437 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 438 const char *name, u32 reg); 439 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 440 unsigned int intel_fb_xy_to_linear(int x, int y, 441 const struct intel_plane_state *state, 442 int plane); 443 void intel_add_fb_offsets(int *x, int *y, 444 const struct intel_plane_state *state, int plane); 445 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 446 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); 447 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 448 int intel_display_suspend(struct drm_device *dev); 449 void intel_encoder_destroy(struct drm_encoder *encoder); 450 struct drm_display_mode * 451 intel_encoder_current_mode(struct intel_encoder *encoder); 452 void intel_encoder_get_config(struct intel_encoder *encoder, 453 struct intel_crtc_state *crtc_state); 454 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); 455 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); 456 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy); 457 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, 458 enum port port); 459 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 460 struct drm_file *file_priv); 461 462 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 463 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 464 struct intel_digital_port *dig_port, 465 unsigned int expected_mask); 466 int intel_get_load_detect_pipe(struct drm_connector *connector, 467 struct intel_load_detect_pipe *old, 468 struct drm_modeset_acquire_ctx *ctx); 469 void intel_release_load_detect_pipe(struct drm_connector *connector, 470 struct intel_load_detect_pipe *old, 471 struct drm_modeset_acquire_ctx *ctx); 472 struct drm_framebuffer * 473 intel_framebuffer_create(struct drm_i915_gem_object *obj, 474 struct drm_mode_fb_cmd2 *mode_cmd); 475 476 bool intel_fuzzy_clock_check(int clock1, int clock2); 477 478 void intel_display_prepare_reset(struct drm_i915_private *dev_priv); 479 void intel_display_finish_reset(struct drm_i915_private *dev_priv); 480 void intel_zero_m_n(struct intel_link_m_n *m_n); 481 void intel_set_m_n(struct drm_i915_private *i915, 482 const struct intel_link_m_n *m_n, 483 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 484 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 485 void intel_get_m_n(struct drm_i915_private *i915, 486 struct intel_link_m_n *m_n, 487 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 488 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 489 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 490 enum transcoder transcoder); 491 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 492 enum transcoder cpu_transcoder, 493 const struct intel_link_m_n *m_n); 494 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 495 enum transcoder cpu_transcoder, 496 const struct intel_link_m_n *m_n); 497 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 498 enum transcoder cpu_transcoder, 499 struct intel_link_m_n *m_n); 500 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 501 enum transcoder cpu_transcoder, 502 struct intel_link_m_n *m_n); 503 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 504 struct intel_crtc_state *pipe_config); 505 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 506 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config); 507 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port); 508 enum intel_display_power_domain 509 intel_aux_power_domain(struct intel_digital_port *dig_port); 510 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 511 struct intel_crtc_state *crtc_state); 512 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); 513 514 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); 515 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state); 516 517 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state); 518 519 struct intel_encoder * 520 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 521 const struct intel_crtc_state *crtc_state); 522 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 523 struct intel_plane *plane); 524 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 525 struct intel_plane_state *plane_state, 526 bool visible); 527 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state); 528 529 void intel_display_driver_register(struct drm_i915_private *i915); 530 void intel_display_driver_unregister(struct drm_i915_private *i915); 531 532 void intel_update_watermarks(struct drm_i915_private *i915); 533 534 /* modesetting */ 535 bool intel_modeset_probe_defer(struct pci_dev *pdev); 536 void intel_modeset_init_hw(struct drm_i915_private *i915); 537 int intel_modeset_init_noirq(struct drm_i915_private *i915); 538 int intel_modeset_init_nogem(struct drm_i915_private *i915); 539 int intel_modeset_init(struct drm_i915_private *i915); 540 void intel_modeset_driver_remove(struct drm_i915_private *i915); 541 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915); 542 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915); 543 void intel_display_resume(struct drm_device *dev); 544 int intel_modeset_all_pipes(struct intel_atomic_state *state, 545 const char *reason); 546 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 547 struct intel_power_domain_mask *old_domains); 548 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 549 struct intel_power_domain_mask *domains); 550 551 /* modesetting asserts */ 552 void assert_transcoder(struct drm_i915_private *dev_priv, 553 enum transcoder cpu_transcoder, bool state); 554 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true) 555 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false) 556 557 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 558 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 559 * which may not necessarily be a user visible problem. This will either 560 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 561 * enable distros and users to tailor their preferred amount of i915 abrt 562 * spam. 563 */ 564 #define I915_STATE_WARN(condition, format...) ({ \ 565 int __ret_warn_on = !!(condition); \ 566 if (unlikely(__ret_warn_on)) \ 567 if (!WARN(i915_modparams.verbose_state_checks, format)) \ 568 DRM_ERROR(format); \ 569 unlikely(__ret_warn_on); \ 570 }) 571 572 #define I915_STATE_WARN_ON(x) \ 573 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 574 575 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915); 576 577 #endif 578