1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 #include <drm/i915_drm.h> 30 31 enum link_m_n_set; 32 struct dpll; 33 struct drm_connector; 34 struct drm_device; 35 struct drm_display_mode; 36 struct drm_encoder; 37 struct drm_file; 38 struct drm_format_info; 39 struct drm_framebuffer; 40 struct drm_i915_error_state_buf; 41 struct drm_i915_gem_object; 42 struct drm_i915_private; 43 struct drm_modeset_acquire_ctx; 44 struct drm_plane; 45 struct drm_plane_state; 46 struct i915_ggtt_view; 47 struct intel_crtc; 48 struct intel_crtc_state; 49 struct intel_digital_port; 50 struct intel_dp; 51 struct intel_encoder; 52 struct intel_load_detect_pipe; 53 struct intel_plane; 54 struct intel_plane_state; 55 struct intel_remapped_info; 56 struct intel_rotation_info; 57 58 enum i915_gpio { 59 GPIOA, 60 GPIOB, 61 GPIOC, 62 GPIOD, 63 GPIOE, 64 GPIOF, 65 GPIOG, 66 GPIOH, 67 __GPIOI_UNUSED, 68 GPIOJ, 69 GPIOK, 70 GPIOL, 71 GPIOM, 72 GPION, 73 GPIOO, 74 }; 75 76 /* 77 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 78 * rest have consecutive values and match the enum values of transcoders 79 * with a 1:1 transcoder -> pipe mapping. 80 */ 81 enum pipe { 82 INVALID_PIPE = -1, 83 84 PIPE_A = 0, 85 PIPE_B, 86 PIPE_C, 87 PIPE_D, 88 _PIPE_EDP, 89 90 I915_MAX_PIPES = _PIPE_EDP 91 }; 92 93 #define pipe_name(p) ((p) + 'A') 94 95 enum transcoder { 96 /* 97 * The following transcoders have a 1:1 transcoder -> pipe mapping, 98 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 99 * rest have consecutive values and match the enum values of the pipes 100 * they map to. 101 */ 102 TRANSCODER_A = PIPE_A, 103 TRANSCODER_B = PIPE_B, 104 TRANSCODER_C = PIPE_C, 105 TRANSCODER_D = PIPE_D, 106 107 /* 108 * The following transcoders can map to any pipe, their enum value 109 * doesn't need to stay fixed. 110 */ 111 TRANSCODER_EDP, 112 TRANSCODER_DSI_0, 113 TRANSCODER_DSI_1, 114 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 115 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 116 117 I915_MAX_TRANSCODERS 118 }; 119 120 static inline const char *transcoder_name(enum transcoder transcoder) 121 { 122 switch (transcoder) { 123 case TRANSCODER_A: 124 return "A"; 125 case TRANSCODER_B: 126 return "B"; 127 case TRANSCODER_C: 128 return "C"; 129 case TRANSCODER_D: 130 return "D"; 131 case TRANSCODER_EDP: 132 return "EDP"; 133 case TRANSCODER_DSI_A: 134 return "DSI A"; 135 case TRANSCODER_DSI_C: 136 return "DSI C"; 137 default: 138 return "<invalid>"; 139 } 140 } 141 142 static inline bool transcoder_is_dsi(enum transcoder transcoder) 143 { 144 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 145 } 146 147 /* 148 * Global legacy plane identifier. Valid only for primary/sprite 149 * planes on pre-g4x, and only for primary planes on g4x-bdw. 150 */ 151 enum i9xx_plane_id { 152 PLANE_A, 153 PLANE_B, 154 PLANE_C, 155 }; 156 157 #define plane_name(p) ((p) + 'A') 158 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 159 160 /* 161 * Per-pipe plane identifier. 162 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 163 * number of planes per CRTC. Not all platforms really have this many planes, 164 * which means some arrays of size I915_MAX_PLANES may have unused entries 165 * between the topmost sprite plane and the cursor plane. 166 * 167 * This is expected to be passed to various register macros 168 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 169 */ 170 enum plane_id { 171 PLANE_PRIMARY, 172 PLANE_SPRITE0, 173 PLANE_SPRITE1, 174 PLANE_SPRITE2, 175 PLANE_SPRITE3, 176 PLANE_SPRITE4, 177 PLANE_SPRITE5, 178 PLANE_CURSOR, 179 180 I915_MAX_PLANES, 181 }; 182 183 #define for_each_plane_id_on_crtc(__crtc, __p) \ 184 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 185 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 186 187 enum port { 188 PORT_NONE = -1, 189 190 PORT_A = 0, 191 PORT_B, 192 PORT_C, 193 PORT_D, 194 PORT_E, 195 PORT_F, 196 PORT_G, 197 PORT_H, 198 PORT_I, 199 200 I915_MAX_PORTS 201 }; 202 203 #define port_name(p) ((p) + 'A') 204 205 /* 206 * Ports identifier referenced from other drivers. 207 * Expected to remain stable over time 208 */ 209 static inline const char *port_identifier(enum port port) 210 { 211 switch (port) { 212 case PORT_A: 213 return "Port A"; 214 case PORT_B: 215 return "Port B"; 216 case PORT_C: 217 return "Port C"; 218 case PORT_D: 219 return "Port D"; 220 case PORT_E: 221 return "Port E"; 222 case PORT_F: 223 return "Port F"; 224 case PORT_G: 225 return "Port G"; 226 case PORT_H: 227 return "Port H"; 228 case PORT_I: 229 return "Port I"; 230 default: 231 return "<invalid>"; 232 } 233 } 234 235 enum tc_port { 236 PORT_TC_NONE = -1, 237 238 PORT_TC1 = 0, 239 PORT_TC2, 240 PORT_TC3, 241 PORT_TC4, 242 PORT_TC5, 243 PORT_TC6, 244 245 I915_MAX_TC_PORTS 246 }; 247 248 enum tc_port_mode { 249 TC_PORT_TBT_ALT, 250 TC_PORT_DP_ALT, 251 TC_PORT_LEGACY, 252 }; 253 254 enum dpio_channel { 255 DPIO_CH0, 256 DPIO_CH1 257 }; 258 259 enum dpio_phy { 260 DPIO_PHY0, 261 DPIO_PHY1, 262 DPIO_PHY2, 263 }; 264 265 #define I915_NUM_PHYS_VLV 2 266 267 enum aux_ch { 268 AUX_CH_A, 269 AUX_CH_B, 270 AUX_CH_C, 271 AUX_CH_D, 272 AUX_CH_E, /* ICL+ */ 273 AUX_CH_F, 274 }; 275 276 #define aux_ch_name(a) ((a) + 'A') 277 278 /* Used by dp and fdi links */ 279 struct intel_link_m_n { 280 u32 tu; 281 u32 gmch_m; 282 u32 gmch_n; 283 u32 link_m; 284 u32 link_n; 285 }; 286 287 enum phy { 288 PHY_NONE = -1, 289 290 PHY_A = 0, 291 PHY_B, 292 PHY_C, 293 PHY_D, 294 PHY_E, 295 PHY_F, 296 PHY_G, 297 PHY_H, 298 PHY_I, 299 300 I915_MAX_PHYS 301 }; 302 303 #define phy_name(a) ((a) + 'A') 304 305 enum phy_fia { 306 FIA1, 307 FIA2, 308 FIA3, 309 }; 310 311 #define for_each_pipe(__dev_priv, __p) \ 312 for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) 313 314 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 315 for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) \ 316 for_each_if((__mask) & BIT(__p)) 317 318 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 319 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 320 for_each_if ((__mask) & (1 << (__t))) 321 322 #define for_each_universal_plane(__dev_priv, __pipe, __p) \ 323 for ((__p) = 0; \ 324 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ 325 (__p)++) 326 327 #define for_each_sprite(__dev_priv, __p, __s) \ 328 for ((__s) = 0; \ 329 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 330 (__s)++) 331 332 #define for_each_port_masked(__port, __ports_mask) \ 333 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ 334 for_each_if((__ports_mask) & BIT(__port)) 335 336 #define for_each_phy_masked(__phy, __phys_mask) \ 337 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 338 for_each_if((__phys_mask) & BIT(__phy)) 339 340 #define for_each_crtc(dev, crtc) \ 341 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 342 343 #define for_each_intel_plane(dev, intel_plane) \ 344 list_for_each_entry(intel_plane, \ 345 &(dev)->mode_config.plane_list, \ 346 base.head) 347 348 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 349 list_for_each_entry(intel_plane, \ 350 &(dev)->mode_config.plane_list, \ 351 base.head) \ 352 for_each_if((plane_mask) & \ 353 drm_plane_mask(&intel_plane->base))) 354 355 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 356 list_for_each_entry(intel_plane, \ 357 &(dev)->mode_config.plane_list, \ 358 base.head) \ 359 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 360 361 #define for_each_intel_crtc(dev, intel_crtc) \ 362 list_for_each_entry(intel_crtc, \ 363 &(dev)->mode_config.crtc_list, \ 364 base.head) 365 366 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ 367 list_for_each_entry(intel_crtc, \ 368 &(dev)->mode_config.crtc_list, \ 369 base.head) \ 370 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base)) 371 372 #define for_each_intel_encoder(dev, intel_encoder) \ 373 list_for_each_entry(intel_encoder, \ 374 &(dev)->mode_config.encoder_list, \ 375 base.head) 376 377 #define for_each_intel_dp(dev, intel_encoder) \ 378 for_each_intel_encoder(dev, intel_encoder) \ 379 for_each_if(intel_encoder_is_dp(intel_encoder)) 380 381 #define for_each_intel_connector_iter(intel_connector, iter) \ 382 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 383 384 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 385 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 386 for_each_if((intel_encoder)->base.crtc == (__crtc)) 387 388 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 389 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 390 for_each_if((intel_connector)->base.encoder == (__encoder)) 391 392 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 393 for ((__i) = 0; \ 394 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 395 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 396 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 397 (__i)++) \ 398 for_each_if(plane) 399 400 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 401 for ((__i) = 0; \ 402 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 403 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 404 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 405 (__i)++) \ 406 for_each_if(plane) 407 408 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 409 for ((__i) = 0; \ 410 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 411 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 412 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 413 (__i)++) \ 414 for_each_if(crtc) 415 416 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 417 for ((__i) = 0; \ 418 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 419 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 420 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 421 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 422 (__i)++) \ 423 for_each_if(plane) 424 425 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 426 for ((__i) = 0; \ 427 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 428 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 429 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 430 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 431 (__i)++) \ 432 for_each_if(crtc) 433 434 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 435 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 436 (__i) >= 0 && \ 437 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 438 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 439 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 440 (__i)--) \ 441 for_each_if(crtc) 442 443 void intel_link_compute_m_n(u16 bpp, int nlanes, 444 int pixel_clock, int link_clock, 445 struct intel_link_m_n *m_n, 446 bool constant_n, bool fec_enable); 447 bool is_ccs_modifier(u64 modifier); 448 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); 449 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 450 u32 pixel_format, u64 modifier); 451 bool intel_plane_can_remap(const struct intel_plane_state *plane_state); 452 enum drm_mode_status 453 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 454 const struct drm_display_mode *mode); 455 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 456 457 void intel_plane_destroy(struct drm_plane *plane); 458 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 459 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 460 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); 461 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 462 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 463 const char *name, u32 reg, int ref_freq); 464 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 465 const char *name, u32 reg); 466 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); 467 void lpt_disable_iclkip(struct drm_i915_private *dev_priv); 468 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 469 unsigned int intel_fb_xy_to_linear(int x, int y, 470 const struct intel_plane_state *state, 471 int plane); 472 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, 473 int color_plane, unsigned int height); 474 void intel_add_fb_offsets(int *x, int *y, 475 const struct intel_plane_state *state, int plane); 476 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 477 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); 478 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 479 int intel_display_suspend(struct drm_device *dev); 480 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); 481 void intel_encoder_destroy(struct drm_encoder *encoder); 482 struct drm_display_mode * 483 intel_encoder_current_mode(struct intel_encoder *encoder); 484 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); 485 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); 486 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, 487 enum port port); 488 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 489 struct drm_file *file_priv); 490 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 491 enum pipe pipe); 492 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); 493 494 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); 495 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 496 struct intel_digital_port *dport, 497 unsigned int expected_mask); 498 int intel_get_load_detect_pipe(struct drm_connector *connector, 499 const struct drm_display_mode *mode, 500 struct intel_load_detect_pipe *old, 501 struct drm_modeset_acquire_ctx *ctx); 502 void intel_release_load_detect_pipe(struct drm_connector *connector, 503 struct intel_load_detect_pipe *old, 504 struct drm_modeset_acquire_ctx *ctx); 505 struct i915_vma * 506 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, 507 const struct i915_ggtt_view *view, 508 bool uses_fence, 509 unsigned long *out_flags); 510 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags); 511 struct drm_framebuffer * 512 intel_framebuffer_create(struct drm_i915_gem_object *obj, 513 struct drm_mode_fb_cmd2 *mode_cmd); 514 int intel_prepare_plane_fb(struct drm_plane *plane, 515 struct drm_plane_state *new_state); 516 void intel_cleanup_plane_fb(struct drm_plane *plane, 517 struct drm_plane_state *old_state); 518 519 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 520 enum pipe pipe); 521 522 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 523 const struct dpll *dpll); 524 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); 525 int lpt_get_iclkip(struct drm_i915_private *dev_priv); 526 bool intel_fuzzy_clock_check(int clock1, int clock2); 527 528 void intel_prepare_reset(struct drm_i915_private *dev_priv); 529 void intel_finish_reset(struct drm_i915_private *dev_priv); 530 void intel_dp_get_m_n(struct intel_crtc *crtc, 531 struct intel_crtc_state *pipe_config); 532 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, 533 enum link_m_n_set m_n); 534 void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp, 535 const struct intel_crtc_state *crtc_state); 536 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 537 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 538 struct dpll *best_clock); 539 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); 540 541 bool intel_crtc_active(struct intel_crtc *crtc); 542 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); 543 void hsw_enable_ips(const struct intel_crtc_state *crtc_state); 544 void hsw_disable_ips(const struct intel_crtc_state *crtc_state); 545 enum intel_display_power_domain intel_port_to_power_domain(enum port port); 546 enum intel_display_power_domain 547 intel_aux_power_domain(struct intel_digital_port *dig_port); 548 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 549 struct intel_crtc_state *pipe_config); 550 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 551 struct intel_crtc_state *crtc_state); 552 553 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center); 554 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); 555 int skl_max_scale(const struct intel_crtc_state *crtc_state, 556 const struct drm_format_info *format); 557 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, 558 const struct intel_plane_state *plane_state); 559 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state); 560 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 561 const struct intel_plane_state *plane_state); 562 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state); 563 u32 skl_plane_stride(const struct intel_plane_state *plane_state, 564 int plane); 565 int skl_check_plane_surface(struct intel_plane_state *plane_state); 566 int i9xx_check_plane_surface(struct intel_plane_state *plane_state); 567 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); 568 unsigned int i9xx_plane_max_stride(struct intel_plane *plane, 569 u32 pixel_format, u64 modifier, 570 unsigned int rotation); 571 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); 572 573 struct intel_display_error_state * 574 intel_display_capture_error_state(struct drm_i915_private *dev_priv); 575 void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 576 struct intel_display_error_state *error); 577 578 /* modesetting */ 579 void intel_modeset_init_hw(struct drm_i915_private *i915); 580 int intel_modeset_init(struct drm_i915_private *i915); 581 void intel_modeset_driver_remove(struct drm_i915_private *i915); 582 void intel_display_resume(struct drm_device *dev); 583 void intel_init_pch_refclk(struct drm_i915_private *dev_priv); 584 585 /* modesetting asserts */ 586 void assert_panel_unlocked(struct drm_i915_private *dev_priv, 587 enum pipe pipe); 588 void assert_pll(struct drm_i915_private *dev_priv, 589 enum pipe pipe, bool state); 590 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 591 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 592 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); 593 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) 594 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) 595 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 596 enum pipe pipe, bool state); 597 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) 598 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) 599 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); 600 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) 601 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) 602 603 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 604 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 605 * which may not necessarily be a user visible problem. This will either 606 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 607 * enable distros and users to tailor their preferred amount of i915 abrt 608 * spam. 609 */ 610 #define I915_STATE_WARN(condition, format...) ({ \ 611 int __ret_warn_on = !!(condition); \ 612 if (unlikely(__ret_warn_on)) \ 613 if (!WARN(i915_modparams.verbose_state_checks, format)) \ 614 DRM_ERROR(format); \ 615 unlikely(__ret_warn_on); \ 616 }) 617 618 #define I915_STATE_WARN_ON(x) \ 619 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 620 621 #endif 622