1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 30 enum link_m_n_set; 31 enum drm_scaling_filter; 32 struct dpll; 33 struct drm_connector; 34 struct drm_device; 35 struct drm_display_mode; 36 struct drm_encoder; 37 struct drm_file; 38 struct drm_format_info; 39 struct drm_framebuffer; 40 struct drm_i915_error_state_buf; 41 struct drm_i915_gem_object; 42 struct drm_i915_private; 43 struct drm_mode_fb_cmd2; 44 struct drm_modeset_acquire_ctx; 45 struct drm_plane; 46 struct drm_plane_state; 47 struct i915_ggtt_view; 48 struct intel_atomic_state; 49 struct intel_crtc; 50 struct intel_crtc_state; 51 struct intel_crtc_state; 52 struct intel_digital_port; 53 struct intel_dp; 54 struct intel_encoder; 55 struct intel_initial_plane_config; 56 struct intel_load_detect_pipe; 57 struct intel_plane; 58 struct intel_plane_state; 59 struct intel_remapped_info; 60 struct intel_rotation_info; 61 62 enum i915_gpio { 63 GPIOA, 64 GPIOB, 65 GPIOC, 66 GPIOD, 67 GPIOE, 68 GPIOF, 69 GPIOG, 70 GPIOH, 71 __GPIOI_UNUSED, 72 GPIOJ, 73 GPIOK, 74 GPIOL, 75 GPIOM, 76 GPION, 77 GPIOO, 78 }; 79 80 /* 81 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 82 * rest have consecutive values and match the enum values of transcoders 83 * with a 1:1 transcoder -> pipe mapping. 84 */ 85 enum pipe { 86 INVALID_PIPE = -1, 87 88 PIPE_A = 0, 89 PIPE_B, 90 PIPE_C, 91 PIPE_D, 92 _PIPE_EDP, 93 94 I915_MAX_PIPES = _PIPE_EDP 95 }; 96 97 #define pipe_name(p) ((p) + 'A') 98 99 enum transcoder { 100 INVALID_TRANSCODER = -1, 101 /* 102 * The following transcoders have a 1:1 transcoder -> pipe mapping, 103 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 104 * rest have consecutive values and match the enum values of the pipes 105 * they map to. 106 */ 107 TRANSCODER_A = PIPE_A, 108 TRANSCODER_B = PIPE_B, 109 TRANSCODER_C = PIPE_C, 110 TRANSCODER_D = PIPE_D, 111 112 /* 113 * The following transcoders can map to any pipe, their enum value 114 * doesn't need to stay fixed. 115 */ 116 TRANSCODER_EDP, 117 TRANSCODER_DSI_0, 118 TRANSCODER_DSI_1, 119 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 120 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 121 122 I915_MAX_TRANSCODERS 123 }; 124 125 static inline const char *transcoder_name(enum transcoder transcoder) 126 { 127 switch (transcoder) { 128 case TRANSCODER_A: 129 return "A"; 130 case TRANSCODER_B: 131 return "B"; 132 case TRANSCODER_C: 133 return "C"; 134 case TRANSCODER_D: 135 return "D"; 136 case TRANSCODER_EDP: 137 return "EDP"; 138 case TRANSCODER_DSI_A: 139 return "DSI A"; 140 case TRANSCODER_DSI_C: 141 return "DSI C"; 142 default: 143 return "<invalid>"; 144 } 145 } 146 147 static inline bool transcoder_is_dsi(enum transcoder transcoder) 148 { 149 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 150 } 151 152 /* 153 * Global legacy plane identifier. Valid only for primary/sprite 154 * planes on pre-g4x, and only for primary planes on g4x-bdw. 155 */ 156 enum i9xx_plane_id { 157 PLANE_A, 158 PLANE_B, 159 PLANE_C, 160 }; 161 162 #define plane_name(p) ((p) + 'A') 163 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 164 165 /* 166 * Per-pipe plane identifier. 167 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 168 * number of planes per CRTC. Not all platforms really have this many planes, 169 * which means some arrays of size I915_MAX_PLANES may have unused entries 170 * between the topmost sprite plane and the cursor plane. 171 * 172 * This is expected to be passed to various register macros 173 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 174 */ 175 enum plane_id { 176 PLANE_PRIMARY, 177 PLANE_SPRITE0, 178 PLANE_SPRITE1, 179 PLANE_SPRITE2, 180 PLANE_SPRITE3, 181 PLANE_SPRITE4, 182 PLANE_SPRITE5, 183 PLANE_CURSOR, 184 185 I915_MAX_PLANES, 186 }; 187 188 #define for_each_plane_id_on_crtc(__crtc, __p) \ 189 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 190 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 191 192 #define for_each_dbuf_slice_in_mask(__slice, __mask) \ 193 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \ 194 for_each_if((BIT(__slice)) & (__mask)) 195 196 #define for_each_dbuf_slice(__slice) \ 197 for_each_dbuf_slice_in_mask(__slice, BIT(I915_MAX_DBUF_SLICES) - 1) 198 199 enum port { 200 PORT_NONE = -1, 201 202 PORT_A = 0, 203 PORT_B, 204 PORT_C, 205 PORT_D, 206 PORT_E, 207 PORT_F, 208 PORT_G, 209 PORT_H, 210 PORT_I, 211 212 /* tgl+ */ 213 PORT_TC1 = PORT_D, 214 PORT_TC2, 215 PORT_TC3, 216 PORT_TC4, 217 PORT_TC5, 218 PORT_TC6, 219 220 I915_MAX_PORTS 221 }; 222 223 #define port_name(p) ((p) + 'A') 224 225 /* 226 * Ports identifier referenced from other drivers. 227 * Expected to remain stable over time 228 */ 229 static inline const char *port_identifier(enum port port) 230 { 231 switch (port) { 232 case PORT_A: 233 return "Port A"; 234 case PORT_B: 235 return "Port B"; 236 case PORT_C: 237 return "Port C"; 238 case PORT_D: 239 return "Port D"; 240 case PORT_E: 241 return "Port E"; 242 case PORT_F: 243 return "Port F"; 244 case PORT_G: 245 return "Port G"; 246 case PORT_H: 247 return "Port H"; 248 case PORT_I: 249 return "Port I"; 250 default: 251 return "<invalid>"; 252 } 253 } 254 255 enum tc_port { 256 TC_PORT_NONE = -1, 257 258 TC_PORT_1 = 0, 259 TC_PORT_2, 260 TC_PORT_3, 261 TC_PORT_4, 262 TC_PORT_5, 263 TC_PORT_6, 264 265 I915_MAX_TC_PORTS 266 }; 267 268 enum tc_port_mode { 269 TC_PORT_TBT_ALT, 270 TC_PORT_DP_ALT, 271 TC_PORT_LEGACY, 272 }; 273 274 enum dpio_channel { 275 DPIO_CH0, 276 DPIO_CH1 277 }; 278 279 enum dpio_phy { 280 DPIO_PHY0, 281 DPIO_PHY1, 282 DPIO_PHY2, 283 }; 284 285 enum aux_ch { 286 AUX_CH_A, 287 AUX_CH_B, 288 AUX_CH_C, 289 AUX_CH_D, 290 AUX_CH_E, /* ICL+ */ 291 AUX_CH_F, 292 AUX_CH_G, 293 AUX_CH_H, 294 AUX_CH_I, 295 296 /* tgl+ */ 297 AUX_CH_USBC1 = AUX_CH_D, 298 AUX_CH_USBC2, 299 AUX_CH_USBC3, 300 AUX_CH_USBC4, 301 AUX_CH_USBC5, 302 AUX_CH_USBC6, 303 }; 304 305 #define aux_ch_name(a) ((a) + 'A') 306 307 /* Used by dp and fdi links */ 308 struct intel_link_m_n { 309 u32 tu; 310 u32 gmch_m; 311 u32 gmch_n; 312 u32 link_m; 313 u32 link_n; 314 }; 315 316 enum phy { 317 PHY_NONE = -1, 318 319 PHY_A = 0, 320 PHY_B, 321 PHY_C, 322 PHY_D, 323 PHY_E, 324 PHY_F, 325 PHY_G, 326 PHY_H, 327 PHY_I, 328 329 I915_MAX_PHYS 330 }; 331 332 #define phy_name(a) ((a) + 'A') 333 334 enum phy_fia { 335 FIA1, 336 FIA2, 337 FIA3, 338 }; 339 340 #define for_each_pipe(__dev_priv, __p) \ 341 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ 342 for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p)) 343 344 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 345 for_each_pipe(__dev_priv, __p) \ 346 for_each_if((__mask) & BIT(__p)) 347 348 #define for_each_cpu_transcoder(__dev_priv, __t) \ 349 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 350 for_each_if (INTEL_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t)) 351 352 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 353 for_each_cpu_transcoder(__dev_priv, __t) \ 354 for_each_if ((__mask) & BIT(__t)) 355 356 #define for_each_sprite(__dev_priv, __p, __s) \ 357 for ((__s) = 0; \ 358 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 359 (__s)++) 360 361 #define for_each_port(__port) \ 362 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 363 364 #define for_each_port_masked(__port, __ports_mask) \ 365 for_each_port(__port) \ 366 for_each_if((__ports_mask) & BIT(__port)) 367 368 #define for_each_phy_masked(__phy, __phys_mask) \ 369 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 370 for_each_if((__phys_mask) & BIT(__phy)) 371 372 #define for_each_crtc(dev, crtc) \ 373 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 374 375 #define for_each_intel_plane(dev, intel_plane) \ 376 list_for_each_entry(intel_plane, \ 377 &(dev)->mode_config.plane_list, \ 378 base.head) 379 380 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 381 list_for_each_entry(intel_plane, \ 382 &(dev)->mode_config.plane_list, \ 383 base.head) \ 384 for_each_if((plane_mask) & \ 385 drm_plane_mask(&intel_plane->base)) 386 387 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 388 list_for_each_entry(intel_plane, \ 389 &(dev)->mode_config.plane_list, \ 390 base.head) \ 391 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 392 393 #define for_each_intel_crtc(dev, intel_crtc) \ 394 list_for_each_entry(intel_crtc, \ 395 &(dev)->mode_config.crtc_list, \ 396 base.head) 397 398 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ 399 list_for_each_entry(intel_crtc, \ 400 &(dev)->mode_config.crtc_list, \ 401 base.head) \ 402 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base)) 403 404 #define for_each_intel_encoder(dev, intel_encoder) \ 405 list_for_each_entry(intel_encoder, \ 406 &(dev)->mode_config.encoder_list, \ 407 base.head) 408 409 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 410 list_for_each_entry(intel_encoder, \ 411 &(dev)->mode_config.encoder_list, \ 412 base.head) \ 413 for_each_if((encoder_mask) & \ 414 drm_encoder_mask(&intel_encoder->base)) 415 416 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \ 417 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 418 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \ 419 intel_encoder_can_psr(intel_encoder)) 420 421 #define for_each_intel_dp(dev, intel_encoder) \ 422 for_each_intel_encoder(dev, intel_encoder) \ 423 for_each_if(intel_encoder_is_dp(intel_encoder)) 424 425 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \ 426 for_each_intel_encoder((dev), (intel_encoder)) \ 427 for_each_if(intel_encoder_can_psr(intel_encoder)) 428 429 #define for_each_intel_connector_iter(intel_connector, iter) \ 430 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 431 432 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 433 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 434 for_each_if((intel_encoder)->base.crtc == (__crtc)) 435 436 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 437 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 438 for_each_if((intel_connector)->base.encoder == (__encoder)) 439 440 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 441 for ((__i) = 0; \ 442 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 443 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 444 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 445 (__i)++) \ 446 for_each_if(plane) 447 448 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 449 for ((__i) = 0; \ 450 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 451 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 452 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 453 (__i)++) \ 454 for_each_if(plane) 455 456 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 457 for ((__i) = 0; \ 458 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 459 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 460 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 461 (__i)++) \ 462 for_each_if(crtc) 463 464 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 465 for ((__i) = 0; \ 466 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 467 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 468 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 469 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 470 (__i)++) \ 471 for_each_if(plane) 472 473 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 474 for ((__i) = 0; \ 475 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 476 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 477 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 478 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 479 (__i)++) \ 480 for_each_if(crtc) 481 482 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 483 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 484 (__i) >= 0 && \ 485 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 486 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 487 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 488 (__i)--) \ 489 for_each_if(crtc) 490 491 #define intel_atomic_crtc_state_for_each_plane_state( \ 492 plane, plane_state, \ 493 crtc_state) \ 494 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 495 ((crtc_state)->uapi.plane_mask)) \ 496 for_each_if ((plane_state = \ 497 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) 498 499 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 500 for ((__i) = 0; \ 501 (__i) < (__state)->base.num_connector; \ 502 (__i)++) \ 503 for_each_if ((__state)->base.connectors[__i].ptr && \ 504 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 505 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 506 507 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 508 struct intel_crtc *crtc); 509 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 510 u8 active_pipes); 511 void intel_link_compute_m_n(u16 bpp, int nlanes, 512 int pixel_clock, int link_clock, 513 struct intel_link_m_n *m_n, 514 bool constant_n, bool fec_enable); 515 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); 516 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 517 u32 pixel_format, u64 modifier); 518 bool intel_plane_can_remap(const struct intel_plane_state *plane_state); 519 enum drm_mode_status 520 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 521 const struct drm_display_mode *mode, 522 bool bigjoiner); 523 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 524 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 525 526 void intel_plane_destroy(struct drm_plane *plane); 527 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state); 528 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state); 529 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 530 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 531 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); 532 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 533 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 534 const char *name, u32 reg, int ref_freq); 535 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 536 const char *name, u32 reg); 537 void lpt_pch_enable(const struct intel_crtc_state *crtc_state); 538 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); 539 void lpt_disable_iclkip(struct drm_i915_private *dev_priv); 540 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 541 unsigned int intel_fb_xy_to_linear(int x, int y, 542 const struct intel_plane_state *state, 543 int plane); 544 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, 545 int color_plane, unsigned int height); 546 void intel_add_fb_offsets(int *x, int *y, 547 const struct intel_plane_state *state, int plane); 548 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 549 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); 550 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 551 int intel_display_suspend(struct drm_device *dev); 552 void intel_encoder_destroy(struct drm_encoder *encoder); 553 struct drm_display_mode * 554 intel_encoder_current_mode(struct intel_encoder *encoder); 555 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); 556 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); 557 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, 558 enum port port); 559 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 560 struct drm_file *file_priv); 561 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); 562 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state); 563 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state); 564 565 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 566 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 567 struct intel_digital_port *dig_port, 568 unsigned int expected_mask); 569 int intel_get_load_detect_pipe(struct drm_connector *connector, 570 struct intel_load_detect_pipe *old, 571 struct drm_modeset_acquire_ctx *ctx); 572 void intel_release_load_detect_pipe(struct drm_connector *connector, 573 struct intel_load_detect_pipe *old, 574 struct drm_modeset_acquire_ctx *ctx); 575 struct i915_vma * 576 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, 577 const struct i915_ggtt_view *view, 578 bool uses_fence, 579 unsigned long *out_flags); 580 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags); 581 struct drm_framebuffer * 582 intel_framebuffer_create(struct drm_i915_gem_object *obj, 583 struct drm_mode_fb_cmd2 *mode_cmd); 584 int intel_prepare_plane_fb(struct drm_plane *plane, 585 struct drm_plane_state *new_state); 586 void intel_cleanup_plane_fb(struct drm_plane *plane, 587 struct drm_plane_state *old_state); 588 589 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 590 enum pipe pipe); 591 592 int lpt_get_iclkip(struct drm_i915_private *dev_priv); 593 bool intel_fuzzy_clock_check(int clock1, int clock2); 594 595 void intel_display_prepare_reset(struct drm_i915_private *dev_priv); 596 void intel_display_finish_reset(struct drm_i915_private *dev_priv); 597 void intel_dp_get_m_n(struct intel_crtc *crtc, 598 struct intel_crtc_state *pipe_config); 599 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, 600 enum link_m_n_set m_n); 601 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 602 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 603 struct dpll *best_clock); 604 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); 605 606 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); 607 void hsw_enable_ips(const struct intel_crtc_state *crtc_state); 608 void hsw_disable_ips(const struct intel_crtc_state *crtc_state); 609 enum intel_display_power_domain intel_port_to_power_domain(enum port port); 610 enum intel_display_power_domain 611 intel_aux_power_domain(struct intel_digital_port *dig_port); 612 enum intel_display_power_domain 613 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch); 614 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 615 struct intel_crtc_state *crtc_state); 616 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); 617 618 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); 619 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state); 620 621 struct intel_display_error_state * 622 intel_display_capture_error_state(struct drm_i915_private *dev_priv); 623 void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 624 struct intel_display_error_state *error); 625 626 bool 627 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, 628 u64 modifier); 629 630 int intel_plane_compute_gtt(struct intel_plane_state *plane_state); 631 u32 intel_plane_compute_aligned_offset(int *x, int *y, 632 const struct intel_plane_state *state, 633 int color_plane); 634 int intel_plane_pin_fb(struct intel_plane_state *plane_state); 635 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state); 636 struct intel_encoder * 637 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 638 const struct intel_crtc_state *crtc_state); 639 640 unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, 641 int color_plane); 642 void intel_fb_plane_get_subsampling(int *hsub, int *vsub, 643 const struct drm_framebuffer *fb, 644 int color_plane); 645 u32 intel_plane_adjust_aligned_offset(int *x, int *y, 646 const struct intel_plane_state *state, 647 int color_plane, 648 u32 old_offset, u32 new_offset); 649 unsigned int intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane); 650 unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane); 651 652 void intel_display_driver_register(struct drm_i915_private *i915); 653 void intel_display_driver_unregister(struct drm_i915_private *i915); 654 655 /* modesetting */ 656 void intel_modeset_init_hw(struct drm_i915_private *i915); 657 int intel_modeset_init_noirq(struct drm_i915_private *i915); 658 int intel_modeset_init_nogem(struct drm_i915_private *i915); 659 int intel_modeset_init(struct drm_i915_private *i915); 660 void intel_modeset_driver_remove(struct drm_i915_private *i915); 661 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915); 662 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915); 663 void intel_display_resume(struct drm_device *dev); 664 void intel_init_pch_refclk(struct drm_i915_private *dev_priv); 665 666 /* modesetting asserts */ 667 void assert_panel_unlocked(struct drm_i915_private *dev_priv, 668 enum pipe pipe); 669 void assert_pll(struct drm_i915_private *dev_priv, 670 enum pipe pipe, bool state); 671 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 672 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 673 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); 674 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) 675 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) 676 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 677 enum pipe pipe, bool state); 678 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) 679 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) 680 void assert_pipe(struct drm_i915_private *dev_priv, 681 enum transcoder cpu_transcoder, bool state); 682 #define assert_pipe_enabled(d, t) assert_pipe(d, t, true) 683 #define assert_pipe_disabled(d, t) assert_pipe(d, t, false) 684 685 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 686 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 687 * which may not necessarily be a user visible problem. This will either 688 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 689 * enable distros and users to tailor their preferred amount of i915 abrt 690 * spam. 691 */ 692 #define I915_STATE_WARN(condition, format...) ({ \ 693 int __ret_warn_on = !!(condition); \ 694 if (unlikely(__ret_warn_on)) \ 695 if (!WARN(i915_modparams.verbose_state_checks, format)) \ 696 DRM_ERROR(format); \ 697 unlikely(__ret_warn_on); \ 698 }) 699 700 #define I915_STATE_WARN_ON(x) \ 701 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 702 703 #endif 704