1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 #include <drm/i915_drm.h> 30 31 enum link_m_n_set; 32 struct dpll; 33 struct drm_connector; 34 struct drm_device; 35 struct drm_encoder; 36 struct drm_file; 37 struct drm_framebuffer; 38 struct drm_i915_error_state_buf; 39 struct drm_i915_gem_object; 40 struct drm_i915_private; 41 struct drm_modeset_acquire_ctx; 42 struct drm_plane; 43 struct drm_plane_state; 44 struct i915_ggtt_view; 45 struct intel_crtc; 46 struct intel_crtc_state; 47 struct intel_digital_port; 48 struct intel_dp; 49 struct intel_encoder; 50 struct intel_load_detect_pipe; 51 struct intel_plane; 52 struct intel_plane_state; 53 struct intel_remapped_info; 54 struct intel_rotation_info; 55 56 enum i915_gpio { 57 GPIOA, 58 GPIOB, 59 GPIOC, 60 GPIOD, 61 GPIOE, 62 GPIOF, 63 GPIOG, 64 GPIOH, 65 __GPIOI_UNUSED, 66 GPIOJ, 67 GPIOK, 68 GPIOL, 69 GPIOM, 70 GPION, 71 GPIOO, 72 }; 73 74 /* 75 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 76 * rest have consecutive values and match the enum values of transcoders 77 * with a 1:1 transcoder -> pipe mapping. 78 */ 79 enum pipe { 80 INVALID_PIPE = -1, 81 82 PIPE_A = 0, 83 PIPE_B, 84 PIPE_C, 85 PIPE_D, 86 _PIPE_EDP, 87 88 I915_MAX_PIPES = _PIPE_EDP 89 }; 90 91 #define pipe_name(p) ((p) + 'A') 92 93 enum transcoder { 94 /* 95 * The following transcoders have a 1:1 transcoder -> pipe mapping, 96 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 97 * rest have consecutive values and match the enum values of the pipes 98 * they map to. 99 */ 100 TRANSCODER_A = PIPE_A, 101 TRANSCODER_B = PIPE_B, 102 TRANSCODER_C = PIPE_C, 103 TRANSCODER_D = PIPE_D, 104 105 /* 106 * The following transcoders can map to any pipe, their enum value 107 * doesn't need to stay fixed. 108 */ 109 TRANSCODER_EDP, 110 TRANSCODER_DSI_0, 111 TRANSCODER_DSI_1, 112 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 113 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 114 115 I915_MAX_TRANSCODERS 116 }; 117 118 static inline const char *transcoder_name(enum transcoder transcoder) 119 { 120 switch (transcoder) { 121 case TRANSCODER_A: 122 return "A"; 123 case TRANSCODER_B: 124 return "B"; 125 case TRANSCODER_C: 126 return "C"; 127 case TRANSCODER_D: 128 return "D"; 129 case TRANSCODER_EDP: 130 return "EDP"; 131 case TRANSCODER_DSI_A: 132 return "DSI A"; 133 case TRANSCODER_DSI_C: 134 return "DSI C"; 135 default: 136 return "<invalid>"; 137 } 138 } 139 140 static inline bool transcoder_is_dsi(enum transcoder transcoder) 141 { 142 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 143 } 144 145 /* 146 * Global legacy plane identifier. Valid only for primary/sprite 147 * planes on pre-g4x, and only for primary planes on g4x-bdw. 148 */ 149 enum i9xx_plane_id { 150 PLANE_A, 151 PLANE_B, 152 PLANE_C, 153 }; 154 155 #define plane_name(p) ((p) + 'A') 156 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 157 158 /* 159 * Per-pipe plane identifier. 160 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 161 * number of planes per CRTC. Not all platforms really have this many planes, 162 * which means some arrays of size I915_MAX_PLANES may have unused entries 163 * between the topmost sprite plane and the cursor plane. 164 * 165 * This is expected to be passed to various register macros 166 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 167 */ 168 enum plane_id { 169 PLANE_PRIMARY, 170 PLANE_SPRITE0, 171 PLANE_SPRITE1, 172 PLANE_SPRITE2, 173 PLANE_SPRITE3, 174 PLANE_SPRITE4, 175 PLANE_SPRITE5, 176 PLANE_CURSOR, 177 178 I915_MAX_PLANES, 179 }; 180 181 #define for_each_plane_id_on_crtc(__crtc, __p) \ 182 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 183 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 184 185 /* 186 * Ports identifier referenced from other drivers. 187 * Expected to remain stable over time 188 */ 189 static inline const char *port_identifier(enum port port) 190 { 191 switch (port) { 192 case PORT_A: 193 return "Port A"; 194 case PORT_B: 195 return "Port B"; 196 case PORT_C: 197 return "Port C"; 198 case PORT_D: 199 return "Port D"; 200 case PORT_E: 201 return "Port E"; 202 case PORT_F: 203 return "Port F"; 204 case PORT_G: 205 return "Port G"; 206 case PORT_H: 207 return "Port H"; 208 case PORT_I: 209 return "Port I"; 210 default: 211 return "<invalid>"; 212 } 213 } 214 215 enum tc_port { 216 PORT_TC_NONE = -1, 217 218 PORT_TC1 = 0, 219 PORT_TC2, 220 PORT_TC3, 221 PORT_TC4, 222 PORT_TC5, 223 PORT_TC6, 224 225 I915_MAX_TC_PORTS 226 }; 227 228 enum tc_port_mode { 229 TC_PORT_TBT_ALT, 230 TC_PORT_DP_ALT, 231 TC_PORT_LEGACY, 232 }; 233 234 enum dpio_channel { 235 DPIO_CH0, 236 DPIO_CH1 237 }; 238 239 enum dpio_phy { 240 DPIO_PHY0, 241 DPIO_PHY1, 242 DPIO_PHY2, 243 }; 244 245 #define I915_NUM_PHYS_VLV 2 246 247 enum aux_ch { 248 AUX_CH_A, 249 AUX_CH_B, 250 AUX_CH_C, 251 AUX_CH_D, 252 AUX_CH_E, /* ICL+ */ 253 AUX_CH_F, 254 }; 255 256 #define aux_ch_name(a) ((a) + 'A') 257 258 /* Used by dp and fdi links */ 259 struct intel_link_m_n { 260 u32 tu; 261 u32 gmch_m; 262 u32 gmch_n; 263 u32 link_m; 264 u32 link_n; 265 }; 266 267 enum phy { 268 PHY_NONE = -1, 269 270 PHY_A = 0, 271 PHY_B, 272 PHY_C, 273 PHY_D, 274 PHY_E, 275 PHY_F, 276 PHY_G, 277 PHY_H, 278 PHY_I, 279 280 I915_MAX_PHYS 281 }; 282 283 #define phy_name(a) ((a) + 'A') 284 285 enum phy_fia { 286 FIA1, 287 FIA2, 288 FIA3, 289 }; 290 291 #define for_each_pipe(__dev_priv, __p) \ 292 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) 293 294 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 295 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ 296 for_each_if((__mask) & BIT(__p)) 297 298 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 299 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 300 for_each_if ((__mask) & (1 << (__t))) 301 302 #define for_each_universal_plane(__dev_priv, __pipe, __p) \ 303 for ((__p) = 0; \ 304 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ 305 (__p)++) 306 307 #define for_each_sprite(__dev_priv, __p, __s) \ 308 for ((__s) = 0; \ 309 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 310 (__s)++) 311 312 #define for_each_port_masked(__port, __ports_mask) \ 313 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ 314 for_each_if((__ports_mask) & BIT(__port)) 315 316 #define for_each_phy_masked(__phy, __phys_mask) \ 317 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 318 for_each_if((__phys_mask) & BIT(__phy)) 319 320 #define for_each_crtc(dev, crtc) \ 321 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 322 323 #define for_each_intel_plane(dev, intel_plane) \ 324 list_for_each_entry(intel_plane, \ 325 &(dev)->mode_config.plane_list, \ 326 base.head) 327 328 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 329 list_for_each_entry(intel_plane, \ 330 &(dev)->mode_config.plane_list, \ 331 base.head) \ 332 for_each_if((plane_mask) & \ 333 drm_plane_mask(&intel_plane->base))) 334 335 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 336 list_for_each_entry(intel_plane, \ 337 &(dev)->mode_config.plane_list, \ 338 base.head) \ 339 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 340 341 #define for_each_intel_crtc(dev, intel_crtc) \ 342 list_for_each_entry(intel_crtc, \ 343 &(dev)->mode_config.crtc_list, \ 344 base.head) 345 346 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ 347 list_for_each_entry(intel_crtc, \ 348 &(dev)->mode_config.crtc_list, \ 349 base.head) \ 350 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base)) 351 352 #define for_each_intel_encoder(dev, intel_encoder) \ 353 list_for_each_entry(intel_encoder, \ 354 &(dev)->mode_config.encoder_list, \ 355 base.head) 356 357 #define for_each_intel_dp(dev, intel_encoder) \ 358 for_each_intel_encoder(dev, intel_encoder) \ 359 for_each_if(intel_encoder_is_dp(intel_encoder)) 360 361 #define for_each_intel_connector_iter(intel_connector, iter) \ 362 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 363 364 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 365 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 366 for_each_if((intel_encoder)->base.crtc == (__crtc)) 367 368 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 369 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 370 for_each_if((intel_connector)->base.encoder == (__encoder)) 371 372 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 373 for ((__i) = 0; \ 374 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 375 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 376 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 377 (__i)++) \ 378 for_each_if(plane) 379 380 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 381 for ((__i) = 0; \ 382 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 383 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 384 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 385 (__i)++) \ 386 for_each_if(plane) 387 388 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 389 for ((__i) = 0; \ 390 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 391 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 392 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 393 (__i)++) \ 394 for_each_if(crtc) 395 396 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 397 for ((__i) = 0; \ 398 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 399 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 400 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 401 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 402 (__i)++) \ 403 for_each_if(plane) 404 405 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 406 for ((__i) = 0; \ 407 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 408 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 409 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 410 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 411 (__i)++) \ 412 for_each_if(crtc) 413 414 void intel_link_compute_m_n(u16 bpp, int nlanes, 415 int pixel_clock, int link_clock, 416 struct intel_link_m_n *m_n, 417 bool constant_n); 418 bool is_ccs_modifier(u64 modifier); 419 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); 420 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 421 u32 pixel_format, u64 modifier); 422 bool intel_plane_can_remap(const struct intel_plane_state *plane_state); 423 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 424 425 void intel_plane_destroy(struct drm_plane *plane); 426 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 427 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 428 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); 429 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 430 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 431 const char *name, u32 reg, int ref_freq); 432 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 433 const char *name, u32 reg); 434 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); 435 void lpt_disable_iclkip(struct drm_i915_private *dev_priv); 436 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 437 unsigned int intel_fb_xy_to_linear(int x, int y, 438 const struct intel_plane_state *state, 439 int plane); 440 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, 441 int color_plane, unsigned int height); 442 void intel_add_fb_offsets(int *x, int *y, 443 const struct intel_plane_state *state, int plane); 444 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 445 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); 446 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 447 int intel_display_suspend(struct drm_device *dev); 448 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); 449 void intel_encoder_destroy(struct drm_encoder *encoder); 450 struct drm_display_mode * 451 intel_encoder_current_mode(struct intel_encoder *encoder); 452 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); 453 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); 454 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, 455 enum port port); 456 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 457 struct drm_file *file_priv); 458 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 459 enum pipe pipe); 460 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); 461 462 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); 463 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 464 struct intel_digital_port *dport, 465 unsigned int expected_mask); 466 int intel_get_load_detect_pipe(struct drm_connector *connector, 467 const struct drm_display_mode *mode, 468 struct intel_load_detect_pipe *old, 469 struct drm_modeset_acquire_ctx *ctx); 470 void intel_release_load_detect_pipe(struct drm_connector *connector, 471 struct intel_load_detect_pipe *old, 472 struct drm_modeset_acquire_ctx *ctx); 473 struct i915_vma * 474 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, 475 const struct i915_ggtt_view *view, 476 bool uses_fence, 477 unsigned long *out_flags); 478 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags); 479 struct drm_framebuffer * 480 intel_framebuffer_create(struct drm_i915_gem_object *obj, 481 struct drm_mode_fb_cmd2 *mode_cmd); 482 int intel_prepare_plane_fb(struct drm_plane *plane, 483 struct drm_plane_state *new_state); 484 void intel_cleanup_plane_fb(struct drm_plane *plane, 485 struct drm_plane_state *old_state); 486 487 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 488 enum pipe pipe); 489 490 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 491 const struct dpll *dpll); 492 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); 493 int lpt_get_iclkip(struct drm_i915_private *dev_priv); 494 bool intel_fuzzy_clock_check(int clock1, int clock2); 495 496 void intel_prepare_reset(struct drm_i915_private *dev_priv); 497 void intel_finish_reset(struct drm_i915_private *dev_priv); 498 void intel_dp_get_m_n(struct intel_crtc *crtc, 499 struct intel_crtc_state *pipe_config); 500 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, 501 enum link_m_n_set m_n); 502 void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp, 503 const struct intel_crtc_state *crtc_state); 504 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 505 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 506 struct dpll *best_clock); 507 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); 508 509 bool intel_crtc_active(struct intel_crtc *crtc); 510 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); 511 void hsw_enable_ips(const struct intel_crtc_state *crtc_state); 512 void hsw_disable_ips(const struct intel_crtc_state *crtc_state); 513 enum intel_display_power_domain intel_port_to_power_domain(enum port port); 514 enum intel_display_power_domain 515 intel_aux_power_domain(struct intel_digital_port *dig_port); 516 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 517 struct intel_crtc_state *pipe_config); 518 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 519 struct intel_crtc_state *crtc_state); 520 521 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center); 522 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); 523 int skl_max_scale(const struct intel_crtc_state *crtc_state, 524 u32 pixel_format); 525 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, 526 const struct intel_plane_state *plane_state); 527 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state); 528 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 529 const struct intel_plane_state *plane_state); 530 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state); 531 u32 skl_plane_stride(const struct intel_plane_state *plane_state, 532 int plane); 533 int skl_check_plane_surface(struct intel_plane_state *plane_state); 534 int i9xx_check_plane_surface(struct intel_plane_state *plane_state); 535 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); 536 unsigned int i9xx_plane_max_stride(struct intel_plane *plane, 537 u32 pixel_format, u64 modifier, 538 unsigned int rotation); 539 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); 540 541 struct intel_display_error_state * 542 intel_display_capture_error_state(struct drm_i915_private *dev_priv); 543 void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 544 struct intel_display_error_state *error); 545 546 /* modesetting */ 547 void intel_modeset_init_hw(struct drm_device *dev); 548 int intel_modeset_init(struct drm_device *dev); 549 void intel_modeset_driver_remove(struct drm_device *dev); 550 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state); 551 void intel_display_resume(struct drm_device *dev); 552 void i915_redisable_vga(struct drm_i915_private *dev_priv); 553 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv); 554 void intel_init_pch_refclk(struct drm_i915_private *dev_priv); 555 556 /* modesetting asserts */ 557 void assert_panel_unlocked(struct drm_i915_private *dev_priv, 558 enum pipe pipe); 559 void assert_pll(struct drm_i915_private *dev_priv, 560 enum pipe pipe, bool state); 561 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 562 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 563 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); 564 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) 565 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) 566 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 567 enum pipe pipe, bool state); 568 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) 569 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) 570 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); 571 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) 572 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) 573 574 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 575 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 576 * which may not necessarily be a user visible problem. This will either 577 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 578 * enable distros and users to tailor their preferred amount of i915 abrt 579 * spam. 580 */ 581 #define I915_STATE_WARN(condition, format...) ({ \ 582 int __ret_warn_on = !!(condition); \ 583 if (unlikely(__ret_warn_on)) \ 584 if (!WARN(i915_modparams.verbose_state_checks, format)) \ 585 DRM_ERROR(format); \ 586 unlikely(__ret_warn_on); \ 587 }) 588 589 #define I915_STATE_WARN_ON(x) \ 590 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 591 592 #endif 593