1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 30 enum link_m_n_set; 31 enum drm_scaling_filter; 32 struct dpll; 33 struct drm_connector; 34 struct drm_device; 35 struct drm_display_mode; 36 struct drm_encoder; 37 struct drm_file; 38 struct drm_format_info; 39 struct drm_framebuffer; 40 struct drm_i915_gem_object; 41 struct drm_i915_private; 42 struct drm_mode_fb_cmd2; 43 struct drm_modeset_acquire_ctx; 44 struct drm_plane; 45 struct drm_plane_state; 46 struct i915_address_space; 47 struct i915_ggtt_view; 48 struct intel_atomic_state; 49 struct intel_crtc; 50 struct intel_crtc_state; 51 struct intel_digital_port; 52 struct intel_dp; 53 struct intel_encoder; 54 struct intel_initial_plane_config; 55 struct intel_load_detect_pipe; 56 struct intel_plane; 57 struct intel_plane_state; 58 struct intel_remapped_info; 59 struct intel_rotation_info; 60 struct pci_dev; 61 62 enum i915_gpio { 63 GPIOA, 64 GPIOB, 65 GPIOC, 66 GPIOD, 67 GPIOE, 68 GPIOF, 69 GPIOG, 70 GPIOH, 71 __GPIOI_UNUSED, 72 GPIOJ, 73 GPIOK, 74 GPIOL, 75 GPIOM, 76 GPION, 77 GPIOO, 78 }; 79 80 /* 81 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 82 * rest have consecutive values and match the enum values of transcoders 83 * with a 1:1 transcoder -> pipe mapping. 84 */ 85 enum pipe { 86 INVALID_PIPE = -1, 87 88 PIPE_A = 0, 89 PIPE_B, 90 PIPE_C, 91 PIPE_D, 92 _PIPE_EDP, 93 94 I915_MAX_PIPES = _PIPE_EDP 95 }; 96 97 #define pipe_name(p) ((p) + 'A') 98 99 enum transcoder { 100 INVALID_TRANSCODER = -1, 101 /* 102 * The following transcoders have a 1:1 transcoder -> pipe mapping, 103 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 104 * rest have consecutive values and match the enum values of the pipes 105 * they map to. 106 */ 107 TRANSCODER_A = PIPE_A, 108 TRANSCODER_B = PIPE_B, 109 TRANSCODER_C = PIPE_C, 110 TRANSCODER_D = PIPE_D, 111 112 /* 113 * The following transcoders can map to any pipe, their enum value 114 * doesn't need to stay fixed. 115 */ 116 TRANSCODER_EDP, 117 TRANSCODER_DSI_0, 118 TRANSCODER_DSI_1, 119 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 120 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 121 122 I915_MAX_TRANSCODERS 123 }; 124 125 static inline const char *transcoder_name(enum transcoder transcoder) 126 { 127 switch (transcoder) { 128 case TRANSCODER_A: 129 return "A"; 130 case TRANSCODER_B: 131 return "B"; 132 case TRANSCODER_C: 133 return "C"; 134 case TRANSCODER_D: 135 return "D"; 136 case TRANSCODER_EDP: 137 return "EDP"; 138 case TRANSCODER_DSI_A: 139 return "DSI A"; 140 case TRANSCODER_DSI_C: 141 return "DSI C"; 142 default: 143 return "<invalid>"; 144 } 145 } 146 147 static inline bool transcoder_is_dsi(enum transcoder transcoder) 148 { 149 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 150 } 151 152 /* 153 * Global legacy plane identifier. Valid only for primary/sprite 154 * planes on pre-g4x, and only for primary planes on g4x-bdw. 155 */ 156 enum i9xx_plane_id { 157 PLANE_A, 158 PLANE_B, 159 PLANE_C, 160 }; 161 162 #define plane_name(p) ((p) + 'A') 163 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 164 165 /* 166 * Per-pipe plane identifier. 167 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 168 * number of planes per CRTC. Not all platforms really have this many planes, 169 * which means some arrays of size I915_MAX_PLANES may have unused entries 170 * between the topmost sprite plane and the cursor plane. 171 * 172 * This is expected to be passed to various register macros 173 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 174 */ 175 enum plane_id { 176 PLANE_PRIMARY, 177 PLANE_SPRITE0, 178 PLANE_SPRITE1, 179 PLANE_SPRITE2, 180 PLANE_SPRITE3, 181 PLANE_SPRITE4, 182 PLANE_SPRITE5, 183 PLANE_CURSOR, 184 185 I915_MAX_PLANES, 186 }; 187 188 #define for_each_plane_id_on_crtc(__crtc, __p) \ 189 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 190 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 191 192 #define for_each_dbuf_slice(__dev_priv, __slice) \ 193 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \ 194 for_each_if(INTEL_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice)) 195 196 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \ 197 for_each_dbuf_slice((__dev_priv), (__slice)) \ 198 for_each_if((__mask) & BIT(__slice)) 199 200 enum port { 201 PORT_NONE = -1, 202 203 PORT_A = 0, 204 PORT_B, 205 PORT_C, 206 PORT_D, 207 PORT_E, 208 PORT_F, 209 PORT_G, 210 PORT_H, 211 PORT_I, 212 213 /* tgl+ */ 214 PORT_TC1 = PORT_D, 215 PORT_TC2, 216 PORT_TC3, 217 PORT_TC4, 218 PORT_TC5, 219 PORT_TC6, 220 221 /* XE_LPD repositions D/E offsets and bitfields */ 222 PORT_D_XELPD = PORT_TC5, 223 PORT_E_XELPD, 224 225 I915_MAX_PORTS 226 }; 227 228 #define port_name(p) ((p) + 'A') 229 230 /* 231 * Ports identifier referenced from other drivers. 232 * Expected to remain stable over time 233 */ 234 static inline const char *port_identifier(enum port port) 235 { 236 switch (port) { 237 case PORT_A: 238 return "Port A"; 239 case PORT_B: 240 return "Port B"; 241 case PORT_C: 242 return "Port C"; 243 case PORT_D: 244 return "Port D"; 245 case PORT_E: 246 return "Port E"; 247 case PORT_F: 248 return "Port F"; 249 case PORT_G: 250 return "Port G"; 251 case PORT_H: 252 return "Port H"; 253 case PORT_I: 254 return "Port I"; 255 default: 256 return "<invalid>"; 257 } 258 } 259 260 enum tc_port { 261 TC_PORT_NONE = -1, 262 263 TC_PORT_1 = 0, 264 TC_PORT_2, 265 TC_PORT_3, 266 TC_PORT_4, 267 TC_PORT_5, 268 TC_PORT_6, 269 270 I915_MAX_TC_PORTS 271 }; 272 273 enum tc_port_mode { 274 TC_PORT_DISCONNECTED, 275 TC_PORT_TBT_ALT, 276 TC_PORT_DP_ALT, 277 TC_PORT_LEGACY, 278 }; 279 280 enum dpio_channel { 281 DPIO_CH0, 282 DPIO_CH1 283 }; 284 285 enum dpio_phy { 286 DPIO_PHY0, 287 DPIO_PHY1, 288 DPIO_PHY2, 289 }; 290 291 enum aux_ch { 292 AUX_CH_A, 293 AUX_CH_B, 294 AUX_CH_C, 295 AUX_CH_D, 296 AUX_CH_E, /* ICL+ */ 297 AUX_CH_F, 298 AUX_CH_G, 299 AUX_CH_H, 300 AUX_CH_I, 301 302 /* tgl+ */ 303 AUX_CH_USBC1 = AUX_CH_D, 304 AUX_CH_USBC2, 305 AUX_CH_USBC3, 306 AUX_CH_USBC4, 307 AUX_CH_USBC5, 308 AUX_CH_USBC6, 309 310 /* XE_LPD repositions D/E offsets and bitfields */ 311 AUX_CH_D_XELPD = AUX_CH_USBC5, 312 AUX_CH_E_XELPD, 313 }; 314 315 #define aux_ch_name(a) ((a) + 'A') 316 317 /* Used by dp and fdi links */ 318 struct intel_link_m_n { 319 u32 tu; 320 u32 gmch_m; 321 u32 gmch_n; 322 u32 link_m; 323 u32 link_n; 324 }; 325 326 enum phy { 327 PHY_NONE = -1, 328 329 PHY_A = 0, 330 PHY_B, 331 PHY_C, 332 PHY_D, 333 PHY_E, 334 PHY_F, 335 PHY_G, 336 PHY_H, 337 PHY_I, 338 339 I915_MAX_PHYS 340 }; 341 342 #define phy_name(a) ((a) + 'A') 343 344 enum phy_fia { 345 FIA1, 346 FIA2, 347 FIA3, 348 }; 349 350 enum hpd_pin { 351 HPD_NONE = 0, 352 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 353 HPD_CRT, 354 HPD_SDVO_B, 355 HPD_SDVO_C, 356 HPD_PORT_A, 357 HPD_PORT_B, 358 HPD_PORT_C, 359 HPD_PORT_D, 360 HPD_PORT_E, 361 HPD_PORT_TC1, 362 HPD_PORT_TC2, 363 HPD_PORT_TC3, 364 HPD_PORT_TC4, 365 HPD_PORT_TC5, 366 HPD_PORT_TC6, 367 368 HPD_NUM_PINS 369 }; 370 371 #define for_each_hpd_pin(__pin) \ 372 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 373 374 #define for_each_pipe(__dev_priv, __p) \ 375 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ 376 for_each_if(INTEL_INFO(__dev_priv)->display.pipe_mask & BIT(__p)) 377 378 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 379 for_each_pipe(__dev_priv, __p) \ 380 for_each_if((__mask) & BIT(__p)) 381 382 #define for_each_cpu_transcoder(__dev_priv, __t) \ 383 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 384 for_each_if (INTEL_INFO(__dev_priv)->display.cpu_transcoder_mask & BIT(__t)) 385 386 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 387 for_each_cpu_transcoder(__dev_priv, __t) \ 388 for_each_if ((__mask) & BIT(__t)) 389 390 #define for_each_sprite(__dev_priv, __p, __s) \ 391 for ((__s) = 0; \ 392 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 393 (__s)++) 394 395 #define for_each_port(__port) \ 396 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 397 398 #define for_each_port_masked(__port, __ports_mask) \ 399 for_each_port(__port) \ 400 for_each_if((__ports_mask) & BIT(__port)) 401 402 #define for_each_phy_masked(__phy, __phys_mask) \ 403 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 404 for_each_if((__phys_mask) & BIT(__phy)) 405 406 #define for_each_crtc(dev, crtc) \ 407 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 408 409 #define for_each_intel_plane(dev, intel_plane) \ 410 list_for_each_entry(intel_plane, \ 411 &(dev)->mode_config.plane_list, \ 412 base.head) 413 414 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 415 list_for_each_entry(intel_plane, \ 416 &(dev)->mode_config.plane_list, \ 417 base.head) \ 418 for_each_if((plane_mask) & \ 419 drm_plane_mask(&intel_plane->base)) 420 421 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 422 list_for_each_entry(intel_plane, \ 423 &(dev)->mode_config.plane_list, \ 424 base.head) \ 425 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 426 427 #define for_each_intel_crtc(dev, intel_crtc) \ 428 list_for_each_entry(intel_crtc, \ 429 &(dev)->mode_config.crtc_list, \ 430 base.head) 431 432 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ 433 list_for_each_entry(intel_crtc, \ 434 &(dev)->mode_config.crtc_list, \ 435 base.head) \ 436 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base)) 437 438 #define for_each_intel_encoder(dev, intel_encoder) \ 439 list_for_each_entry(intel_encoder, \ 440 &(dev)->mode_config.encoder_list, \ 441 base.head) 442 443 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 444 list_for_each_entry(intel_encoder, \ 445 &(dev)->mode_config.encoder_list, \ 446 base.head) \ 447 for_each_if((encoder_mask) & \ 448 drm_encoder_mask(&intel_encoder->base)) 449 450 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \ 451 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 452 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \ 453 intel_encoder_can_psr(intel_encoder)) 454 455 #define for_each_intel_dp(dev, intel_encoder) \ 456 for_each_intel_encoder(dev, intel_encoder) \ 457 for_each_if(intel_encoder_is_dp(intel_encoder)) 458 459 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \ 460 for_each_intel_encoder((dev), (intel_encoder)) \ 461 for_each_if(intel_encoder_can_psr(intel_encoder)) 462 463 #define for_each_intel_connector_iter(intel_connector, iter) \ 464 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 465 466 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 467 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 468 for_each_if((intel_encoder)->base.crtc == (__crtc)) 469 470 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 471 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 472 for_each_if((intel_connector)->base.encoder == (__encoder)) 473 474 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 475 for ((__i) = 0; \ 476 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 477 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 478 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 479 (__i)++) \ 480 for_each_if(plane) 481 482 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 483 for ((__i) = 0; \ 484 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 485 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 486 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 487 (__i)++) \ 488 for_each_if(plane) 489 490 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 491 for ((__i) = 0; \ 492 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 493 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 494 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 495 (__i)++) \ 496 for_each_if(crtc) 497 498 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 499 for ((__i) = 0; \ 500 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 501 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 502 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 503 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 504 (__i)++) \ 505 for_each_if(plane) 506 507 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 508 for ((__i) = 0; \ 509 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 510 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 511 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 512 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 513 (__i)++) \ 514 for_each_if(crtc) 515 516 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 517 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 518 (__i) >= 0 && \ 519 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 520 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 521 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 522 (__i)--) \ 523 for_each_if(crtc) 524 525 #define intel_atomic_crtc_state_for_each_plane_state( \ 526 plane, plane_state, \ 527 crtc_state) \ 528 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 529 ((crtc_state)->uapi.plane_mask)) \ 530 for_each_if ((plane_state = \ 531 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) 532 533 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 534 for ((__i) = 0; \ 535 (__i) < (__state)->base.num_connector; \ 536 (__i)++) \ 537 for_each_if ((__state)->base.connectors[__i].ptr && \ 538 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 539 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 540 541 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 542 struct intel_crtc *crtc); 543 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 544 u8 active_pipes); 545 void intel_link_compute_m_n(u16 bpp, int nlanes, 546 int pixel_clock, int link_clock, 547 struct intel_link_m_n *m_n, 548 bool constant_n, bool fec_enable); 549 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 550 u32 pixel_format, u64 modifier); 551 enum drm_mode_status 552 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 553 const struct drm_display_mode *mode, 554 bool bigjoiner); 555 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 556 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 557 558 void intel_plane_destroy(struct drm_plane *plane); 559 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); 560 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state); 561 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 562 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 563 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); 564 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 565 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 566 const char *name, u32 reg, int ref_freq); 567 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 568 const char *name, u32 reg); 569 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 570 unsigned int intel_fb_xy_to_linear(int x, int y, 571 const struct intel_plane_state *state, 572 int plane); 573 void intel_add_fb_offsets(int *x, int *y, 574 const struct intel_plane_state *state, int plane); 575 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 576 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); 577 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 578 int intel_display_suspend(struct drm_device *dev); 579 void intel_encoder_destroy(struct drm_encoder *encoder); 580 struct drm_display_mode * 581 intel_encoder_current_mode(struct intel_encoder *encoder); 582 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); 583 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); 584 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy); 585 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, 586 enum port port); 587 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 588 struct drm_file *file_priv); 589 590 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 591 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 592 struct intel_digital_port *dig_port, 593 unsigned int expected_mask); 594 int intel_get_load_detect_pipe(struct drm_connector *connector, 595 struct intel_load_detect_pipe *old, 596 struct drm_modeset_acquire_ctx *ctx); 597 void intel_release_load_detect_pipe(struct drm_connector *connector, 598 struct intel_load_detect_pipe *old, 599 struct drm_modeset_acquire_ctx *ctx); 600 struct drm_framebuffer * 601 intel_framebuffer_create(struct drm_i915_gem_object *obj, 602 struct drm_mode_fb_cmd2 *mode_cmd); 603 604 bool intel_fuzzy_clock_check(int clock1, int clock2); 605 606 void intel_display_prepare_reset(struct drm_i915_private *dev_priv); 607 void intel_display_finish_reset(struct drm_i915_private *dev_priv); 608 void intel_dp_get_m_n(struct intel_crtc *crtc, 609 struct intel_crtc_state *pipe_config); 610 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, 611 enum link_m_n_set m_n); 612 void ilk_get_fdi_m_n_config(struct intel_crtc *crtc, 613 struct intel_crtc_state *pipe_config); 614 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 615 struct intel_crtc_state *pipe_config); 616 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 617 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); 618 void hsw_enable_ips(const struct intel_crtc_state *crtc_state); 619 void hsw_disable_ips(const struct intel_crtc_state *crtc_state); 620 enum intel_display_power_domain intel_port_to_power_domain(enum port port); 621 enum intel_display_power_domain 622 intel_aux_power_domain(struct intel_digital_port *dig_port); 623 enum intel_display_power_domain 624 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch); 625 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 626 struct intel_crtc_state *crtc_state); 627 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); 628 629 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); 630 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state); 631 632 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state); 633 634 struct intel_encoder * 635 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 636 const struct intel_crtc_state *crtc_state); 637 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 638 struct intel_plane *plane); 639 640 void intel_display_driver_register(struct drm_i915_private *i915); 641 void intel_display_driver_unregister(struct drm_i915_private *i915); 642 643 /* modesetting */ 644 bool intel_modeset_probe_defer(struct pci_dev *pdev); 645 void intel_modeset_init_hw(struct drm_i915_private *i915); 646 int intel_modeset_init_noirq(struct drm_i915_private *i915); 647 int intel_modeset_init_nogem(struct drm_i915_private *i915); 648 int intel_modeset_init(struct drm_i915_private *i915); 649 void intel_modeset_driver_remove(struct drm_i915_private *i915); 650 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915); 651 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915); 652 void intel_display_resume(struct drm_device *dev); 653 int intel_modeset_all_pipes(struct intel_atomic_state *state); 654 655 /* modesetting asserts */ 656 void assert_transcoder(struct drm_i915_private *dev_priv, 657 enum transcoder cpu_transcoder, bool state); 658 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true) 659 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false) 660 661 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 662 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 663 * which may not necessarily be a user visible problem. This will either 664 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 665 * enable distros and users to tailor their preferred amount of i915 abrt 666 * spam. 667 */ 668 #define I915_STATE_WARN(condition, format...) ({ \ 669 int __ret_warn_on = !!(condition); \ 670 if (unlikely(__ret_warn_on)) \ 671 if (!WARN(i915_modparams.verbose_state_checks, format)) \ 672 DRM_ERROR(format); \ 673 unlikely(__ret_warn_on); \ 674 }) 675 676 #define I915_STATE_WARN_ON(x) \ 677 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 678 679 #endif 680