1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 30 #include "i915_reg_defs.h" 31 #include "intel_display_limits.h" 32 33 enum drm_scaling_filter; 34 struct dpll; 35 struct drm_atomic_state; 36 struct drm_connector; 37 struct drm_device; 38 struct drm_display_mode; 39 struct drm_encoder; 40 struct drm_file; 41 struct drm_format_info; 42 struct drm_framebuffer; 43 struct drm_i915_gem_object; 44 struct drm_i915_private; 45 struct drm_mode_fb_cmd2; 46 struct drm_modeset_acquire_ctx; 47 struct drm_plane; 48 struct drm_plane_state; 49 struct i915_address_space; 50 struct i915_gtt_view; 51 struct intel_atomic_state; 52 struct intel_crtc; 53 struct intel_crtc_state; 54 struct intel_digital_port; 55 struct intel_dp; 56 struct intel_encoder; 57 struct intel_initial_plane_config; 58 struct intel_link_m_n; 59 struct intel_plane; 60 struct intel_plane_state; 61 struct intel_power_domain_mask; 62 struct intel_remapped_info; 63 struct intel_rotation_info; 64 struct pci_dev; 65 struct work_struct; 66 67 68 #define pipe_name(p) ((p) + 'A') 69 70 static inline const char *transcoder_name(enum transcoder transcoder) 71 { 72 switch (transcoder) { 73 case TRANSCODER_A: 74 return "A"; 75 case TRANSCODER_B: 76 return "B"; 77 case TRANSCODER_C: 78 return "C"; 79 case TRANSCODER_D: 80 return "D"; 81 case TRANSCODER_EDP: 82 return "EDP"; 83 case TRANSCODER_DSI_A: 84 return "DSI A"; 85 case TRANSCODER_DSI_C: 86 return "DSI C"; 87 default: 88 return "<invalid>"; 89 } 90 } 91 92 static inline bool transcoder_is_dsi(enum transcoder transcoder) 93 { 94 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 95 } 96 97 /* 98 * Global legacy plane identifier. Valid only for primary/sprite 99 * planes on pre-g4x, and only for primary planes on g4x-bdw. 100 */ 101 enum i9xx_plane_id { 102 PLANE_A, 103 PLANE_B, 104 PLANE_C, 105 }; 106 107 #define plane_name(p) ((p) + 'A') 108 #define sprite_name(p, s) ((p) * DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 109 110 #define for_each_plane_id_on_crtc(__crtc, __p) \ 111 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 112 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 113 114 #define for_each_dbuf_slice(__dev_priv, __slice) \ 115 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \ 116 for_each_if(INTEL_INFO(__dev_priv)->display->dbuf.slice_mask & BIT(__slice)) 117 118 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \ 119 for_each_dbuf_slice((__dev_priv), (__slice)) \ 120 for_each_if((__mask) & BIT(__slice)) 121 122 #define port_name(p) ((p) + 'A') 123 124 /* 125 * Ports identifier referenced from other drivers. 126 * Expected to remain stable over time 127 */ 128 static inline const char *port_identifier(enum port port) 129 { 130 switch (port) { 131 case PORT_A: 132 return "Port A"; 133 case PORT_B: 134 return "Port B"; 135 case PORT_C: 136 return "Port C"; 137 case PORT_D: 138 return "Port D"; 139 case PORT_E: 140 return "Port E"; 141 case PORT_F: 142 return "Port F"; 143 case PORT_G: 144 return "Port G"; 145 case PORT_H: 146 return "Port H"; 147 case PORT_I: 148 return "Port I"; 149 default: 150 return "<invalid>"; 151 } 152 } 153 154 enum tc_port { 155 TC_PORT_NONE = -1, 156 157 TC_PORT_1 = 0, 158 TC_PORT_2, 159 TC_PORT_3, 160 TC_PORT_4, 161 TC_PORT_5, 162 TC_PORT_6, 163 164 I915_MAX_TC_PORTS 165 }; 166 167 enum aux_ch { 168 AUX_CH_NONE = -1, 169 170 AUX_CH_A, 171 AUX_CH_B, 172 AUX_CH_C, 173 AUX_CH_D, 174 AUX_CH_E, /* ICL+ */ 175 AUX_CH_F, 176 AUX_CH_G, 177 AUX_CH_H, 178 AUX_CH_I, 179 180 /* tgl+ */ 181 AUX_CH_USBC1 = AUX_CH_D, 182 AUX_CH_USBC2, 183 AUX_CH_USBC3, 184 AUX_CH_USBC4, 185 AUX_CH_USBC5, 186 AUX_CH_USBC6, 187 188 /* XE_LPD repositions D/E offsets and bitfields */ 189 AUX_CH_D_XELPD = AUX_CH_USBC5, 190 AUX_CH_E_XELPD, 191 }; 192 193 #define aux_ch_name(a) ((a) + 'A') 194 195 enum phy { 196 PHY_NONE = -1, 197 198 PHY_A = 0, 199 PHY_B, 200 PHY_C, 201 PHY_D, 202 PHY_E, 203 PHY_F, 204 PHY_G, 205 PHY_H, 206 PHY_I, 207 208 I915_MAX_PHYS 209 }; 210 211 #define phy_name(a) ((a) + 'A') 212 213 enum phy_fia { 214 FIA1, 215 FIA2, 216 FIA3, 217 }; 218 219 #define for_each_hpd_pin(__pin) \ 220 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 221 222 #define for_each_pipe(__dev_priv, __p) \ 223 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ 224 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p)) 225 226 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 227 for_each_pipe(__dev_priv, __p) \ 228 for_each_if((__mask) & BIT(__p)) 229 230 #define for_each_cpu_transcoder(__dev_priv, __t) \ 231 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 232 for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t)) 233 234 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 235 for_each_cpu_transcoder(__dev_priv, __t) \ 236 for_each_if ((__mask) & BIT(__t)) 237 238 #define for_each_sprite(__dev_priv, __p, __s) \ 239 for ((__s) = 0; \ 240 (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 241 (__s)++) 242 243 #define for_each_port(__port) \ 244 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 245 246 #define for_each_port_masked(__port, __ports_mask) \ 247 for_each_port(__port) \ 248 for_each_if((__ports_mask) & BIT(__port)) 249 250 #define for_each_phy_masked(__phy, __phys_mask) \ 251 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 252 for_each_if((__phys_mask) & BIT(__phy)) 253 254 #define for_each_crtc(dev, crtc) \ 255 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 256 257 #define for_each_intel_plane(dev, intel_plane) \ 258 list_for_each_entry(intel_plane, \ 259 &(dev)->mode_config.plane_list, \ 260 base.head) 261 262 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 263 list_for_each_entry(intel_plane, \ 264 &(dev)->mode_config.plane_list, \ 265 base.head) \ 266 for_each_if((plane_mask) & \ 267 drm_plane_mask(&intel_plane->base)) 268 269 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 270 list_for_each_entry(intel_plane, \ 271 &(dev)->mode_config.plane_list, \ 272 base.head) \ 273 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 274 275 #define for_each_intel_crtc(dev, intel_crtc) \ 276 list_for_each_entry(intel_crtc, \ 277 &(dev)->mode_config.crtc_list, \ 278 base.head) 279 280 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \ 281 list_for_each_entry(intel_crtc, \ 282 &(dev)->mode_config.crtc_list, \ 283 base.head) \ 284 for_each_if((pipe_mask) & BIT(intel_crtc->pipe)) 285 286 #define for_each_intel_encoder(dev, intel_encoder) \ 287 list_for_each_entry(intel_encoder, \ 288 &(dev)->mode_config.encoder_list, \ 289 base.head) 290 291 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 292 list_for_each_entry(intel_encoder, \ 293 &(dev)->mode_config.encoder_list, \ 294 base.head) \ 295 for_each_if((encoder_mask) & \ 296 drm_encoder_mask(&intel_encoder->base)) 297 298 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \ 299 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 300 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \ 301 intel_encoder_can_psr(intel_encoder)) 302 303 #define for_each_intel_dp(dev, intel_encoder) \ 304 for_each_intel_encoder(dev, intel_encoder) \ 305 for_each_if(intel_encoder_is_dp(intel_encoder)) 306 307 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \ 308 for_each_intel_encoder((dev), (intel_encoder)) \ 309 for_each_if(intel_encoder_can_psr(intel_encoder)) 310 311 #define for_each_intel_connector_iter(intel_connector, iter) \ 312 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 313 314 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 315 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 316 for_each_if((intel_encoder)->base.crtc == (__crtc)) 317 318 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 319 for ((__i) = 0; \ 320 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 321 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 322 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 323 (__i)++) \ 324 for_each_if(plane) 325 326 #define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \ 327 for ((__i) = 0; \ 328 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 329 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 330 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \ 331 (__i)++) \ 332 for_each_if(crtc) 333 334 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 335 for ((__i) = 0; \ 336 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 337 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 338 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 339 (__i)++) \ 340 for_each_if(plane) 341 342 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 343 for ((__i) = 0; \ 344 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 345 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 346 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 347 (__i)++) \ 348 for_each_if(crtc) 349 350 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 351 for ((__i) = 0; \ 352 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 353 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 354 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 355 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 356 (__i)++) \ 357 for_each_if(plane) 358 359 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 360 for ((__i) = 0; \ 361 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 362 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 363 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 364 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 365 (__i)++) \ 366 for_each_if(crtc) 367 368 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 369 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 370 (__i) >= 0 && \ 371 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 372 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 373 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 374 (__i)--) \ 375 for_each_if(crtc) 376 377 #define intel_atomic_crtc_state_for_each_plane_state( \ 378 plane, plane_state, \ 379 crtc_state) \ 380 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 381 ((crtc_state)->uapi.plane_mask)) \ 382 for_each_if ((plane_state = \ 383 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) 384 385 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 386 for ((__i) = 0; \ 387 (__i) < (__state)->base.num_connector; \ 388 (__i)++) \ 389 for_each_if ((__state)->base.connectors[__i].ptr && \ 390 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 391 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 392 393 int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 394 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 395 struct intel_crtc *crtc); 396 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 397 u8 active_pipes); 398 void intel_link_compute_m_n(u16 bpp, int nlanes, 399 int pixel_clock, int link_clock, 400 struct intel_link_m_n *m_n, 401 bool fec_enable); 402 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 403 u32 pixel_format, u64 modifier); 404 enum drm_mode_status 405 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 406 const struct drm_display_mode *mode, 407 bool bigjoiner); 408 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 409 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 410 bool is_trans_port_sync_master(const struct intel_crtc_state *state); 411 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state); 412 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state); 413 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state); 414 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state); 415 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); 416 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, 417 const struct intel_crtc_state *pipe_config, 418 bool fastset); 419 420 void intel_plane_destroy(struct drm_plane *plane); 421 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 422 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 423 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); 424 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state); 425 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 426 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 427 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 428 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 429 const char *name, u32 reg, int ref_freq); 430 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 431 const char *name, u32 reg); 432 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 433 unsigned int intel_fb_xy_to_linear(int x, int y, 434 const struct intel_plane_state *state, 435 int plane); 436 void intel_add_fb_offsets(int *x, int *y, 437 const struct intel_plane_state *state, int plane); 438 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 439 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); 440 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 441 void intel_encoder_destroy(struct drm_encoder *encoder); 442 struct drm_display_mode * 443 intel_encoder_current_mode(struct intel_encoder *encoder); 444 void intel_encoder_get_config(struct intel_encoder *encoder, 445 struct intel_crtc_state *crtc_state); 446 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); 447 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); 448 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy); 449 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, 450 enum port port); 451 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 452 struct drm_file *file_priv); 453 454 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 455 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 456 struct intel_digital_port *dig_port, 457 unsigned int expected_mask); 458 struct drm_framebuffer * 459 intel_framebuffer_create(struct drm_i915_gem_object *obj, 460 struct drm_mode_fb_cmd2 *mode_cmd); 461 462 bool intel_fuzzy_clock_check(int clock1, int clock2); 463 464 void intel_zero_m_n(struct intel_link_m_n *m_n); 465 void intel_set_m_n(struct drm_i915_private *i915, 466 const struct intel_link_m_n *m_n, 467 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 468 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 469 void intel_get_m_n(struct drm_i915_private *i915, 470 struct intel_link_m_n *m_n, 471 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 472 i915_reg_t link_m_reg, i915_reg_t link_n_reg); 473 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 474 enum transcoder transcoder); 475 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 476 enum transcoder cpu_transcoder, 477 const struct intel_link_m_n *m_n); 478 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 479 enum transcoder cpu_transcoder, 480 const struct intel_link_m_n *m_n); 481 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 482 enum transcoder cpu_transcoder, 483 struct intel_link_m_n *m_n); 484 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 485 enum transcoder cpu_transcoder, 486 struct intel_link_m_n *m_n); 487 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 488 struct intel_crtc_state *pipe_config); 489 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 490 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config); 491 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port); 492 enum intel_display_power_domain 493 intel_aux_power_domain(struct intel_digital_port *dig_port); 494 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 495 struct intel_crtc_state *crtc_state); 496 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); 497 498 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc); 499 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state); 500 501 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state); 502 503 struct intel_encoder * 504 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 505 const struct intel_crtc_state *crtc_state); 506 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 507 struct intel_plane *plane); 508 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 509 struct intel_plane_state *plane_state, 510 bool visible); 511 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state); 512 513 void intel_update_watermarks(struct drm_i915_private *i915); 514 515 /* modesetting */ 516 int intel_modeset_all_pipes(struct intel_atomic_state *state, 517 const char *reason); 518 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 519 struct intel_power_domain_mask *old_domains); 520 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 521 struct intel_power_domain_mask *domains); 522 523 /* interface for intel_display_driver.c */ 524 void intel_setup_outputs(struct drm_i915_private *i915); 525 int intel_initial_commit(struct drm_device *dev); 526 void intel_panel_sanitize_ssc(struct drm_i915_private *i915); 527 void intel_update_czclk(struct drm_i915_private *i915); 528 void intel_atomic_helper_free_state_worker(struct work_struct *work); 529 enum drm_mode_status intel_mode_valid(struct drm_device *dev, 530 const struct drm_display_mode *mode); 531 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, 532 bool nonblock); 533 534 void intel_hpd_poll_fini(struct drm_i915_private *i915); 535 536 /* modesetting asserts */ 537 void assert_transcoder(struct drm_i915_private *dev_priv, 538 enum transcoder cpu_transcoder, bool state); 539 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true) 540 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false) 541 542 /* 543 * Use I915_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw state sanity 544 * checks to check for unexpected conditions which may not necessarily be a user 545 * visible problem. This will either WARN() or DRM_ERROR() depending on the 546 * verbose_state_checks module param, to enable distros and users to tailor 547 * their preferred amount of i915 abrt spam. 548 */ 549 #define I915_STATE_WARN(__i915, condition, format...) ({ \ 550 struct drm_device *drm = &(__i915)->drm; \ 551 int __ret_warn_on = !!(condition); \ 552 if (unlikely(__ret_warn_on)) \ 553 if (!drm_WARN(drm, i915_modparams.verbose_state_checks, format)) \ 554 drm_err(drm, format); \ 555 unlikely(__ret_warn_on); \ 556 }) 557 558 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915); 559 560 #endif 561